JPH02265382A - Noise reduction circuit for chrominance signal - Google Patents

Abstract

PURPOSE:To apply noise reduction processing with a different system from a luminance signal by selecting not 3 primary colors R, G, B but 2 kinds of color difference signals (R-Y, B-Y or the like) as color signals of processing object in a noise reduction circuit of a chrominance signal placed in a television receiver. CONSTITUTION:Color difference signals R-Y, B-Y being an object of noise reduction fed to input terminals 1a, 1b are subjected to subtraction by adjacent inter-field difference of processed high level suppression in subtraction circuits 2a, 2b and become the color difference signals R-Y, B-Y after noise reduction is applied and are fed to output terminals Oa, Ob and an input terminal of a multiplex parallel/serial conversion circuit 3. Thus, the inter-frame correlation is used as to the luminance signal with high visual sensitivity to apply noise reduction processing with a comparatively high cost and the inter-field correlation is used for the color signal with low visual sensitivity to apply noise reduction processing with a low cost.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a color signal noise reduction circuit installed in a television receiver.

(Prior Art) In television receivers called EDTV or IDTV, received analog television video signals are
High image quality is achieved by converting to a digital video signal, performing various digital image processing such as contour compensation, scanning line interpolation, and noise reduction in addition to high-precision Y/C separation, and then converting it back to an analog video signal. That is planned.

Regarding the above noise reduction processing, a noise reduction circuit that utilizes correlation between adjacent frames has been developed.

As shown in FIG. 18, this noise reduction circuit is composed of subtraction circuits 141 and 142, a one-frame delay memory 143, and a motion adaptive coefficient generation circuit 144.

The input terminal IN receives Y/Y from the received television video signal.
C-separated luminance signal (Y) and color difference signal (R-Y),
Component digital video signals such as (B-Y) or three primary color signals (R, G, B) are supplied.

The video signal of the current frame appearing at this input terminal IN and 1
A subtraction circuit 141 subtracts the noise-reduced video signal of the immediately previous frame output from the frame delay memory 143 to generate a difference signal between adjacent frames. This difference signal between adjacent frames has a correlation of 10
If it is 0%, that is, if there is no movement at all on the display screen, it is nothing but a noise component.

Therefore, by subtracting this inter-adjacent frame difference signal from the video signal of the current frame in the subtraction circuit 142,
A video signal with reduced noise can be generated.

In reality, a motion component accompanying the collapse of the correlation between adjacent frames is mixed into the difference signal between adjacent frames. in this case,
The lower the level of the difference signal between adjacent frames, the higher the probability that it is a noise component, and the higher the level, the higher the probability that it is a motion component. Therefore, the motion adaptive coefficient generation circuit 144
In this step, a noise component on the low level side is extracted by multiplying by a coefficient that suppresses the high level side of the difference signal between adjacent frames. In the subtraction circuit 142, the extracted noise component is subtracted from the video signal of the original frame appearing at the input terminal IN, thereby generating a noise-reduced video signal, which is supplied to the output terminal OUT.

(Problems to be Solved by the Invention) In the conventional noise reduction circuit that utilizes the correlation between adjacent frames, the luminance signal (Y), color difference signal (R-Y), (
A noise reduction circuit having a configuration as shown in FIG. 18 is installed for each of the three component video signals such as B-Y). Therefore, three large-capacity and expensive frame memories are required, which raises the problem of increased manufacturing costs.

(Means for Solving the Problems) Firstly, the color signal noise reduction circuit according to the present invention uses two types of color difference signals (R-Y, B) instead of the three primary colors R, G, and B as color signals to be processed. -Y, etc.), it is possible to apply noise reduction processing using a method different from that for luminance signals.

Second, the color signal noise reduction circuit according to the present invention performs noise reduction processing on the color signal using an inter-adjacent field difference signal based on the correlation between adjacent fields instead of the correlation between adjacent frames. By replacing the frame memory for delay with field memory, the capacity is reduced by half, and the manufacturing cost is reduced.

Thirdly, the color signal noise reduction circuit according to the present invention thins out each of the two types of color difference signals every predetermined number of pixels, performs time division multiplexing, delays by one field, and then demultiplexes the two types of color difference signals. By doing so, the memory capacity for delay is further compressed and the manufacturing cost is further reduced.

Fourthly, the color signal noise reduction circuit according to the present invention performs parallel/serial conversion by time division multiplexing on the upper bit portion and lower bit portion of each pixel signal to be multiplexed, and delays the signal by one field. By subsequently performing serial/parallel conversion and restoring the pixel signal to the original bit width, the manufacturing cost can be reduced due to the compression of the bit width of the memory.

Fifth, the noise reduction circuit of the present invention performs high-level suppression processing to suppress the high-level side of the difference signal between adjacent fields of the color difference signal, thereby suppressing the effects of malfunctions caused by the collapse of the correlation between adjacent fields. Configured to remove.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

(Embodiment) FIG. 1 is a block diagram showing the configuration of a color signal noise reduction circuit according to an embodiment of the present invention, where (a) and Ib are color difference signals (R-Y) to be subjected to noise reduction.

(B-Y) input terminal, Ic is field pulse input terminal, la, lb are low-pass filter circuits, 2a, 2b are subtraction circuits, 3 is multiplexing/parallel/serial conversion circuit, 4 is 262
Line delay memory 5 is a 1 line delay memory. Further, 6 is a switch, 7 is a demultiplexing/serial/parallel conversion circuit, 8a and 8b are sampling circuits, 9a and 9b are subtraction circuits, 10a and 10b are high level suppression processing circuits, Oa,
Ob is an output terminal for a color difference signal that has been subjected to noise reduction processing.

Input terminals 1a and Ib each receive 8-bit wide digital color difference signals (R-Y) and (B-Y) sampled at a frequency (4fsc) four times that of the carrier color signal, which are the colors to be noise-reduced. Supplied as a signal. The color difference signal (R-Y) to be noise-reduced supplied to the input terminal 1a is subjected to subtraction by the difference between adjacent fields that has been subjected to high-level suppression processing in the subtraction circuit 2a, and is converted into a noise-reduced color difference signal (R-Y).
-Y) and is supplied to the output terminal Oa and one input terminal of the multiplexing/parallel/serial conversion circuit 3. Similarly, the color difference signal (B-Y
) is subjected to subtraction by the difference between adjacent fields that has been subjected to high-level suppression processing in the subtraction circuit 2b, and becomes a noise-reduced color difference signal (B-Y), which is then sent to the output terminal ob and the other side of the multiplexing/parallel/serial conversion circuit 3. is supplied to the input terminal of

The color difference signals (R-Y) and (B-Y) supplied to each input terminal of the multiplexing/parallel/serial conversion circuit 3 are extracted in 4-pixel jumps, and the color difference signals are time-division multiplexed. At the same time, the upper 4 bits and lower 4 bits of each pixel to be multiplexed are also subjected to parallel/serial conversion by time division multiplexing, thereby converting them into a multiplexed serial color difference signal. This multiplexed serial color difference signal is delayed by one field by a 262-line delay memory 4, a one-line delay memory 5, and a switch 6 that is switched every other field, and then is supplied to a demultiplexing/serial/parallel conversion circuit 7. be done.

The multiplexed serial color difference signal supplied to the demultiplexing/serial/parallel conversion circuit 7 undergoes demultiplexing and serial/parallel conversion of the color difference signals, thereby converting the original bit width into a color difference signal having a time width equal to the number of pixels. The signal is restored into signals (RY) and (B-Y) and supplied to one input terminal of subtraction circuits 9a and 9b. The other input terminals of the subtracting circuits 9a and 9b receive color difference signals (R-Y) of the current field, which are extracted every fourth pixel in the sampling circuits 8a and 8b and held for a time width corresponding to the number of four pixels. B-Y) is supplied. Therefore, the subtracting circuits 9a and 9b output adjacent field difference signals Δ(R-Y) and Δ(B-Y) of the color difference signal based on the difference between the color difference signal of the current field and the color difference signal of the immediately previous field.

These adjacent field difference signals Δ(RY) and Δ(B-Y
) is subjected to high-level suppression in each of high-level suppression processing circuits 10a and 1ob, and then supplied to one input terminal of subtraction circuits 2a and 2b. Subtraction circuits 2a and 2
The other input terminal of b is supplied with the color difference signals (R-Y) and (B-Y) of the current field on input terminals Ia and Ib. As a result, the subtraction circuits 2a and 2b each subtract the high-level suppression-processed inter-field difference signal from the current field color difference signal, resulting in a current field noise-reduced color difference signal (R-\).

(B-Y) and is output to each of the output terminals Oa and ob.

FIG. 2 is a block diagram showing the configuration of the multiplexing/parallel/serial conversion circuit 3 of FIG. 1.

This multiplexing/parallel/serial conversion circuit 3 has input terminals 21a for color difference signals (R-Y) and (B-Y) that have undergone noise reduction processing.
, 21b, and a latch circuit 22a.

22b, 25 and multiplexer 2 for parallel/serial conversion
3a, 23b, a multiplexer 24 for multiplexing color difference signals, and an output terminal 26 for multiplexed serial color difference signals.

As shown in waveforms (B) and (C) of FIG. 6, the input terminals 21a and 21b each receive an 8-bit wide digital color difference signal (R-Y) sampled with a sampling clock having a frequency of 4 fsc. (BY) is supplied. However, in FIG. 6, for convenience of illustration, the color difference pixel signal (RY) is shown.

(B-Y) are simply displayed as R and B, and arithmetic numbers 1, 2, 3, etc. indicating sampling serial numbers are added to these color difference pixel signals R and B. . These color difference pixel signal groups have the waveform (
The middle three pixels are thinned out as shown in waveforms (E) and (F) by being held in the launch circuits 22a and 22b in 4-pixel jumps in synchronization with the clock signal of frequency fsc shown in D). A group of color difference pixel signals (R1, R5, R9...), both expanded to a width of 4 pixels, (B1.B5゜B
9...). These color difference pixel signal groups (R1,
R5, R9...), (Bl, B5゜B9...
) are separated into an upper bit part and a lower bit part each having a width of 4 bits, and are connected to multiplexers 23a and 23b.
multiplexers 23a and 23, respectively.
b is a group of color difference pixel signals R1, B having a width of 4 pixels in synchronization with a clock signal having a frequency of 4fsc shown in the waveform (A) of FIG.
By alternately selecting and outputting the upper bit portions RIH, BIH... and the lower focused portions RIL, BIL... of l..., parallel / Create a serially converted color difference pixel signal group element. This parallel/serial converted color difference pixel signal group is sent to a multiplexer 24 which alternately selects and outputs the outputs of multiplexers 23a and 23b in synchronization with a clock signal of frequency 2fsc, as shown in waveform (1) in FIG. The color difference signals are multiplexed with each other, resulting in a multiplexed serial color difference signal as shown in waveform (J). This multiplexed serial color difference signal is launched into a launch circuit 25 in synchronization with a clock signal having a frequency of 4 fsc, and is supplied to an output terminal 26.

In this way, by compressing the 8-bit width color difference signal to 4-bit width by parallel/serial conversion, the 262-bit width of the subsequent stage
The line delay memory can be configured with a general-purpose FIFO for image processing with a capacity of 1 Mbit and a width of 4 bits. In other words, in the case of an NTSC television video signal, the total number of pixels obtained by sampling at a frequency of 4 fsc is 910 per line, so the number of columns in order to provide a delay of 1 field (262 lines) is 910 x 2.
62 = 238,420 stages, and if each stage is configured with a 4-pin width, the required total bit/7-bit capacity is 238° 420 x 4
=953.680 bits. Therefore, by allocating one general-purpose FIFO with a capacity of i1M bits, 2
The 62-line delay memory 4 can be constructed at low cost.

FIG. 3 is a block diagram showing the configuration of the demultiplexing/serial/parallel conversion circuit 7 of FIG. 1.

This demultiplexing/serial/parallel conversion circuit 7 has a frequency of 4 fs.
latch circuits 32, 33, and 34 that hold signals in synchronization with the clock signal of c, and 263 line interpolation circuits 35a, 3
5b, latch circuits 36a and 36b that hold signals in synchronization with a clock signal of frequency rsc, and output terminals 37a and 37b for color difference signals that have been demultiplexed and parallel-converted.

At the input terminal 31, as shown in the waveform (a) of FIG.
Multiplexed serial color difference pixel signal group RIH, RI arranged at a sampling period equivalent to fsc and delayed by one field
L, BIH, BIL, R5H.

R5L, B5H, B5L... are supplied. This pixel signal group is sequentially held in the latch circuits 32, 33 and 34 in synchronization with a clock signal having a frequency of 4 fsc, resulting in the waveform shown in FIG. 7 (b).

As shown in (c) and (d), the signal is delayed by a sampling period equivalent to 4 fsc. Through serial/parallel conversion in which the outputs before and after the final stage latch circuit 34 are combined as an 8-bit width lower part and an upper part, an 8-bit width color difference signal R1 is generated as shown in the waveform (D) in FIG. , Bl
, R5, B5, . . . and supplied to the 263-line interpolation circuit 35a. Similarly, the first stage latch circuit 32
As a result of serial/parallel conversion in which the outputs before and after are combined as an 8-bit width lower part and an upper part, an 8-bit width color difference signal Bl is generated, as shown in waveform (E) in FIG.

The signals are restored to R5, B5, . . . and supplied to the 263-line interpolation circuit 35b. 263 line interpolation circuit 35a, 3
5b, the delay period of 262 lines performed every other field is left unchanged, and the delay period of 263 lines is interpolated. To be exact, 26
In addition to the above-mentioned processing in each of the 3-line interpolation circuits 35a and 35b, a delay twice the sampling period equivalent to 4fsc is added, resulting in waveforms (F) and (G) in FIG.
) is output. These waveforms are held by launch circuits 36a and 36b that operate at a sampling period equivalent to rsc, and the color difference signals are demultiplexed and the color difference pixel signals R1, 4 times the width of the color difference pixel signal before multiplexing are generated. R5,R
9...and Bl, B5°B9... are restored.

FIG. 4 shows the 263 line interpolation circuits 35a and 35 of FIG.
FIG. 3 is a block diagram representatively illustrating the configuration of FIG.

This 263-line interpolation circuit 35a has an input terminal 41 for the restored 8-bit wide color difference signal (R-Y), and four cascade-connected terminals each holding a signal in synchronization with a clock signal of frequency 4Esc. Latch circuit 42, 43.44
and 45, an adder circuit 46, a switch 47, and an output terminal 48.

The switch 47 is set to 263 by the field pulse FP.
It is switched to the lower side of the diagram for the period of line delay,
The period for delaying 262 lines is switched to the upper side of the figure. Therefore, during the 262-line delay period, the color difference signal (R-Y) at the point of interest A between the latch circuits 43 and 44 is supplied to the output terminal 48 via the switch 47, and is delayed by only 2 sampling periods. The signal is output from the H.263 line interpolation circuit 35a. On the other hand, during the 263-line delay period, the average value of the color difference pixel signals before and after two sampling periods to the point of interest is supplied from the adder circuit 46 to the output terminal 48 via the switch 47.

The reason why the pixel signal is interpolated from two pixels before and after in the case of 263 lines of delay is as follows. In other words, 910 color difference pixel signals per line are sampled with 3 pixel jumps (4 pixel periods), so the 263rd line has 910 color difference pixel signals.
This is because since 10X263 (=239.330) is not an integral multiple of 4, the position of the (RY) pixel signal replaces the position of the (B-Y) pixel signal.

FIG. 5 shows the high level suppression processing circuits 10a and 10 of FIG.
FIG. 3 is a block diagram representatively illustrating the configuration of FIG.

This high level suppression processing circuit 10a includes an input terminal 51 for an adjacent field difference signal Δ(RY) of a color difference signal, coefficient multipliers 52a, 52b, switches 53, 54, 59, 61,
It is comprised of an absolute value circuit 55, a polarity discrimination circuit 56, a comparison circuit 57, dark value holding circuits 58a and 58b, a polarity inversion circuit 60, an output terminal 62, and an input terminal 63 for a noise reduction processing cancellation command.

The adjacent field difference signal Δ(RY) of the color difference signal outputted from the subtraction circuit 9a and supplied to the input terminal 51 is supplied to the coefficient unit 52a and the absolute value circuit 55. The difference signal between adjacent fields, which has become a non-polar signal in the absolute value circuit 55, is
It is supplied to one input terminal of the comparison circuit 57. The other input terminal of the comparison circuit 57 is supplied with the threshold value Δ0 held in the dark value holding circuit 58a via the switch 59.

If the absolute value of the adjacent field difference signal being input is less than or equal to the dark value ΔO, the output of the comparator circuit 57 is held in a high state, and the switch 53 is switched to the upper side in the figure. As a result, the input adjacent field difference signal koΔ(RY) on which a certain coefficient ko has been added is supplied to the output terminal 62 via the switches 53 and 54.

On the other hand, when the absolute value of the input adjacent field difference signal becomes larger than the dark value ΔO, the output of the comparator circuit 57 is inverted to a low state, and the switch 53 is switched to the lower side in the figure. As a result, 1ΔO becomes kOΔ(
R-Y) is supplied to output terminal 62 via switches 53 and 54 instead. Note that the switch 61 is switched to the upper side or the lower side in the figure depending on whether the polarity determination circuit 56 determines whether the polarity of the adjacent field difference signal being input is positive or negative. A certain level is output.

As a result, as shown in FIG. 8, the input signal Δ(RY)
The output signal δ(R-Y) increases linearly in proportion to the input signal until it exceeds the threshold value Δ0, and even if the input signal becomes larger than the threshold value ΔO, the output signal δ(R-Y) remains at a constant value. is held, and the high level side is suppressed. This is equivalent to changing the overall coefficient value as shown in FIG. 9 according to the level of the input signal.

By changing the threshold value Δ0 to the threshold value Δl by switching the switch 59, the point at which the level becomes constant is changed. When Δ1>ΔO, the suppression characteristic on the high level side is changed to that shown by the dashed line in FIG. 8 by switching the switch 59.

In addition, when canceling the above-described noise reduction process, a high signal instructing to cancel the process is supplied to the input terminal 63 by a user's manual operation or the like, and the switch 54 is switched to the lower side in the figure. As a result, zero is output from the output terminal 62, and the noise reduction process is canceled.

FIG. 10 shows the high level suppression processing circuits 10a and 1 of FIG.
FIG. 3 is a block diagram illustrating another configuration of the high-level suppression processing circuit 10a as a representative example.

This high level suppression processing circuit has an input terminal 71 . Coefficient units 72a, 72b, switches 73.74
, 79.81 In addition to the absolute value circuit 75, the polarity discrimination circuit 76, the comparison circuit 77a, the dark value holding circuits 713a and 78b, the polarity inversion circuit 80a, the output terminal 82, and the input terminal 83 for canceling the noise reduction process, 2 comparison circuits 77b, a subtraction circuit 84, and an OR gate 77b.

It is assumed that the switch 79 is switched to the upper side in the figure and the threshold value Δ1 is being selected. In this case, the input signal Δ(R-
The comparison circuit 77 determines that the absolute value of Y) is less than or equal to the threshold value Δ1.
While detection is being made at point a, the switch 73 is switched to the upper side in the figure. As a result, Δ(R-Y) output from the coefficient circuit 72a is outputted to the output terminal 82 via the switches 73 and 74, and the output signal δ(R-Y) increases linearly in proportion to the input signal. ). On the other hand, the input signal Δ(
The comparator circuit 7 indicates that the absolute value of RY) exceeds the threshold Δ1.
7a, the switch 73 is switched to the lower side in the figure, and the output 2 of the subtraction circuit 84 is outputted from Δ1− to Δ(R−Y
) is output via switches 73 and 74. Further, when the comparison circuit 77b detects that the absolute value of the input signal Δ(RY) exceeds twice the threshold value Δ1, the OR gate 85
The output rises to high, the switch 74 is switched to the lower side in the figure, and the output is fixed at zero.

As a result, a triangular input/output characteristic as shown by the solid line in FIG. 11 is obtained. This converts the coefficient of the total input signal Δ(
This is equivalent to changing the signal as shown in FIG. 12 according to the level of R-Y). Further, by changing the threshold value Δl to Δ2 by switching the switch 79, the input/output characteristics shown in FIG. 11 can be changed. - For example, when Δ2>Δ1, the input/output characteristics in FIG. 11 change as illustrated by the dashed line.

FIG. 13 shows the high level suppression processing circuits 10a and 1 of FIG.
FIG. 3 is a block diagram illustrating still another configuration of the high-level suppression processing circuit 10a as a representative example of the high-level suppression processing circuit 10a.

This high level suppression processing circuit includes an input terminal 91 for the adjacent field difference signal Δ(RY) of the color difference signal corresponding to the case shown in FIG.
4, 99, 101, absolute value circuit 95, polarity discrimination circuit 96
, comparison circuit 97a.

97b, threshold value holding circuits 98a, 98b, polarity inversion circuit 1
00a, coefficient circuit xoob, 1ooc, output terminal 102
, a noise reduction processing cancellation command input terminal 103, a subtraction circuit 104, and an OR gate 105, a third comparison circuit 97c, a coefficient circuit 106, and a switch 107 are provided.

The switch 99 is switched to the upper side in the figure, and the holding circuit 9
It is assumed that the threshold value Δ1 of 8a is being selected. in this case,
While the comparison circuit 97a detects that the absolute value of the input signal Δ(RY) is less than or equal to the threshold value Δ1, the switch 9
3 is switched to the upper side in the figure. As a result, Δ(RY) is output from the coefficient circuit 92a at the switch 93.
, 107 and 94, and is output to the output terminal 102, resulting in an output signal δ(R-Y) that increases linearly in proportion to the input. On the other hand, the absolute value of the input signal Δ(RY) is the threshold Δ1
When the comparison circuit 97a detects that Δ1 has exceeded the constant value output from the subtraction circuit 92b, the switch 93 is switched to the lower side in the figure, and the switches 93, 107, and 9
4 and is output to the output terminal 102. Furthermore, when the comparator circuit 97b detects that the absolute value of the input signal Δ(RY) exceeds the threshold value 2Δ1 output from the coefficient circuit 100b, the switch 107 is switched to the lower side in the figure, and the subtraction Output of circuit 104 (3 to Δ1- to Δ(R-Y))
is output to output terminal 102 via switches 107 and 94. Furthermore, when the comparator circuit 97c detects that the absolute value of the input signal Δ(R-Y) exceeds 3ΔI output from the coefficient circuit 100c, the output of the OR gate 105 rises to high and the switch 94 switches as shown in the figure. is switched to the lower side, and the output is fixed at zero.

As a result, a trapezoidal input/output characteristic as shown by the solid line in FIG. 14 is obtained. This converts the overall coefficient to the input signal Δ(R
-Y) as shown in FIG. 15. Furthermore, by changing the threshold value Δ1 to Δ2 by switching the switch 99, the input/output characteristics shown in FIG. 14 can be changed. - For example, when Δ2>Δ1, the input/output characteristics in FIG. 14 change as illustrated by the dashed line in the figure.

FIG. 16 shows the high level suppression processing circuits 10a and 1 of FIG.
FIG. 3 is a block diagram illustrating still another configuration of the high-level suppression processing circuit 10a as a representative example of the high-level suppression processing circuit 10a.

This high-level suppression processing circuit has a trapezoidal input similar to that shown in FIG. 13 by adding a high-level suppression processing circuit similar to that shown in FIG. 5 after the high-level suppression processing circuit similar to that shown in FIG. The output characteristics are configured to be realized by a different configuration.

That is, the front stage from the input terminal 111 to the output terminal of the switch 114 includes coefficient circuits 112a and 112b that multiply the input signal by a factor of 2 and 2 by a factor of 2, respectively, and when the absolute value of the input level exceeds the threshold value Δl. Comparison circuit 117a
The switch 113 is switched by the output of the comparator circuit 1 when the absolute value of the input level exceeds twice the threshold value Δ1.
It is provided with a switch 114 that can be switched by the output of 17b. Furthermore, this first stage part is 2 to Δ1−k (
A subtraction circuit 124 and an absolute value circuit 115 that generate R-Y)
, a polarity determination circuit 116, a dark value holding circuit 118, a polarity determination circuit 1160, a polarity assignment circuit that assigns the same polarity to the threshold value Δ1 according to the determination result 119.2 times the coefficient circuit 1201
It includes an OR gate 122, an input terminal 123 for a command to cancel noise reduction processing, and the like.

Therefore, in the configuration of this former stage, the dark value is the holding circuit 118.
The structure is the same as that of the high level suppression processing circuit shown in FIG. 10, except that Δ1 is the only type held. As a result, a triangular input/output characteristic having an input level Δ(RY) equal to the threshold value Δl as a vertex is created in this first stage portion as shown in FIG.

Further, in the latter part from the output terminal of the switch 114 to the output terminal 131, there is a dark value holding circuit 12 that holds the threshold value δ1.
8. Absolute value circuit 125, polarity determination circuit 126, polarity assignment circuit 129 that assigns the same polarity to the threshold value δl according to the determination results of the polarity determination circuit 126, and a comparison circuit 127 when the output of the absolute value circuit 125 exceeds the threshold value δ1. It is equipped with a switch 130 etc. which can be switched by the output of.

Therefore, the configuration of this latter stage is the same as the high level suppression processing circuit shown in FIG. 5, except that the dark value is only 61. As a result, the output signal δ(RY) supplied to the output terminal 131 is maintained at a constant level δ1 within a range in which the input to the latter stage, that is, the output of the front stage exceeds the threshold value δ1.

The overall input/output characteristic of the nonlinear processing circuit shown in FIG. 16, which is a combination of the above-mentioned front-stage part and rear-stage part, is trapezoidal as shown in FIG. 17.

As described above, the sampling circuit 8 is provided before the subtraction circuits 9a and 9b.
A and 8b are installed to hold one pixel signal extracted from a pixel column of primary color difference signals at four-pixel jumps over a four-pixel width. However, since there is often a considerable degree of correlation between adjacent pixels, these sampling circuits can be omitted if some error due to the collapse of this correlation is tolerable.

Further, a configuration in which a 263 line interpolation circuit is installed in the demultiplexing/serial/parallel conversion circuit 7 is illustrated.

However, instead of this interpolation circuit, for the 263rd line, the outputs of the (R-Y) and (B-Y) color difference signal systems are crossed, that is, the (R-Y) color difference signal is changed to the (B-Y) color difference signal.
At the same time, the color difference signal of the (B-Y) system is output to the (R
-Y) may be configured to be output to the system.

Furthermore, the color difference signals to be noise reduced are (RY) and (B-
The present invention has been explained taking as an example the case where Y, but I, R
The present invention can also be applied to color difference signals.

(Effects of the Invention) As described in detail above, the color signal noise reduction circuit according to the present invention has the following advantages.

First, the three primary colors R and G are used as color signals to be processed.

Since the configuration selects two types of color difference signals (R-Y, B-Y, etc.) instead of B, it is possible to apply noise reduction processing using a method different from that for luminance signals.

In other words, relatively high-cost noise reduction processing is performed using inter-frame correlation for luminance signals with high visibility, and low-cost noise reduction processing is performed using inter-field correlation for color signals with low visibility. can be applied. Note that whether or not to perform noise reduction processing using inter-field correlation instead of inter-frame correlation for luminance signals is determined based on a comprehensive judgment that also takes into account other points.

Second, the color signal noise reduction circuit according to the present invention performs noise reduction processing on the color signal using an inter-adjacent field difference signal based on the correlation between adjacent fields instead of the correlation between adjacent frames. Since the frame memory for delay is replaced with a field memory, the memory capacity is reduced to half and the manufacturing cost is reduced.

Thirdly, the color signal noise reduction circuit according to the present invention thins out each of the two types of color difference signals every predetermined number of pixels, performs time division multiplexing, delays by one field, and then demultiplexes the two types of color difference signals. By doing this, the memory capacity for delay is further compressed, so there is an advantage that manufacturing costs are further reduced. Since the color signal has few high-frequency components, even if data is compressed by thinning, there is little deterioration in image quality due to this, and a significant improvement in cost performance is achieved.

Fourthly, the color signal noise reduction circuit according to the present invention performs parallel/serial conversion by time division multiplexing on the upper bit portion and lower bit portion of each pixel signal to be multiplexed, and delays the signal by one field. Since the configuration compresses the bit width of the memory by subsequently performing serial/parallel conversion and restoring the pixel signal to the original bit width, only one relatively small capacity general-purpose memory can be used for delay processing. memory can be configured, and manufacturing costs can be reduced accordingly.

Fifth, since the noise reduction circuit of the present invention is configured to perform processing to suppress the high level side of the difference signal between adjacent fields of the color difference signal, a dedicated detection circuit is used to detect malfunctions due to the collapse of the correlation between adjacent fields. Another advantage is that it can be removed at low cost without using any circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a color signal noise reduction circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the multiplexing/parallel/serial conversion circuit 3 in FIG. 1, Third
The figure is a block diagram showing the configuration of the multiplexing/separating/serial/parallel conversion circuit 7 in FIG. 1, and FIG. 4 is the 263-line interpolation circuit 35a in FIG. 3. 35b is a block diagram representatively showing the configuration of the former;
FIG. 5 shows the high level suppression processing circuits 10a and 10 in FIG.
A block diagram representatively showing the configuration of b by the former, No. 6
The figure is a waveform diagram for explaining the operation of the multiplexing/parallel/serial conversion circuit 3 in Figure 1, and Figure 7 is a waveform diagram for explaining the operation of the multiplexing/parallel/serial conversion circuit 3 in Figure 1.
A waveform diagram for explaining the operation of the serial/parallel conversion circuit 7,
Figures 8 and 9 are nonlinear processing circuit 1 in Figure 1, respectively.
A characteristic diagram illustrating the input/output characteristics of 0a and the relationship between the input level and the overall coefficient, and FIG. 10 is a block diagram showing another example of the configuration of the high level suppression processing circuits 10a and 10b in FIG. 1, with the former representative. Figures 11 and 12 are the first
Figure 13 is a characteristic diagram illustrating the input/output characteristics of the high level suppression processing circuit shown in Figure 0 and the relationship between the input level and the total coefficient.
A 14th block diagram showing still another example of the configuration of the high-level suppression processing circuits 10a and 10b shown in the figure, with the former being representative.
15 and 15 are characteristic diagrams respectively illustrating the input/output characteristics of the high level suppression processing circuit in FIG. 13 and the relationship between the input level and the total coefficient, and FIG. FIG. 17 is a characteristic diagram illustrating the input/output characteristics of the high-level suppression processing circuit of FIG. 16, and FIG. 18 is a block diagram illustrating the conventional inter-frame correlation. 1 is a block diagram showing the configuration of a noise reduction circuit that utilizes. Ia, Ib...color difference signal (R-Y) to be noise reduced,
(B-Y) input terminal, Ic...field pulse input terminal, 2a, 2b, 9a, 9b...subtraction circuit, 3...multiplexing/parallel/serial conversion circuit, 4...26
2 line delay circuit, 5...1 line delay circuit, 6...
・Switch switched by field pulse,
7... Demultiplexing/serial/parallel conversion circuit, 8a, 8b.
...Sampling circuit, 10a, 10b...Nonlinear processing circuit, Oa, Ob...Noise reduction processed color difference signal (R-Y), (B-Y) output terminal, 22a, 22
b, 25---Latch circuit, 23a. 23b, 24... multiplexer, 32.3334.
36a, 36b...-latch circuit, 35a, 35b...
・263 line interpolation circuit, 42-45... latch circuit, 46... addition circuit, 52a, 52b, 60... coefficient circuit, 55-- absolute value circuit, 56... polarity discrimination circuit, 57 . . . Comparison circuit, 58a, 58b . . . Dark value holding circuit. Patent applicant: NEC Home Electronics Co., Ltd.

Claims (4)

[Claims] (1) A color signal noise reduction circuit that performs noise low-frequency processing on digital first and second color difference signals separated from a composite video signal in a television receiver, the first and second outputs The first and second color difference signals being output to the terminals are extracted every predetermined number of pixels and are time-division multiplexed, while the upper and lower bit parts of each pixel to be multiplexed are also time-division multiplexed. means for performing parallel/serial conversion on the delayed multiplexed serial color difference signal by one field; means for performing parallel/serial conversion on the delayed multiplexed serial color difference signal by one field; series/
means for performing parallel conversion to restore first and second color difference signals having a time width corresponding to the predetermined number of pixels with the original bit width; , means for generating an adjacent field difference signal between the first and second primary color difference signals appearing at the second input terminal; a high-level suppression processing means that performs processing to suppress the side, and synthesizes the adjacent field difference signals of the first and second color difference signals that have been subjected to the high-level suppression processing and the corresponding first and second primary color difference signals. and means for outputting the noise-reduced first and second color difference signals to the first and second output terminals. (2) The high level suppression processing means increases the output level linearly as the input level increases below a predetermined input level, and maintains the output level at a predetermined value in a range exceeding this input level regardless of the increase in the input level. 2. The color signal noise reduction circuit according to claim 1, wherein the color signal noise reduction circuit retains the following characteristics. (3) The high level suppression processing means linearly increases the output level as the input level increases below a predetermined input level, and linearly lowers the output level to zero level as the input level increases in a range exceeding this input level. 2. The color signal noise reduction circuit according to claim 1, wherein the color signal noise reduction circuit reduces noise to . (4) The high level suppression processing means linearly increases the output level as the input level increases below a first predetermined input level, and within a range greater than this input level and below a second predetermined input level. In this patent claim, the output level is maintained at a predetermined value regardless of an increase in the input level, and in a range exceeding the second input level, the output level is linearly decreased to zero level as the input level increases. A chrominance signal noise reduction circuit according to range 1.