JPH02262361A - Semiconductor device and storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device which has a negative resistance and operates at high speed and then makes integration to a silicon substrate easy by providing the 1st region of the 1st conductivity type, the 2nd region of the 2nd conductivity type which surrounds the 1st region, the 3rd region of the 2nd conductivity type which surrounds the 2nd region externally without coming into contact with the 2nd region, and the 1st conductivity type 4th region whose impurity concentration is high. CONSTITUTION:This device is equipped with the 1st region 2 of the 1st conductivity type, the 2nd region 3 of the 2nd conductivity type which surrounds the 1st region 2, the 3rd region 5 of the 2nd conductivity type which surrounds 2nd region 3 externally without coming into contact with the 2nd region 3, and the 1st conductivity type 4th region 6 whose impurity concentration is high. For example, as shown by Fig., an N-type impurity region 2 and P-type impurity region 3 are formed at an N-type semiconductor substrate 1 and then a hook region 4 is made up by joining the region 2 with region 3. Further, a P-type emitter region 5 and an N<+> type base region 6 are formed. This configuration lessens a resistance between emitter and hook regions and decreases the absolute quantity of minority carriers which are accumulated around the hook region 4 and then makes this device operate at great speed by reducing transition period from ON to OFF.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a semiconductor device that is fast in operation, has a simple configuration, and has negative resistance characteristics, and a memory that combines this semiconductor device with a memory resistor. It is related to the device.

[Conventional technology]

Conventionally, as a semiconductor device having this kind of negative resistance,
These included Gunn diodes, PNPN diodes, unijunction transistors, conductance transistors, and combinations of FETs. These semiconductor devices utilize negative resistance and have been expected to be applied to memories, etc., but they have not been seriously applied to LSIs due to difficulties in integration and slow operation speed. There was nothing to do.

FIG. 8 is an explanatory diagram showing a conventional hooked unijunction transistor (hereinafter referred to as rHUJTJ). In the figure, 1 is an N-type semiconductor substrate, 2 is an N diffusion region, 3 is a P diffusion region, 4 is a hook region or collector electrode consisting of diffusion regions 2 and 3, 5 is an emitter electrode of the P diffusion region, and 6 is an emitter electrode of the P diffusion region. N is the base electrode of the diffusion region. When a constant voltage is applied between the base and collector of this transistor and the voltage between the emitter and collector is traced, a current-controlled negative resistance as shown in Figure 9(a) is observed (the vertical axis is emitter current I).

In addition, if a constant voltage is applied between the emitter and collector and the voltage VB between the base and collector is traced, Figure 9 (
A voltage-controlled negative resistance as shown in b) is observed (the vertical axis indicates the base current I).The details of these operations can be found in the following papers ① and ②.

■ Suzuki and Mizutori, Report of the 3rd Conference on Plasma-Coupled Semiconductor Devices and Solid-State Devices, Tokyo, 1972.
Pages 40-44 (Suzuki and Mizushi
ma.

Plasma-coupled 5eIIlicond
uctor devices +Proceedin
gs of 3rd conference on 5
olid 5tate devices, Tokyo
, 1972+ pp, 4O-44) Tamura, Mizutori and Daikoku, Voltage-controlled negative resistance in a conductance transistor with hook structure, Electronics Letter, April 17, 1975, Vol. 11, No. 8, 167-
168 pages (T, Tamura + Y, Mizushir
aa and K, Daikoku, ” Volta
ge-controlled n-egative r
resistance in conductance
transistors with hook 5tru
ture, Electronics Lette
rs17th April 1975. vol, 11.
No, 8. (pp, 167-168) [Problems to be Solved by the Invention] However, the device shown in FIG.
Although it can be easily manufactured using the I process, negative resistance characteristics are obtained by injecting minority carriers into the semiconductor substrate and accumulating them around the collector, so the operating speed is limited by the lifetime of the minority carriers. The problem was that it wasn't faster.

The present invention has been made in view of these points, and its purpose is to provide a semiconductor device and a memory device that have negative resistance, are high-speed, and are easy to integrate onto a silicon substrate. There is a particular thing.

[Means to solve the problem]

In order to achieve such an object, the first aspect of the present invention includes a first region of a first conductivity type, a second region of a second conductivity type surrounding the first region, and a second region of a second conductivity type surrounding the first region. A third region of the second conductivity type that does not touch the second region and surrounds the second region in a planar manner, and a fourth region of the first conductivity type having a high impurity concentration are provided. This is what I did.

Further, the second aspect of the present invention provides a first region of a first conductivity type, a second region of a second conductivity type surrounding the first region, and a second region in contact with the second region. a third region of the second conductivity type that has a lower impurity concentration than the second region and that surrounds the second region; and a third region that is in contact with the third region and has a higher impurity concentration than the third region; , and a fourth region of the second conductivity type which planarly surrounds the third region, and a fifth region of the first conductivity type having a high impurity concentration.

Furthermore, a third aspect of the present invention provides a first region of a first conductive type, a second region of a second conductive type surrounding the first region, and a second region of a second conductive type that does not touch the second region. , and a third region of the second conductivity type surrounding the second region in-plane, a fourth region of the first conductivity type having a high impurity concentration, and an insulating region surrounding the third region in-plane. In this embodiment, an area is provided.

Furthermore, a fourth aspect of the present invention includes a first region of a first conductivity type, a second region of a second conductivity type surrounding the first region, and a second region in contact with the second region. a third region of the second conductivity type that has a lower impurity concentration than the second region and surrounds the second region in-plane; and a third region that is in contact with the third region and has a higher impurity concentration than the third region. , and a fourth region of the second conductivity type surrounding the third region in-plane, a fifth region of the first conductivity type having a high impurity concentration, and an insulating region surrounding the fourth region in-plane. In this embodiment, an area is provided.

Furthermore, a fifth invention of the present invention provides a semiconductor device according to the first, second, third or fourth invention, and one end of which is an emitter or an emitter of the semiconductor device according to the first, second, third or fourth invention. A memory resistor connected to the base and serving as a load is provided.

[Effect]

In the semiconductor device according to the present invention, the resistance between the emitter and the hook is small, the absolute amount of minority carriers accumulated around the hook can be reduced, and the minority carriers can be recovered through the emitter surrounding the hook.

〔Example〕

First, the features of the present invention and the differences from the prior art will be described. By surrounding the periphery of the hook region with the emitter diffusion region of the HUJT, the present invention reduces the resistance between the emitter and the hook during the transition period from off to on, and reduces the resistance that accumulates around the hook during the on state. The HUJT achieves high-speed operation by reducing the absolute amount of carriers and collecting minority carriers through the emitter during the transition period from on to off. High-speed operation can be achieved without any problems. Furthermore, by connecting the emitter diffusion region and the hook region with a region of the same conductivity and low impurity concentration, the above-mentioned effect is further enhanced and high speed is achieved.

FIG. 1 is an explanatory diagram showing a first embodiment of the present invention. In the figure, 1 is an N-type semiconductor substrate, 2 is an N-type impurity region, 3 is a P-type impurity region, and regions 2 and 3 are
Together, hook area 4 is realized. Further, 5 is an emitter region, and 6 is a base region. A method for realizing such a structure is omitted here because it can be realized by an extremely rudimentary LSI manufacturing process.

In this way, this embodiment has a configuration in which the periphery of the hook region 4 is surrounded by the emitter diffusion region.

Therefore, the resistance between the emitter and the hook is smaller,
It is clear that the off-to-on transition time can be reduced and increased in speed. In addition, the absolute amount of minority carriers accumulated around the hook region 4 can be reduced, and the minority carriers can be recovered through the emitter region 5 surrounding this area, so the transition time from on to off can be reduced. It can be made smaller and faster. In the current-voltage characteristics of this embodiment, sharp characteristics similar to those of the conventional one shown in FIG. 8 can be realized as both current-controlled negative resistance characteristics and voltage-controlled negative resistance characteristics.

FIG. 2 is an explanatory diagram showing a second embodiment of the present invention. Reference numeral 7 denotes a region of the same conductivity type as the emitter region 5, which connects the emitter and the hook. Here, it is called the bridge area. This region is set to have an impurity concentration low enough to be depleted when the base becomes higher than a certain bias.

The other areas are the same as in FIG. 1, and in FIG. 2, the same or equivalent parts as in FIG. 1 are given the same reference numerals.

Since the embodiment of the second invention has such a configuration, it is clear that the resistance between the emitter and the hook is smaller, and the transition time from off to on can be reduced and the speed can be increased. Furthermore, since minority carriers can be more easily recovered through the emiff region 5 surrounding the hook region 4, the transition time from on to off can be reduced and increased in speed. - Once turned off, the depletion layer between the emitter and the hook pinches off, so the characteristics become similar to those shown in FIG. It is also possible to control the off-state current using the emitter current.

FIG. 3 is a sectional view showing a third embodiment of the present invention, which is realized using an LSI process. In the figure, 1 is a semiconductor substrate, which is different from the previous embodiment! O
It is a P type substrate. 2 to 5 are the first. This is similar to the embodiment of the second invention. 6 is N' diffusion region and base region, 8 is N
9 and 10 are oxide films, 11 is N-type polysilicon and is a collector electrode, 12 is P-type polysilicon and is an emitter terminal, and 13 is N-type polysilicon and is a base electrode. This structure can be easily realized by SST technology, which uses polysilicon to realize a fine bipolar transistor structure in a self-aligned manner. S.S.
For details on T technology, please refer to the paper "Sakaki et al. "Gigabit Logic Pibora Engineering: Advanced Super-Selfline Process Engineering," Electron Letters, Vol. 19, No. 8, 283-28.
Page 4 (T, 5akaki et al, + 'Giga
bit logic bipolar te-cbno
logic:Advanced 5upper self-
aligned process technology
+Electron, Lett,, vo1.19
．． no, 8+pp.

283-284.1983) Details on J.

FIG. 4 is a sectional view showing a process flow for realizing the structure shown in FIG. 3. In FIG. 4(a), 13 is a silicon nitride film, and 14 is a silicon oxide film. First, as shown in FIG. 4A, an oxide film 14, a nitride film 13, and a P-type polysilicon 12 are deposited on a semiconductor substrate 8, and a portion that will become a collector is opened using a normal lithography technique. Thereafter, as shown in FIG. 4(b), after oxidizing the surface of the P-type polysilicon 12, an oxide film 14 and a nitride film 13 are formed.
overhang etching. Next, as shown in FIG. 4C, the etched portion is filled with polysilicon, and P-type impurities are diffused from the polysilicon 12 to the semiconductor substrate 8, thereby realizing an emitter 61M5.

As a result, the emitter region 5 can be formed in a self-aligned manner so as to surround the collector pattern. Next, as shown in FIG. 4(d), while forming an oxide film to separate the emitter and collector, a collector window is opened, first a P-type impurity region 2 is formed, and then a P-type impurity region 2 is formed. N
By forming a type impurity region 3, a hook region 4 is formed.

When the structure shown in Fig. 3 is realized, the region where minority carriers are injected is limited to the semiconductor region 8 surrounded by the oxide film 9, thereby reducing the amount of accumulated carriers and significantly increasing the recovery speed to the emitter. can do. Therefore, the operating speed can be further improved.

FIG. 5 is a sectional view showing a fourth embodiment of the present invention. In the same figure, 7 is a region having the same conductivity type as the emitter, and is a bridge region connecting the emitter region 5 and the hook region 4, as in the second embodiment of the invention. This region is set to have an impurity concentration low enough to be depleted when the base becomes higher than a certain bias.

It is clear that with this configuration, the resistance between the emitter and the hook is lower, and the off-to-on transition time can be reduced and the speed increased. Furthermore, since minority carriers can be more easily recovered through the emitter region 5 surrounding the hook region 4, the transition time from on to off can be reduced and increased in speed. - Once turned off, the depletion layer between the emitter and the hook pinches off, so the characteristics become similar to those shown in FIG.

It is also possible to control the off-state current using the emitter current.

FIG. 6 is a circuit diagram showing an embodiment of a storage device according to the fifth aspect of the present invention. In the figure, Q is the above-mentioned semiconductor device, B is the base terminal, E is the emitter terminal,
C is a collector terminal. Further, 15 is a load resistor as a memory resistor, 16 is a voltage source for base bias, and 17
is a voltage source for emitter bias.

With this configuration, by setting the emitter bias voltage source 17 to a higher voltage than the base bias voltage source 16, the semiconductor device IQ can be turned on, and the voltage source 17 can be set to zero voltage. It can be turned off by setting it to OFF. Further, the on state and off state of the semiconductor device Q can be evaluated by measuring the voltage (2) of the emitter E. As described above, the semiconductor device Q is extremely small and fast, and a high resistance and compact device can be realized by using polysilicon or the like as a load resistor. Therefore, by utilizing this fact, it is possible to construct a high-speed and highly integrated storage device. Note that T in FIG. 6 is an emitter current.

FIG. 7 is a circuit diagram showing a second embodiment of a storage device according to the fifth aspect of the present invention. In the figure, Q is the semiconductor device mentioned above, B is the base terminal, E is the emitter terminal, and C
is the collector terminal. Further, 15 is a load resistor as a storage resistor, 16 is a voltage source for base bias, and 17 is a voltage source for emitter bias.

With this configuration, the semiconductor device Q can be turned on by setting the emitter bias voltage source 17 to a lower voltage than the base bias voltage source 6, and by setting it to a higher voltage. Can be turned off. Further, the on state and off state of the semiconductor device Q can be evaluated by measuring the voltage of the base terminal B. As mentioned above, the semiconductor device iQ is extremely small and fast, and a high resistance and compact device can be realized by using polysilicon or the like as a load resistor. Therefore, by utilizing this fact, it is possible to construct a high-speed and highly integrated storage device.

〔Effect of the invention〕

As explained above, the present invention surrounds the periphery of the hook with the emitter diffusion region of the unijunction transistor with the hook, thereby reducing the resistance between the emitter and the hook during the transition period from off to on, and reducing the resistance during the on state. to reduce the absolute amount of minority carriers that accumulate around the hook,
During the transition period from on to off, minority carriers can be recovered through the emitter, which has the effect of realizing high-speed operation.

Further, the above effect can be further enhanced by connecting the emitter diffusion region and the hook region with a region of the same conductivity and low impurity concentration.

Furthermore, by combining the semiconductor device according to the present invention and a load resistor, it is possible to construct a memory device that has an extremely large degree of integration and is capable of high-speed reading and writing.

[Brief explanation of drawings]

FIGS. 1 and 2 show the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing the third embodiment of the present invention; FIG. 4 is a cross-sectional view showing the manufacturing process of the device shown in FIG. 3; FIG. 5 is a sectional view showing the fourth embodiment of the present invention, and FIG.
FIG. 7 shows the first and second embodiments of the fifth invention of the present invention.
FIG. 8 is an explanatory diagram showing a conventional semiconductor device, and FIG. 9 is a characteristic diagram showing current-controlled negative resistance characteristics and voltage-controlled negative resistance characteristics. ■...Semiconductor substrate, 2...N-type semiconductor region, 3...
- P-type semiconductor region, 4... hook region, 5... emitter region, 6... base region, 7... bridge region. Figure 1, Ward 2, Figure 3

Claims (5)

[Claims] (1) A first region of a first conductivity type, a second region of a second conductivity type surrounding the first region, and a surface of the second region that does not touch the second region. What is claimed is: 1. A semiconductor device comprising: a third region of a second conductivity type surrounding a semiconductor device; and a fourth region of a first conductivity type having a high impurity concentration. (2) A first region of the first conductivity type, a second region of the second conductivity type surrounding the first region, and a region that is in contact with the second region and has a higher impurity concentration than the second region. a third region of the second conductivity type that is low and planarly surrounds the second region; and a third region that is in contact with the third region and has a higher impurity concentration than the third region;
A semiconductor device comprising: a fourth region of the second conductivity type which planarly surrounds the third region; and a fifth region of the first conductivity type having a high impurity concentration. (3) a first region of a first conductivity type, a second region of a second conductivity type surrounding the first region, and a surface of the second region that does not touch the second region; A third region of the second conductivity type that surrounds the third region, a fourth region of the first conductivity type that has a high impurity concentration, and an insulating region that planarly surrounds the third region. semiconductor device. (4) A first region of the first conductivity type, a second region of the second conductivity type surrounding the first region, and a region that is in contact with the second region and has a higher impurity concentration than the second region. a third region of the second conductivity type that is low and planarly surrounds the second region; and a third region that is in contact with the third region and has a higher impurity concentration than the third region;
and a fourth region of the second conductivity type that planarly surrounds the third region, a fifth region of the first conductivity type that has a high impurity concentration, and an insulating region that planarly surrounds the fourth region. A semiconductor device comprising: (5) A memory device comprising the semiconductor device according to claim 1, 2, 3, or 4, and a memory resistor having one end connected to the emitter or base of the semiconductor device and serving as a load.