JPH0226119A - Data processing system - Google Patents

Abstract

PURPOSE:To simplify hardware constitution without improving the processing speed of a CPU by executing the reading of a reproduced time code and the control of data output timing with the same CPU. CONSTITUTION:A buffer memory 61 controls the output timing of the parallel data of 16 bits to a terminal 62 in order to compensate a part, in which the time mismatching of reproduced data from two types of decode data can not be mechanically compensated. The timing control of writing and reading in the memory 61 is executed by supplying the reproduced time code to a host computer with a CPU64 and receiving the command of output time control. Further, the CPU64 executes the giving and receiving of the data with a clock generator 56 for the formation of the time code. However, since the CPU64 executes processing at a low speed in comparison with a CPU for the correlative arithmetic of a correlation device, the high speed processing is not requested. Accordingly, since the exclusive CPU is not provided, a data processing system is simplified even in the hardware constitution.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing system, and in particular to a data processing system that digitizes a pair of broadband analog information signals, records them on separate data recorders, and reproduces them from these data recorders. The present invention relates to a system for measuring the correlation between the pair of wideband analog signals using the data obtained by using the broadband analog signals.

[Conventional technology]

This type of system is VLBI (Very
L○ng Ba5eline Interfero
An observation system called METRY (very long baseline radio interferometer) is well known, and in this specification, a case where the present invention is applied to this VLB I system will be described.

The VLB I observation system receives signals from a radio wave source billions of light-years away using two antennas thousands of kilometers apart.
Measures the distance between two antennas with high accuracy of several centimeters.

Precise measurements of continental sliding and Earth rotation have recently begun using this VLB I technology, and it is attracting a lot of interest in various fields of earth science and space science.

One of the most important components of the VLB I observation system is a high-density, large-capacity data storage device. This is because the received radio waves are extremely weak, so a large amount of data is acquired and the difference in arrival time of the radio waves is detected from the small signal components contained therein. Actually V
The data recorded in the LB I observation system is a predetermined 200 ml of analog broadband signal of several hundred ml (z order).
The MH2 band components are extracted over ten channels, and the analog signals of these ten channels with a bandwidth of 2 MHz are each digitized into one bit. Then, data recorded simultaneously at two points is simultaneously reproduced, and their correlation information (the magnitude of cross-correlation, phase delay time, rate of change thereof, etc.) is measured.

As mentioned above, when obtaining correlation information about ten channels of data reproduced from two data recorders, these data must be perfectly time-aligned. However, if the two data recorders are Even if synchronized operation could be achieved, perfect time alignment could not be achieved due to the limits of physical and mechanical accuracy of each recorder.Therefore, in conventional systems of this type, time codes were set for each channel. Recording and reproduction are performed in addition, and the time mismatch that occurs between the reproduced data from the two data recorders is compensated for each channel by using the above-mentioned time code at the input stage of the correlation measuring device.

(Problem to be Solved by the Invention) However, since the above-mentioned correlation measurement device requires extremely complicated arithmetic processing, a CPU capable of high-speed processing for this arithmetic processing is used to compensate for time mismatch. If you say,
Furthermore, it is necessary to prepare a CPU with high processing speed, which is not desirable, but it is necessary to prepare a CPU with a separate CPU to compensate for this time mismatch.
Providing a PU complicates the hardware configuration. especially,
1 and must be configured to control this 1, and the CPU for this requires a considerable amount of processing power.
The above-mentioned trend is even more pronounced.

In view of the above-mentioned background, the present invention provides a system having a function of compensating for temporal misalignment of reproduced data related to two wideband analog information signals without increasing the processing speed of the CPU. The purpose of this invention is to provide a data processing system that can simplify the hardware configuration.

[Means for solving problems]

With such an object in mind, the present invention includes a pair of data recorder sections each digitizing and recording a broadband analog information signal, and a pair of analog information based on the data respectively reproduced from the pair of data recorder sections. In a system comprising a correlation measurement unit that measures the correlation of signals, the data recorder unit records and reproduces a time code in addition to the data related to the analog information signal, and the data recorder unit records and reproduces a time code in addition to the data related to the analog information signal, and also transmits information to the interphase measurement unit based on the reproduced time code. The data output timing can be controlled, and the reading of the reproduced time code and the control of the data output timing are performed by the same CPU.

[For production]

By configuring as described above, the CP in the phase-to-phase measuring section
Compared to U, the CPU for reading time codes, which does not require high processing speed, is used to control the output timing of data from the data recorder to the correlation measuring section. In this case, the time mismatch between the two data can be compensated for on the data recorder side, and there is no need to provide a separate CPU.
Moreover, there is no need to prepare a high-speed CPU.

〔Example〕

A VLBI observation system to which the present invention is applied will be described below.

FIG. 2 is a diagram showing the configuration of the VLBl observation system to be applied in this example. In FIG. 0, la and lb are
100 ~ obtained from parabolic antennas at each observation station.
Terminal 2a, into which a 520MHz analog signal is input;
2b is an analog interface that separates 16 2MHz bandwidth components distributed in the input analog signal band to obtain 16 channels of analog signals (
A-IF), 3a, and 3b are A-IF2a.

4a and 4b are human interfaces (input IFs) that further convert the 16-bit parallel data obtained by sampling 1 bit of each of the 16 channels of analog signals from 2b into 4-bit parallel data.
In addition to the 4-bit data from a and 3b, time code,
Recorded data processing circuit 5a that adds error correction codes and the like to create a data format suitable for magnetic recording and reproduction.

5b is a digital data recorder (DDR) for recording and reproducing digital signals from the processing circuits 4a and 4b, and at each observation station, at least the portions surrounded by the dashed lines Aa and Ab are prepared. ing.

6a and 6b are reproduction data processing circuits that return the data reproduced from the DDRs 5a and 5b to the original data format, perform error correction, time code extraction, etc.; 7a and 7b are reproduction data processing circuits that perform processing such as error correction and time code extraction; This is an output interface (IF) that converts 4-bit data into 16-bit data and creates a data format that meets the specifications for observing data correlation in the correlator 8 in the subsequent stage, and in this specification, 3a to 7a. , 3b to 7b, that is, the range surrounded by broken lines Ba and Bb is referred to as a data recorder section. 8 is a correlator, which calculates the various correlation information mentioned above for the purpose of the introduction. The two observation stations are naturally located at different points on the earth, but the information observed at these observation stations and recorded as data is brought to the correlator and the correlation is measured. In this case, at least the portion surrounded by the two-dot chain line C in the figure is prepared. However, in this embodiment, it is assumed that the data recorder section BaBb is integrally constructed.

FIG. 3 is a diagram showing a specific configuration of the data recorder sections Ba and Bb in FIG. 2 as an embodiment of the present invention. 10 in FIG. 20 is a data processing section including a recording data processing circuit and a reproduction data processing circuit; 30 is a DDR.

In the interface section 10, 11 is a terminal into which 16 channels of analog signals from A-1F are input.
Input IF12 receives these 16 channels of analog signals,
After sampling 1 bit of each to create 16-bit parallel data, the data is further supplied to the data processing section 20 as 4-bit parallel data. 13 is a terminal to which a reference clock common to another observation station is input; 14 is a terminal that converts the 4-bit parallel data from the data processing unit 20 into the original 16-bit parallel data and a data format for the correlator; This is an output IF whose output timing to the terminal 15 can be adjusted.

16, the input IF 12.16 responds to the keyboard operation and the reference clock. This is a CPU that controls the output IF 14, and the CPU 16 controls the input IF 14 via the control bus 18.
12. This CP exchanges data with the output IF 14 and also exchanges data with a keyboard/display unit 17 having a keyboard and a display.
U16 also has a function of transmitting and receiving time codes to and from the data processing section 20. This interface section 10
This will be explained in detail later.

In the data processing section 20, 4-bit data from the input IF is outputted to the data bus 23 via the data interface (data IF) 21. This data is stored in the -H memory 24, and is supplied to the recording data processing circuit 25 together with the time code from the CPU 22. The recording data processing circuit 25 formats the data including the 4-bit data and time code. Ting.

Processing such as adding an error correction code (ECC) is performed and the DDR3 data is sent via the terminal 40 as two-channel serial data.
0. In the DDR 30, two channels of serial data from the data processing unit 20 are supplied to a rotating magnetic head on a rotating cylinder 32 via an amplifier 31, and the two channels are simultaneously helically recorded on a magnetic tape (not shown).

The two channels of signals simultaneously reproduced from the rotating magnetic head on the rotating cylinder 32 are sent to a reproduction amplifier 33 and an equalizer 3.
4 to the data separation circuit 35, and the circuit 35
The 2-channel serial data obtained by the 0 separation circuit 35, which is converted into the original 2-channel serial data at the terminal 40, is
The reproduced data is supplied to the reproduced data processing circuit 26 via the reproduced data, and the reproduced data is written in the memory 24 according to a predetermined format.

The ECC decoder 27 exchanges data with the memory 24 and performs error correction.The error-corrected 4-bit data is returned to the interface section 10 via the data IF 21, and the time code is sent via the CPU 22. and returned to the interface section.

In the DDR 30, 38 is a servo/system controller, which controls the operation of each part of the DDR 30, such as the cylinder control circuit 37 and the capstan control circuit 36, based on control data obtained from the CPU 22 of the data processing section 20. In response to the operation from the keyboard 1f, the CPU 22 receives the control data and time code generated by the CPtJ16.
Control data is supplied to the servo/system controller 38, and as will be described later, control data when operating two DDRs synchronously is also sent to the servo/system controller 38 via this path.
The system controller 38 is provided with the following information.

FIG. 1 is a diagram showing the specific configuration of the interface section in this embodiment. In the figure, the left side of the dotted line is the input IF
The right side functions as an output IF.

16 channels of analog signals with a bandwidth of 2 MHz are input to the terminal 51, and the clip/sample circuit 52
supplied to A 10 MHz reference clock and an IHz reference pulse (IPPS) are input to 54 and 55, respectively, and the clock generator 56 receives these reference signals.
The CPU 64 is used to output 4 MHz and 16 MHz reference clocks and IPPS. Of course, the reference signal input to the terminals 54 and 55 must be common to each observation station.

In the clip/sample circuit 52, after clipping each of the 16 channels of analog signals, the clock generator 56
Using a 4 MHz clock from the 4 MHz clock, the data is sampled and quantized at 4 M)izl bits, and is supplied to the multiplexer 53 as 16-bit 4 MHz parallel data. The multiplexer 53 converts 4 MHz 16-bit parallel data into 16 MHz 4-bit parallel data. The data acquisition timing and output timing in this multiplexer 53 are determined by the 4 MHz and 16 MHz clocks from the clock generator 56.

On the other hand, the CPU 64 uses the clock obtained via the clock generation circuit 56 to form a time code (time information). This time code is, for example, September 1st, 1 hour 9
It is a precise one that contains information such as minute 9 seconds, 1710 seconds, 1/100 seconds, etc., and each decimal number is formed as 4-bit data. This time code is supplied together with the data from the multiplexer 53 to the data processing section via the connector section 58. At this time, the data supplied from the CPLJ64 to the data processing section includes, in addition to the time code, system control data obtained from keyboard operations, etc., and also includes the 16 MHz and 4 MHz clocks obtained from the clock generator 5B, and the IPPS. The data is supplied to the data processing section 20.

Next, the operation when the DDR connected to this interface section is operated synchronously with other DDRs and output data is supplied to the correlator will be described.

The terminal 66 is a terminal for transmitting and receiving data via an interface (IF) 65 between the host computer and the CPU 64 for synchronized reproduction operation of the two data recorder sections. The time load is sent to the host computer via the IF 65. If the difference between the time codes reproduced from two DDRs operating synchronously is a difference that can be brought closer mechanically, the host computer
A command for controlling such as changing the tape speed of at least one DDR is transmitted to the CP via the IF65.
Supply to U64. The CPU 64 supplies system control data to the CPU 22 of the data processing section 20 based on this command, keyboard input, and the like. As a result, the two DDRs reduce the time difference between reproduced data within a mechanically adjustable range.

The 16 MHz 4-bit parallel data from the data processing section 20 is returned to 4 MHz 16-bit parallel data by the demultiplexer 59. At this time, the clock used for this conversion is a 4 MHz, 16 MHz clock synchronized with the DDR operation.
These are MHz clocks, which are obtained via the connector section 58. Each bit of the 16-bit parallel data from the demultiplexer 59 is sample data of 16 channels of analog signals at the same time, and there is no time lag between each bit. This 16-bit parallel data is formatted For example, in conventional systems, the correlator side compensates for the time mismatch between the two DDR reproduced data. Therefore, the format circuit 60 performs processing such as adding a time code from the CPU 64 or replacing it with predetermined 4-bit data, and adding a redundant code assuming a system in which error detection is performed on the correlator side.

A buffer memory 61 is used to adjust the output timing of the 16-bit parallel data to the terminal 62 in order to compensate for the time mismatch between the two DDRs that cannot be compensated for mechanically. be. The writing/reading timing control of this buffer memory 61 is also performed by the CPU.
64 supplies the reproduced time code to the host computer and receives an output time adjustment command from the host computer. In this case, the time adjustment command is common to 16 channels.

Therefore, the control path 57, which is the data bus of the CPU 64, is connected to the clock generator 56. Formatting circuit 6
0. It will be used for exchanging data with the buffer memory 61.

In this way, since the reproduced data temporally aligned between the three data recorders is supplied to the correlator, the correlator can calculate correlation information without any temporal adjustment.

In the system of the above-described embodiment, the time mismatch between the reproduced data from the two data recorders is compensated for by the buffer memory 61 provided at the output stage of the data recorder section, and the writing/reading thereof is is controlled by the CPU 64 in the human output interface. This CPU 64 sends and receives data to and from the clock generator 56 to form time codes, but since it performs slower processing than the CPU for correlation calculations of the correlator, it controls the buffer memory. Even if this is done, the CPU 64 is not required to process at such a high speed. Therefore, it is extremely advantageous compared to the case where time misalignment is compensated on the correlator side, and in particular, the CPU 64 is not required to perform high-speed processing.
Since there is no , the hardware configuration is also simplified.

Furthermore, in the system of this embodiment, 16-bit parallel data obtained by sampling 1 bit of each of the 16 channels of analog signals is recorded and reproduced as one word using DDR, so that the data of each channel is temporally divided during reproduction. No deviation occurs at all. Therefore, by adjusting the output timing in the buffer memory 61 as 16-bit parallel data, 16-bit parallel data can be output from two DDRs.
The mismatch of all six channels can be compensated for, and there is no need to provide such a timing control circuit for each channel, which is also extremely advantageous.

(Effects of the Invention) As explained above, according to the present invention, in a system having a function of compensating for temporal misalignment of reproduced data related to two broadband analog information signals, it is possible to reduce the burden on the processing speed of the CPU. A data processing system can be obtained in which the hardware configuration of the entire system can be simplified without requiring any additional effort.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an input/output interface section of a system as an embodiment of the present invention, FIG. 2 is a diagram showing the entire configuration of a data recorder section of a system as an embodiment of the present invention, and FIG. The figure shows the configuration of the entire system to which the present invention can be applied. In the figure, Ba and Bb are data recorder sections 2a. 2b is an analog interface, 3a, 3b are input interfaces, 4a, 4b are recording data processing circuits, 5
a and 5b are digital recorders, 6a and 6b are reproduced data processing circuits, 7a and 7b are output interfaces, 8 is a correlator, 10 is an input/output interface section, 20 is a data processing section, 30 is a data recorder, 56 is a clock generation circuit, 60 is a formatting circuit, 61 is a buffer memory,
64 is a CPU.

Claims (1)

[Claims] It consists of a pair of data recorder sections that each digitize and record a broadband analog information signal, and a correlation measurement section that measures the correlation between the pair of analog information signals based on the data respectively reproduced from the pair of data recorder sections. In the system, the data recorder section is configured to record and reproduce a time code in addition to data related to the analog information signal, and to control the timing of outputting data to the correlation measurement section based on the reproduced time code. is,
A data processing system characterized in that reading the reproduced time code and controlling the data output timing are performed by the same CPU.