JPH02256313A - Data identification circuit - Google Patents

Abstract

PURPOSE:To attain stable operation with simple constitution by obtaining an intermediate level between an upper envelope and a lower envelope of an identification input signal regardless of an amplitude of the identification input signal and its DC level. CONSTITUTION:A binary identification input signal (input signal) S1 fed to an input terminal 1 is fed to a comparator 2, an upper envelope detector 3 and a lower envelope detector 4. An intermediate level 54 between an output S2 of the upper envelope detector 3 via a resistor 5, and an output 53 of the lower envelope detector 4 via a resistor 6 is compared and discriminated with the input signal S1 at a comparator 2. Thus, an identification 85 is outputted at an output terminal 7 of the comparator 2. Since the intermediate level S4 is obtained regardless of the input signal S1, an excellent identification S5 with a stable pulse width is obtained from the comparator 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data identification circuit suitable for use in a digital communication system.

[Prior Art] A data identification circuit of a digital communication system has conventionally been configured as shown in FIG. 7, for example.

In the same figure, an identification input signal S1 (shown in FIG. 8A) is supplied to an input terminal 21, and this identification input signal S1 is supplied to an amplitude compensation circuit 22 so that the amplitude thereof is kept at a constant value.

The output signal S6 (shown in FIG. B) of the amplitude compensation circuit 22 is supplied to the DC level compensation circuit 23, and the DC level is set to a constant value E ref.

The output signal S7 (shown in C of the same figure) of the DC level compensation circuit 23 is supplied to the comparator 24.

A reference voltage having the same value as the value E ref compensated by the DC level m compensation circuit 23 is supplied to the comparator 24 to perform a comparison judgment.

Therefore, an identification signal S8 as shown in the eighth diagram is outputted to the output terminal 25 derived from the comparator 24.

[Problems to be Solved by the Invention] By the way, the amplitude compensation circuit 22 and the DC level compensation circuit 23 detect the amplitude and DC level, respectively, during boat fishing, and stabilize the amplitude and DC level by feedback. will be carried out.

Therefore, the circuit configuration becomes complicated, and oscillation may occur if the feedback loop is not optimally designed.

Therefore, it is an object of the present invention to provide a data identification circuit that has a simple configuration and operates stably.

[Means for Solving the Problems] The present invention provides a data identification circuit for a digital signal processing system, which includes a first envelope detector that detects an upper envelope of the amplitude of an identification input signal, and a first envelope detector that detects an upper envelope of the amplitude of an identification input signal. a second envelope detector for detecting a lower envelope of the amplitude of the first envelope;
and a voltage dividing resistor connected between the outputs of the second envelope transverse transducer and generating an arbitrary potential between the upper envelope potential and the lower envelope potential; A comparator is provided for comparing and determining the identification signal using the pressure output as a reference voltage.

[Function] In the above configuration, the identification input signal Jtillii
No matter what the voltage or DC level is, a reference voltage between the upper envelope potential and the lower envelope potential of the identification input signal is obtained, so the comparator outputs an identification signal with a stable pulse width. Ru. Furthermore, there is no need for a circuit that compensates for the amplitude and DC level of the identification input signal, and it can be realized with a simple circuit configuration. Furthermore, since there is no feedback loop, there is no risk of oscillation, and the number of key 18% points is reduced.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG.

In the figure, a binary identification input signal S+ is input to input terminal 1.
(shown in FIG. 2A) is supplied, and this identification input signal S
1 is supplied to a comparator 2 and an envelope detector 3.4.

The envelope detector 3 is configured to detect the upper envelope of the identification input signal S1, while the envelope detector 4 is configured to detect the lower envelope of the identification input signal S1.

These envelope detectors 3 and 4 are constructed using, for example, diodes, as shown in FIGS. 3A and B, and are constructed using ideal diodes, such as operational amplifiers, with no dead band, as shown in FIGS. 4A and B. It is configured as shown in .

A series circuit of resistors 5 and 6 with a resistance value R is connected between the output sides of these envelope detectors 3 and 4, and a signal S4 obtained at the connection point of these resistors 5 and 6 (see C in the same figure) ) is supplied to the comparator 2 as a reference voltage.

In this case, the signal S4 is composed of the upper envelope potential S2 (shown in FIG. B) of the identification input signal S1 output from the envelope detector 3 and the identification input signal S1 output from the envelope detector 4.
It becomes an intermediate potential between the lower envelope potential S3 (shown in B of the same figure).

Comparator 2 receives identification input signal S! A comparison judgment is made between the signal S4 and the signal S4. Therefore, an identification signal S5 as shown in the second diagram is outputted to the output terminal 7 derived from the comparator 2.

In this way, according to this example, no matter what the amplitude or DC level of the identification input signal S+, the identification input signal Sl
Since a reference voltage s4 intermediate between the potential S2 of the upper envelope and the potential S3 of the lower envelope is obtained, a good identification signal S5 with a stable pulse width can be obtained from the comparator 2. Furthermore, there is no need for a circuit that compensates for the amplitude and DC level of the identification input signal S1 to be constant, and a simple circuit configuration can be achieved. Further, since there is no feed pan groove, there is no fear of oscillation, and there are advantages in that there are fewer adjustment points.

Note that in the digital radio device, the output of the demodulator corresponds to the identification input signal Sl of this example. In this case, variations in the modulation degree and demodulation sensitivity correspond to amplitude variations in the identification input signal S1, and variations in the transmission frequency and reception station oscillation frequency correspond to variations in the DC level of the identification input signal s1.

Next, FIG. 5 shows another embodiment of the present invention. In FIG. 5, parts corresponding to those in FIG. 1 are designated by the same reference numerals.

In the figure, a ternary identification input signal S1' is input to input terminal 1.
(shown in FIG. 6A) is supplied, and this identification input signal S
l' is a comparator, 2a, 2b and an envelope detector 3.
4.

Further, a series circuit of semi-fixed resistors 8 and 9 having the same resistance value is connected between the output sides of the envelope detectors 3 and 4.
Signals S4a and 54b (shown in FIG. 3C) obtained at the movable ends of these semi-fixed resistors 8 and 9 are supplied as reference voltages to comparators 2a and 2b, respectively.

In this case, the connection point of semi-fixed resistors 8 and 9 has a first
Similar to the example in the figure, the potential S2 of the upper envelope of the identification input signal Sl' (shown in FIG. B) and the potential S3 of the lower envelope
A signal S4 having a potential between (shown in Figure B) is obtained. Therefore, the signal S4a has a potential between the signals S2 and S4, and the negative signal S4b has a potential between the signals S4 and No. 18 S3.

The comparators 2a and 2b compare and judge the identification input signal Sl' with the signals S4a and S4b, respectively. Therefore, these comparators 2a and 2
Output terminals 7a and 7b derived from
5b is output.

In this way, according to this example, even if the amplitude and DC level of the identification input signal Sl' are as follows, the identification input signal S
Reference voltage S 4a, S at a constant level with respect to l'
4b is obtained, so comparator 2a.

From 2b, a good identification signal S5a with a stable pulse width is obtained.
S5b can be obtained. In addition, the identification input signal S
There is no need for a circuit that compensates for the amplitude of l' and the DC level to be constant, and the circuit configuration can be simple. Furthermore, since there is no feedback loop, there is no risk of generation, and there are fewer adjustment points.

[Effects of the Invention] As explained above, according to the present invention, no matter what the amplitude or DC level of the identification input signal, the potential of the upper envelope of the identification input signal and the potential of the lower envelope of the identification input signal are Since a reference voltage between the two is obtained, an identification signal with a stable pulse width can be obtained from the comparator. In addition, there is no need for a circuit to compensate for the amplitude or DC level of the identification input signal.
This can be achieved with a simple circuit configuration. Also, since there is no feedback loop, there is no risk of failure! l! l There will be fewer areas to adjust.

8.9...Semi-fixed resistor

[Brief explanation of drawings]

Claims (1)

[Claims] (1) In a data identification circuit of a digital signal processing system, a first envelope detector detects an upper envelope of the amplitude of an identification input signal, and a second envelope detector detects a lower envelope of the amplitude of the identification input signal. and a voltage divider connected between the outputs of the first and second envelope detectors to generate an arbitrary potential between the potential of the upper envelope and the potential of the lower envelope. A data identification circuit comprising: a resistor; and a comparator that compares and determines the identification signal using a divided voltage output from the voltage dividing resistor as a reference voltage.