JPH02254834A - Short-circuit detection unit in multiplex signal transmission, and multiplex signal transmission system using the unit - Google Patents

Abstract

PURPOSE:To eliminate the disturbance of signal transmission by other repeater by outputting a short-circuit detection signal so as to open a return signal line when a voltage level of the return signal line is in the short-circuit level consecutively for a predetermined and prescribed period. CONSTITUTION:When a short-circuit takes place in a return signal line l4 and the short-circuit period exceeds a prescribed period determined by a short-circuit detection circuit 50, the short-circuit detection circuit 50 outputs a short-circuit detection signal to a return signal opening circuit 51 and a normally closed contact 51a is opened and a return signal line l4 is disconnected. Thus, even when a short-circuit takes place in the reply signal line l4, the voltage level of the return signal line l4 connecting to a trunk line amplifier is opened, the hindrance to the transmission of the replay signal of a repeater connecting to other trunk line amplifier is prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an improvement in multi-signal transmission, and more specifically, to an arrangement in which a signal line is opened when a short circuit occurs in the signal line. It relates to things that have characteristics.

[Prior Art] In recent years, disaster prevention systems have been widely installed to prevent fires, etc. In such disaster prevention systems, a main line connected to - The structure is such that multiple repeaters are connected, terminal devices such as disaster prevention sensors are connected to the repeaters, and information that there is a fire is transmitted to the receiver side using multiplexed signals.

In a disaster prevention system with such a configuration, if the multiplex signal line is disconnected on the terminal device side, no reply signal is returned to polling from the receiver, so it may be a problem with the terminal device or the intermediate van. can be determined on the receiver side, but if the multiplex signal line is short-circuited, all terminal equipment and inside! ! This will interfere with the operation of the device. Further, in such a system, if noise or the like is superimposed on the multiplexed signal line, erroneous control will be performed.

Therefore, as a countermeasure against this problem, a system as shown in FIG. 9 has recently been used.

In the figure, 100 is a multiplex signal receiver, 101 is a trunk line extended from the multiplex signal receiver 100, 102... is a trunk amplifier that electrically isolates and separates the signal of the trunk line 101 and transmits it to a repeater. A repeater to which terminal equipment (not shown) such as a disaster prevention sensor is connected, 104 is a power supply circuit that supplies power to the repeater 103 side isolated by the main amplifier 102, and 105 is a repeater panel.

In this system, the main line 101 includes a main synchronization signal line, a trunk U signal line, a control signal line, a return signal line, a power supply line, and a common line. Signal CPI, sub-synchronization signal CP2, control signal DP, reply signal RD, electric R
vCC and the common line GND are connected across the main amplifier W102.

FIG. 1O is an internal circuit diagram of this main line amplifier 102, and the main synchronization signal CP1, sub-synchronization signal CP2, and control signal DP transmitted from the main line 101 are connected to terminals CPI, CP2, and control signal DP, respectively.
Connected to terminal CP2 and terminal DP, photocoupler Pc
t, electrically insulated and separated by PO2 and PO2 and amplified by amplifier circuits AMPI, AMP2 and AMP3, inside! ! Connector 10391 is connected to parallel terminal CPI'C
Main synchronization signal CPI isolated into P2' and CP3'
, a sub-synchronization signal CP2 and a control signal DP.

Further, the reply signal RD output from the Nakakoshu device 103 side is applied to the terminal RD' of the main line amplifier 102, isolated by the photocoupler PC4, amplified by the amplifier AMP4, and sent from the terminal RD to the main line 101. . Note that the power supply vcc' on the repeater 103 side of the main amplifier 102 is connected to the power supply circuit 1.
It is supplied from 04.

Also, in this system, (a) and (b) in Figure 11
As shown in the figure, the main synchronization signal CP2 and the sub-synchronization signal CPI, which have phases different by 180 degrees, are constantly transmitted through the main synchronization signal line and the sub-synchronization signal line of the main line 101, and their phases are constantly monitored. If noise or the like is superimposed on the sub-synchronization signal line and the main synchronization signal CP2 and sub-synchronization signal CPI are output in the same phase, the control operation is stopped. In addition, the multiplex signal receiver 100
The control signal DP transmitted from 1!1 is a pulse signal in phase with the main synchronization signal CP2, as shown in (C), and when there is no signal, the control signal DP is at the Lj level and up to 8 pulse signals at the H level. As shown in (d), the reply signal RD from the repeater 1゜3 is in phase with the main synchronization signal CP2, and is continuously transmitted as a maximum of eight pulse signals after the transmission of the control signal ends. When there is no signal, the level is "H" and when there is a signal, the level is "L".

In other words, with such a configuration, if the control signal line is short-circuited to the common line CND on the repeater 103 side, the control signal DP will not be transmitted to the repeater 103, so the terminal will be sent via the repeater 103. If the reply signal from the device no longer returns, the multiplex signal receiver 100 can immediately determine whether there is an abnormality in the terminal device or the signal line, and the control signal line DP
This prevents a short circuit from interfering with the signal transmission of the other repeaters 103, and also prevents malfunctions due to noise, improving the reliability of the multiplex signal transmission system. There is.

However, in a multiplex signal transmission system with such a configuration, the reply signal RD transmitted through the reply signal line is
It is at rHJ level when there is no signal, and it is at "L" level when outputting a signal, so if the reply signal line is shorted to the common line GND on the intermediate unit 103 side, the reply signal line goes to ground level and the main line Main line 101 via amplifier 102
Because the return signal line of the repeater 103 is set to the ground level, the return signal RD transmitted from the other repeater 103 becomes indistinguishable, so an improvement is desired.

[Invention tries to solve! ! H] The present invention proposed to solve the above problems eliminates interference with signal transmission of other repeaters by opening a return signal line when a short circuit occurs in the return signal line. The object of the present invention is to provide a detection unit, and the present invention, which is proposed at the same time, is to provide a multiplex signal transmission system with improved reliability using this short circuit detection circuit.

[Means for Solving the Problems] The short circuit detection unit of the present invention according to claim 1 proposed to achieve the above object detects the main synchronization signal, the sub synchronization signal and the control signal output from the main amplifier. A main synchronization signal line, a sub-synchronization signal line, and a control signal line that transmit to each repeater, a reply line 11 that transmits a reply signal output from the repeater to the main amplifier, a power supply line that supplies power supply voltage, and a short-circuit detection circuit that outputs a short-circuit detection signal when the voltage level of the common line and the return signal line is at a short-circuit level for a predetermined number of consecutive visits; and a reply signal opening circuit for opening and holding the reply signal line, and the multiplex signal transmission system of the present invention according to claim 2 has a structure in which a main line is connected between the multiplex signal receiver and the repeater. A multiplex signal transmission system comprising an amplifier and electrically insulating and separating the multiplex signal receiver and the repeater, according to claim 1.
The short circuit detection unit according to claim 3 is further interposed between the main amplifier and the repeater, and the present invention according to claim 3 is characterized in that the short circuit detection circuit of the short circuit detection unit A timing circuit that is activated to start timing when the voltage level of the signal line is at a short-circuit level and is reset when the voltage level of the return signal line returns to a non-short-circuit level, and a timing value of the timing circuit that is set in advance. and a timing discrimination circuit that outputs a short circuit detection signal when the voltage exceeds a predetermined value, and the present invention according to claim 4 provides that the short circuit detection circuit of the short circuit detection unit detects the voltage of the return signal line. A counting circuit is activated to start counting the above-mentioned main synchronization signal when the level is at the short circuit level, and is reset when the voltage level of the return signal line returns to the non-short circuit level, and the count value of the counting circuit is and a count discrimination circuit that outputs a short circuit detection signal when a predetermined value is exceeded. A shift register circuit samples the voltage level of the return signal line using a synchronization signal as a clock pulse, and a short circuit occurs when the output signals of consecutive predetermined registers among the registers of the shift register circuit all reach the short circuit level. and an AND circuit that outputs a detection signal.

[Function] In the short circuit detection unit of the present invention according to claim 1, the main synchronization signal, the sub-synchronization signal, and the control signal output from the main amplifier are transmitted through the main synchronization signal line, the sub-synchronization signal line, and the control signal line. The return signal transmitted to the repeater and output from the repeater is transmitted to the main amplifier via the return signal line. When the return signal line remains at the short circuit level for a predetermined period of time due to a short circuit, etc., the short circuit level is detected by the short circuit detection circuit, and a short circuit detection signal is output to the return signal opening circuit, thereby making the return signal line unique. In the multiplex signal transmission system of the present invention according to claim 2,
The main synchronization signal, sub-synchronization signal and control signal transmitted from the multiplex signal receiver through the main amplifier are transmitted to the repeater via the short circuit detection unit through the main synchronization signal line, sub-synchronization signal line and control signal line, The reply signal output from the middle wAW is transmitted through the reply signal line to the mains amplifier via the short circuit detection unit, and from the mains amplifier to the multiplex signal receiver via the mains. When the return signal line remains at the short circuit level for a predetermined period of time due to a short circuit, etc.,
In the present invention according to claim 3, the short circuit level is detected by the short circuit detection circuit of the short circuit detection unit, and the short circuit detection signal is outputted to the reply signal opening circuit to form the reply signal line. When this happens, the clock circuit of the short circuit detection circuit starts counting time, and when the clock value exceeds a predetermined value, it is determined by the clock discrimination circuit and a short circuit detection signal is output to the return signal generation circuit.

In the present invention as set forth in claim 4, when the return signal line reaches a short-circuit level, the counting circuit of the short-circuit detection circuit starts counting the main synchronization signal, and when the counted value exceeds a predetermined value, it is determined by the counting discrimination circuit. and outputs a short circuit detection signal to the return signal opening circuit.

Further, in the present invention as set forth in claim 6, each time the main synchronization signal is input to the shift register of the short circuit detection circuit, the signal level of the reply signal line is sampled into the register, and the contents of the register are shifted. If all the consecutive registers are at the short circuit level, the AND circuit makes a determination and outputs a short circuit detection signal to the reply signal opening circuit.

[Example] The present invention will be described in detail below with reference to the drawings.

FIG. 1 is an explanatory diagram showing the configuration of the short circuit detection unit of the present invention as set forth in claim 1. In FIG.
A terminal CP is connected to I (not shown) and is used to transmit the sub synchronization signal CPI, the main synchronization signal CP2, the control signal DP, the reply signal RD, the power supply vCC, and the common potential GND, respectively.
! , CP2. D.P.

RD, VCC, and GND are provided, and the front of these terminals are connected by a sub-sync signal line 11, a main synchronization signal line 12, a control signal line 13, a reply signal line 14, a power line 15, and a common line 16, respectively. .

Further, the reply signal line 14 is connected to the short circuit detection circuit 5o,
The reply signal opening circuit 51 has a normally closed contact 51 on the reply signal line 14.
The configuration includes a.

To explain the operation of this short circuit detection unit, each signal line 1
When 1 to 16 are not short-circuited, the normally closed contact 51a
are closed, and the main amplifier and repeater are connected by these signal lines 11-18 to perform signal transmission.

However, when a short circuit occurs in the reply signal line 14 and the short circuit period exceeds a predetermined period (in this embodiment, the main synchronization signal CP2 is transmitted nine times) determined by the short circuit detection circuit 50, Short circuit detection circuit 5° to reply signal opening circuit 51
A short circuit detection signal is output to the terminal 51a, the normally closed contact 51a is held open, and the reply signal line 14 is disconnected.

Therefore, even if a short circuit occurs in the return signal line 14, the voltage level of the return signal line 14 connected to the main amplifier will be in an open state, which will interfere with the transmission of return signals from repeaters connected to other main amplifiers. is prevented from occurring.

FIG. 2 is a diagram showing the configuration of the multiplex signal transmission system according to claim 2, and between the main amplifier and repeater of the multiplex signal transmission system shown in FIG. The configuration is such that the short circuit detection unit 6 described above is interposed therein.

In the figure, l is a disaster prevention receiver, l is a sub-synchronization signal line,
Main synchronization signal line, control signal line, reply signal line,
A main line includes a power supply line and a common line, 2 is a main line amplifier, 3 is a power supply circuit that supplies power to the repeater side via the main line amplifier 2, 4 is a repeater, and 5 is a short circuit detection unit. Further, 6 is a repeater board on which the main amplifier 2, power supply circuit 3, repeater 4, and short circuit detection unit 5 are attached.

In the disaster prevention system having such a configuration, when a short circuit occurs in the return signal line 14 on the repeater 4 side with respect to the short circuit detection unit 5, the short circuit detection unit 5 detects the return signal line 14.
Since the relay is opened, interference with signal transmission of other repeaters 4 is prevented. Note that if the short circuit of the return signal line 14 occurs on the main amplifier 2 side rather than the short circuit detection unit 5, the short circuit detection unit 5 has no effect;
In reality, there are many short-circuit accidents due to the short wiring between the main amplifier 2 and the short-circuit detection unit 6, and the wiring of terminal devices such as disaster prevention sensors (not shown) connected to the intermediate amplifier 4. will be played.

Next, FIG. 3 is a block diagram showing the configuration of the present invention according to claim 3, in which the short circuit detection circuit va50 is a clock circuit 50a.
and a time determination circuit 50b.

In this short circuit detection circuit 50, the voltage level of the reply signal line 14 is constantly monitored by the clock circuit 50a, and when this voltage level reaches the "L" level, timing is started. Then, the short circuit of the reply signal line 14 continues, and the clock value changes to the clock discrimination circuit 5.
When the time predetermined by 0b (in this embodiment, the time required to output nine main synchronization signals CP2) is exceeded,
The configuration is such that a short circuit detection signal is output from the time determination circuit 50b to the reply signal opening circuit 51 to maintain the opening of the reply signal line 14.

Further, FIG. 4 is a block diagram showing the configuration of the present invention according to claim 4, and the short circuit detection circuit 50 is composed of a counting circuit 50c and a counting discrimination circuit 50d.

In this short circuit detection circuit 50, the voltage level of the reply signal line 14 is constantly monitored by the counting circuit 50c, and when this voltage level becomes "L" level, the main synchronization signal CP2 transmitted from the main synchronization signal line 12 is Start counting. Then, the short circuit of the return signal line 14 continues, and the count value is changed to the count discrimination circuit 50.
d (in this embodiment, the main synchronization signal CP
When the number of outputs of 2 exceeds 9), the count discrimination circuit 50d outputs a short circuit detection signal to the reply signal opening circuit 51, and the reply signal line 14 is held open.

Next, FIG. 5 is a block diagram showing the configuration of the present invention described in claim 5, and the short circuit detection circuit 5o is different from the short circuit detection unit 5 described in claim 1, and the other configurations are the same. Therefore, the same reference numerals are given and the explanation is omitted.

In this configuration, the shift register circuit 50e constantly samples the voltage level of the reply signal line 14 using the main synchronization signal CP2 transmitted from the main synchronization signal &In2 as a clock pulse. When all the output signals of predetermined consecutive registers reach the short circuit level, a short circuit detection signal is output from the AND circuit 5°f to the reply signal opening circuit 51, and the reply signal line 14 is opened. is being held.

FIG. 6 is a circuit diagram showing the short circuit detection unit 5 of this configuration in more detail, and the shift register circuit 50e of the short circuit detection circuit 60 has two identical shift registers SRI, 5R2 ( In the figure, for convenience of explanation, the 8-stage registers of the shift register SRI are labeled Ql to Q8, and the 8-stage registers of the shift register SR2 are labeled Q9 to Q16), an inverter N0TI, N0T2. It is composed of N0T3.

The output of the register Q8 of this shift register SRI is connected to the data input terminal of the shift register SR2, and the main synchronization signal CP2 is applied to each clock terminal CL, so that the shift register has 16 register stages as a whole. It's working.

In addition, the AND circuit 50f is a four-man-powered AND IC (hereinafter referred to as A).
Furthermore, the reply signal opening circuit 51 includes a normally closed contact 51a, a set/reset relay 51b, a short circuit indicator 51C, and a relay operation indicator 5.
1d, normally closed contact 51e, and set/reset relay 51
transistor TR that sets and drives b, and a reset switch 51f that resets the set-reset relay 51b.
It is composed of: Note that a diode D is provided between each of the sub synchronization signal line 11, main synchronization signal line 12, control signal line 13, and return signal line 14 and the power supply line CC.
... has the function of clamping when the voltage level of each signal line increases to above the power supply voltage vCC, and is used to clamp the signal line when it is incorrectly connected to each terminal or when external noise is induced. Provide protection.

The operation of the short circuit detection unit 5 having such a configuration will be explained with reference to the timing charts of FIGS. 7 and 8. For convenience of explanation, register QIO of shift register SR2
~Q1B is not connected to AND3 and AND4, and is connected to AN
It is assumed that all unconnected input terminals of D3 and AND4 are connected to rHJ level, and shift registers SRI and SR
The explanation will be given assuming that 2 constitutes a 9-stage register.

In this circuit, the main synchronization signal CP2 transmitted by the main synchronization signal line 12 is connected to the inverter NOT2゜N0T3.
The voltage level of the return signal line 12 is inverted by the inverter NOT1 and is constantly input to the data terminal of the shift register SRI (see Fig. 7).
a), (b) #sho).

When no short circuit occurs in the signal line, after the control signal DP is sent out as shown in FIG. 7(c),
As shown in (d), the reply signal RD is returned with a maximum of eight pulses. Since this reply signal RD is in phase with the main synchronization signal CP2, each register samples these data, and when the last 8th pulse is output, the data contents of the reply signal are held in registers Q1 to Q8. It turns out. Then, when the output of the reply signal RD is finished,
Register Ql returns to "L" level in order. Therefore, when no short circuit occurs in the return signal line 14, more than eight registers will not output "H" level at the same time (7th (see Figures (e) to (n)), therefore, the output of AND5 of the AND circuit 50f never goes to "H" level, so the set-reset loop of the reply signal opening circuit 51 is not driven and is normally closed. Contact 51a remains closed.

However, as shown in FIG. 8(d), for example, if a short circuit occurs in the reply signal line i4 when the reply signal RD transmits two pulses, the data manually input to the shift register SRI will be short-circuited. After generation, it is always at the rLJ level, so even at the 9th pulse of the main synchronizing signal CP2, the "L" level is sampled, and all registers Q1 to Q9 are at the rHJ level. Therefore, ANDI, AND2
The output of AND3 becomes "H" level, and the transistor TRItd of the reply signal opening circuit 51 is activated through AND5.
As a result, the set/reset relay 51b becomes set, and the short circuit indicator light 51c lights up. As a result, the normally closed contact 51a is opened and the reply signal line! 4 is opened, the normally closed contact 51e is closed, and the relay operation indicator light 51d is lit. Therefore, these short circuit indicator lights 51
It is possible to immediately know whether or not a short circuit has occurred in the return signal line 14 by the display of the signal line c and the relay operation indicator light 51d. Then, by operating the reset button 51f after supplementing the short circuit of the reply signal line 14, the set-reset relay 51b is returned to the reset state and the normally closed contact is closed.

In the above embodiment, QIO to Q1B of the shift register
register and AND3. Although the explanation has been made with a configuration of 9 stages of registers without connection with AND4, the configuration is not limited to 16 stages of shift registers as shown in FIG. It is also possible to generate the reply signal &114 by sampling the signal. Further, in this embodiment, the short circuit indicator light 51c and the relay operation indicator light 51e are provided in the short circuit detection unit, but it is also possible to perform centralized management by transmitting and outputting the short circuit detection signal.

Furthermore, although the above explanation uses an example in which the short circuit detection unit of the present invention is applied to a disaster prevention system, the present invention is not limited to this example, and can be applied to multiple signal transmission systems having similar signal lines. Needless to say.

[Effects of the Invention] According to the present invention as set forth in claim 1, even if a short circuit occurs in a signal line on one repeater side, it is possible to prevent the operation of other repeaters from being affected. Can provide short circuit detection unit.

According to the present invention as set forth in claim 2, by using the short circuit detection unit as set forth in claim 1, it is possible to provide a multiplex signal transmission system with improved reliability.

Furthermore, according to the present invention as set forth in claim 3.4.5, the short circuit detection circuit can be realized with a simple configuration, and the same effects as in claim 1.2 can be obtained.

[Brief explanation of drawings]

1 is a configuration diagram of a short circuit detection unit of the present invention according to claim 1, and FIG. 2 is a system configuration diagram of the present invention according to claim 2 incorporating the short circuit detection unit according to claim 1,
3 is a block diagram of the short circuit detection circuit of the present invention according to claim 3, FIG. 4 is a block diagram of the short circuit detection circuit of the present invention according to claim 4, and FIG. 5 is a block diagram of the short circuit detection circuit of the present invention according to claim 5. A configuration diagram of the short circuit detection unit of the present invention, FIG. 6 is its circuit diagram, and FIGS. 7 and 8.
9 is a block diagram of a conventional multiplex signal transmission system, FIG. 10 is a circuit diagram of its main amplifier, and FIG. 11 is a timing chart illustrating its transmission signals. [Explanation of symbols] 1...Multiple signal receiver 2...Main amplifier 4...Repeater CF2...Main synchronization signal CPI...Body recovery signal DP...Control signal! t 2 ・ ・ l 11 13 dispute ・ D 1! 4 @ ・ 15th l 61 Φ 5 ・ ・ ・ 50a ・ 50b ・ 50c ・ 50d Life 50e ・ 50f Life・Main sync signal line・Sub sync signal line・Control signal line・Reply signal・Reply signal line・Power line・Common Line/Short circuit detection circuit/Reply signal open circuit Short circuit detection unit...Clock circuit...Time discrimination circuit...Counting circuit...Count discrimination circuit...Shift register circuit...Anding circuit

Claims (5)

[Claims] (1) A trunk amplifier connected to the multiplex signal receiver via a main synchronization signal line, a sub-synchronization signal line, a control signal line, a return signal line, a power supply line, and a common line, and a repeater corresponding to the trunk amplifier. A main synchronization signal line, a sub-synchronization signal line, and a control signal line interposed between the main amplifier and the main synchronization signal line, a sub-synchronization signal line, and a control signal line that transmit the main synchronization signal, sub-synchronization signal, and control signal output from the main amplifier to the repeater, respectively; A return signal line that transmits a return signal output from the device to the main amplifier, a power supply line and a common line that supply power supply voltage, and a voltage level of the return signal line that continues for a predetermined period of time. A short-circuit detection circuit that outputs a short-circuit detection signal when the short-circuit level is reached, and a return signal opening circuit that receives the short-circuit detection signal from the short-circuit detection circuit and holds the return signal line open. Short circuit detection unit in multiplex signal transmission. (2) In a multiplex signal transmission system having a configuration in which a main line amplifier is arranged between a multiple signal receiver and a repeater, and the multiple signal receiver and the repeater are electrically isolated, the main line amplifier A main synchronization signal line, a sub synchronization signal line, and a control signal line that transmit the main synchronization signal, sub synchronization signal, and control signal output from the repeater to the repeater, and a return signal output from the repeater to the main amplifier. a return signal line that transmits the power supply voltage, a power supply line and common line that supply the power supply voltage, and a short circuit detection signal when the voltage level of the return signal line is continuously at the short circuit level for a predetermined period of time. A short-circuit detection unit comprising a short-circuit detection circuit that outputs an output, and a return signal opening circuit that receives a short-circuit detection signal from the short-circuit detection circuit and holds the return signal line open, is connected between the main amplifier and the repeater. A multiplex signal transmission system characterized by further intervening. (3) The short circuit detection circuit of the short circuit detection unit is activated and starts timing when the voltage level of the reply signal line is at the short circuit level, and when the voltage level of the reply signal line returns to the non-short circuit level. Claim 1 or 2, characterized in that it is constituted by a timekeeping circuit that is reset and a timekeeping discrimination circuit that outputs a short circuit detection signal when the timekeeping value of the timekeeping circuit exceeds a predetermined value. Short circuit detection unit as described. (4) The short circuit detection circuit of the short circuit detection unit is activated when the voltage level of the reply signal line is at the short circuit level and starts counting the main synchronization signal, and the voltage level of the reply signal line is at the non-short circuit level. A counting circuit that is reset when the counting circuit returns to a predetermined value, and a counting discrimination circuit that outputs a short circuit detection signal when the counted value of the counting circuit exceeds a predetermined value. The short circuit detection unit according to item 1 or 2. (5) The short circuit detection circuit of the short circuit detection unit includes a shift register circuit that samples the voltage level of the return signal line using the main synchronization signal as a clock pulse, and a predetermined series of registers of the shift register circuit. 3. The short-circuit detection unit according to claim 1, further comprising an AND circuit that outputs a short-circuit detection signal when all the output signals of the registers have a short-circuit level.