JPH02252192A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the area of a chip to be occupied by a circuit element for the precharge of a complementary bit line by providing a bit select switch, which executes turning-on operation in correspondence to the non-selection period of a memory cell, and an equalize switch. CONSTITUTION:DRAM (dynamic random access memory) is equipped with plural n-channel type equalizer MOSFETs Q9 to selectively short-circuit complementary common data lines CD and -CD. A timing control circuit 12 is provided to control all bit line select switches 9 and the FETs Q9 to a turn-on state during the non-selection period of a memory cell 11. When these all the switches 9 and FETs Q9 are controlled to the turn-on state during the non- selection period of the memory cell 11, a pair of complementary bit lines BLi and -BLi, for which a level is forcibly set according to a power supply voltage Vdd and a ground voltage Vss, are conducted and thus, all the lines BLi and -BLi are balanced to a voltage almost half of the voltage Vdd. Thus, an exclusive precharge circuit is not required for each complementary bit line.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device and also to precharging of complementary bit lines, and relates to a technique that is effective when applied to, for example, a DRAM (dynamic random access memory). It is.

[Prior art]

A DRAM has a dynamic memory cell that stores signal charges in a storage capacitor, and when reading data, a sense amplifier amplifies the signal charges appearing from the storage capacitor to a bit line to a predetermined level. For example, in a DRAM formed using the folded intersection method, data input/output terminals of a sense amplifier consisting of a differential amplifier circuit are coupled to each complementary bit line, and a predetermined word line coupled to a selection terminal of a memory cell is selected. Then, the accumulated charge of the selected memory cell is applied to one of the complementary bit lines.

When stored charge is applied from a memory cell, a level determined by charge redistribution appears on one of the bit lines. The sense amplifier amplifies the potential difference between the level changed on one bit line and the reference potential applied to the other bit line, and adjusts the complementary bit line to a predetermined level. Force.

Incidentally, the level reached by the complementary bit lines whose levels are forced complementary by the sense amplifier is a pair of the power supply voltage and the ground voltage, regardless of the logical value of the read data.
In addition, when the sense amplifier is configured with a complementary push-pull circuit such as a complementary MO8 circuit, its operating point is approximately half the power supply voltage, and furthermore, noise due to charging and discharging of the complementary bit line is reduced. To reduce this, it is necessary to reduce the peak value of the charging/discharging current of the complementary bit line. Due to these points, half precharging of bit lines has traditionally been used to apply the above reference potential to complementary bit lines. , and between the respective complementary bit lines to precharge the complementary bit lines to an intermediate level of the power supply voltage.

An example of a document describing a bit line precharge circuit is Japanese Patent Laid-Open No. 60-212894.

[Problem to be solved by the invention]

However, if a dedicated precharge circuit is provided for each complementary bit line as in the past, the chip area of the semiconductor memory device will increase accordingly, and the chip area occupied by the precharge circuit will increase the storage capacity. In other words, the number increases as the number of complementary bit line pairs increases. Particularly in RAMs, where it is required to increase the storage capacity within a limited chip area, the increase in chip area occupied by the bit line precharge circuit cannot be ignored.

An object of the present invention is to provide a semiconductor memory device that can precharge bit lines without requiring a dedicated precharge circuit for each complementary bit line.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an equalization switch is arranged on a complementary common data line to which complementary bit lines are commonly connected via a bit line selection switch, and the bit line selection switch and equalization switch are controlled to be in an on state during a non-selection period of a memory cell. It is.

A plurality of equalize switches can be arranged at different positions on the complementary common data line depending on the length of the allowable precharge period.

[For production]

According to the above-described means, the bit line selection switch and the equalization switch, which are turned on in response to the non-selection period of the memory cell, are complementary bits forced to a complementary attainment level in response to the selection period of the memory cell. The lines are electrically conductive and precharged to mutually balanced levels.

〔Example〕

FIG. 2 shows a block diagram of a DRAM which is an embodiment of the present invention. The DRAM shown in the figure is formed on a single semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique, although this is not particularly limited.

In FIG. 2, reference numeral 1 denotes a memory cell array in which a plurality of dynamic memory cells are arranged in a matrix.Selection terminals of the memory cells are connected to word lines in each row direction, and data input/output terminals of the memory cells are connected in each column direction. is coupled to the complementary bit line. Each complementary bit line is connected to a complementary common data line C via a Y switch circuit 2 including a plurality of bit line selection switches connected one-to-one to the complementary bit lines.
It is commonly connected to D and CD.

The DRAM of this embodiment adopts an address multiplex system, and after supplying the X address signal Ax from the X address latch 4 to the X address decoder 5 via the address buffer and address multiplexer 3, the Y address signal Ay is supplied to the address buffer and address multiplexer 3. Address multiplexer 3
from Y address latch 6 to Y address decoder 7 via
supply to. The X address decoder 5 drives the word line corresponding to the address signal supplied thereto to a selection level. When a predetermined word line is driven to a selection level, a memory cell whose selection terminal is coupled to this word line is selected. Further, the Y address decoder 7 turns on the bit line selection switch corresponding to the address signal supplied thereto, and transfers the selected memory cell to the common data line C.
Make conductive to D and CD.

A sense amplifier, such as a differential amplifier circuit included in the sense amplifier array 8, is connected to each complementary pin 1- line. This sense amplifier detects and amplifies the potential difference between the accumulated charge of the selected memory cell and a reference potential described later. When the potential difference between the complementary pins 1 and 1 is amplified, the change is transmitted from the complementary common data lines CD and CD to the input/output circuit 9.
The main amplifier of the main amplifier amplifies the memory cell data, and the memory cell data is read out to the outside. When write data is given to the input/output circuit 9 from the outside, the write amplifier of the input/output circuit drives the complementary common data lines CD, CD according to the write data, thereby driving the complementary bit line selected by the address signal. Charge information corresponding to the data is stored in a predetermined memory cell via the memory cell.

FIG. 1 shows the Y switch circuit 2 and the memory cell array 1.
, a detailed circuit example near the sense amplifier array 8 is shown.

A pair of complementary bit lines BLi, BLi, which are typically shown in the DRAM of this embodiment, are configured in a folded-crossing manner with respect to the sense amplifier 10. The memory cell 11 is an N-channel type selection MO8FE, although it is not particularly limited.
It is a one-transistor type in which TQI and storage capacitor C5 are connected in series, and its data input/output terminals are sequentially connected to corresponding complementary bit lines BLi, BLi, and its selection terminal is connected to a predetermined word corresponding to each row. It is coupled to lines WLI-WLn. The storage capacity Cs of each memory cell 11 is as follows:
Although not particularly limited, a voltage equivalent to half of the voltage of the power supply voltage Vdd on one side of the circuit is applied.

The sense amplifier 10 includes, but is not particularly limited to, a p-channel type MO8FETQ2 and an n-channel type MO5FE.
Complementary type M○S (hereinafter simply referred to as CM) consisting of TQ3 connected in series
(also written as O8) inverter and p-channel type MO8F
It has a pair of CMOS inverters made by connecting ETQ2' and n-channel type MO8FETQ3' in series, and the input terminal of one CMOS inverter is connected to the input terminal of the other CM.
The MO8FETQ2. The common source electrode of Q2' is connected to a p-channel power switch MO.
Coupled to the circuit power supply voltage Vdd via 8FETQ4,
Above MO8FETQ3. The common source electrode of Q3' is connected to the ground voltage Vss as the other power supply voltage of the circuit via an n-channel power switch MO8FETQ5. Above power switch MO5FETQ4
．． Q5 is switch-controlled in phase by the sense amplifier signal φsa in response to the chip selection period.

The bit line selection switch included in the Y switch circuit 2 is provided corresponding to each complementary bit line, and the bit line selection switch included in the Y switch circuit 2 is provided corresponding to each complementary bit line.
The bit line selection switch 9 corresponding to Li and BLi is an n-channel type MO8FET Q6 interposed between one bit line BLi and common data line CD, and an n-channel type MO8FET Q6 interposed between one bit line BLi and common data line CD. mediated n
A bit line selection signal Y S Wi outputted from the Y address decoder 7 is supplied to the gate electrodes of both channels.

The complementary common data lines CD and CD are connected to n-channel type pull-up MO8FETQ8. It is coupled to the voltage voltage Vdd via Q8. This pull-up MO8FET
Q8. Q8 is controlled to be on by control signal φ□ in response to the chip selection period. Pull-up MO8FETQ
8. When Q8 is controlled to be on, the complementary common data line CD.

CD first connects MO8FETQ to power supply voltage Vdd.
The voltage is forced to a level lowered by the threshold voltage of 8. Before a predetermined complementary bit line is selected by the Y switch circuit 2, a predetermined word line is selected, and thereby the complementary bit line B Li is selected.

A potential difference corresponding to the amount of accumulated charge of the memory cell selected at that time is formed in BLi, and this potential difference is amplified by the activated sense amplifier 10. When the amplification operation by the sense amplifier 10 is substantially determined, the Y address decoder 7 performs a bit line selection operation at a predetermined timing, and for example, the line selection signal YSWi is set to a selection level such as a high level. Ru. At this time, if the level reached by the bit line BLi is the power supply voltage Vdd and the level reached by the other bit line BLj is the ground voltage Vss due to the operation of the sense amplifier 10, one common data line CD is set to the power supply voltage Vdd. The voltage that is lower than the threshold voltage of MO8FETQ8 is maintained, and the other common data line CD is connected to the MOS that is turned on at that time.
According to the resistance voltage division ratio due to the on-resistance of FETQ7 and MO8FETQ8, one of the common data lines CD
be lower than the level of This complementary common data line C
D.

By amplifying the CD level difference by the main amplifier included in the input/output circuit 9, the memory cell data is read out. Note that the levels reached by the complementary common data lines cD and CD do not necessarily have to be set to the power supply voltage Vdd and the ground voltage Vss, depending on the circuit configuration and characteristics of the main amplifier.

The DRAM of this embodiment has a circuit configuration on the Y switch circuit 2 side that half-precharges each complementary bit line to half the voltage of the power supply voltage Vdd during the chip non-selection period. That is, complementary common data line CD.

A plurality of n-channel type equalizing MO3FETQ9 that can selectively short-circuit the CD are provided, and a timing control circuit 12 is provided that controls all the bit line selection switches 9 and equalizing MO8FETQ9 to be in the on state during the non-selection period of the memory cell. . During the non-selection period of memory cells, all the bit line selection switches 9 and equalization MO
When 8FETQ9 is controlled to be on, all complementary bit lines whose levels were forced to the power supply voltage Vdd and ground voltage Vss by the operation of the sense amplifier 1o during the previous chip selection period are indicated by broken lines. Like MO8F
Complementary common data lines CD, CD and MO from ETQ6
The bit lines are made conductive through a path passing through the 8FET Q7, thereby balancing all complementary bit lines to a voltage approximately half of the power supply voltage Vdd.

At this time, even if the levels of the complementary common data lines CD, CD before the start of the half precharge operation do not match the level reached by the complementary bit lines, all the complementary bit line capacitances are equal to the complementary common data line capacitances. Since the level of the complementary common data lines CD, CD before starting the half precharge operation does not substantially affect the precharge level of the complementary bit line. In particular, if the storage capacity is large, in other words, if the number of pairs of lines to complementary pin 1 is extremely large, such complementary common data lines CD.

The influence of CD level can be completely ignored.

Furthermore, as the number of equalizing MO8FETQ9 increases, the number of short-circuit paths for the complementary P1- line increases, so that the bit line precharge speed becomes faster.

In addition, if it is necessary to compensate for the leakage current of the half-precharged complementary bit line when the standby state of the DRAM becomes long, an n-channel type MO8FET Q1 that is turned on in response to the chip non-selection period
0. Q10 to the respective complementary common data lines CD, C
It is possible to add a configuration in which a voltage that is half the power supply voltage Vdd is applied to D.

The timing control circuit 12 not only forms a control signal for bit line precharging, but also serves as a circuit that forms other control signals that control the overall operation of the DRAM. That is, this timing control circuit 12 has a row address strobe signal RAS, a column strobe signal
Address strobe signal CAS and write enable signal WE are supplied as external control signals. When the row address strobe signal RAS is asserted to a low level, the DRAM chip selection and the operation of the X address related circuit are instructed, whereby the address buffer and address multiplexer 3 convert the X address signal Ax into The signal is supplied to the latch 4, and the operation of the X address decoder 5 and the sense amplifier array 8 are instructed at predetermined timing. In particular, when the row address strobe signal RAS is negated, the timing control circuit 12 controls the control signal φ1 to a low level and controls the control signal φ2 to a high level,
Furthermore, a control signal φ is used to force all bit line selection signals output from the Y address decoder 7 to the selection level.
3 to instruct a half precharge operation of the complementary bit line.

When the column address strobe signal CAS is asserted to a low level, the operation of the Y address related circuit of the DRAM is instructed, and thereby the address buffer and address multiplexer 3 supply the Y address signal Ay to the Y address latch 6. At the same time, its Y address signal Ay
The bit line selection operation by the Y address decoder 7 in accordance with the above is instructed at a predetermined timing. The write enable signal WE enables the write operation by its low level.
It is also a control signal for instructing the input/output circuit 9 to perform a read operation at a high level.

Next, an example of the operation of the DRAM of this embodiment will be explained with reference to the timing chart shown in FIG. FIG. 3 shows an example of a read access operation.

Time t. When the row address strobe signal RAS is asserted to a low level in The state of being set to the selection level is canceled,
By turning off all the Y selection switches until a predetermined Y switch selection timing, the complementary bit lines and complementary common data lines CD, CD are made electrically non-conductive.

When the DRAM enters the chip selection state, it takes in an externally supplied X address signal Ax, decodes it with the X address decoder 5, and sets a predetermined word line, such as word line WL1, corresponding to the X address signal Ax to the selection level. drive As a result, a voltage whose charges are redistributed according to the accumulated charge amount of the memory cell 11 appears on one bit line BLi to which the data input/output terminal of the selected memory cell 11 is connected, and the other bit line BLi is connected to the reference bit line BLi. Maintain the precharge level as a potential. After the word line is selected, the sense amplifier 10 is activated, and the activated sense amplifier 10 converts the potential difference between the complementary bit lines BLi, BLi to a complementary attained level (power supply voltage Vdd,
amplify toward the ground voltage Vss).

Furthermore, when the DRAM enters the chip selection state, the control signal φ
, is inverted to high level, and the control signal φ2 is inverted to low level, thereby turning off the equalization MO.
Complementary common data lines CD and CD electrically separated by 8FETQ9 are pulled up by MO8F to be turned on.
ETQ8. Due to the action of Q8, M
The voltage is forced to drop by the threshold voltage of O8FETQ8.

When the column address strobe signal CAS is asserted to a low level at time t1, the DRAM takes in the Y address signal Ay supplied from the outside, decodes it in the Y address decoder 7, and responds to the Y address signal Ay. A selection signal for selecting a predetermined bit line selection switch, for example, a bit line selection signal Y S Wi , is set to high level at time t2. This selection timing is sense amplifier 1
The timing is after the amplification operation based on 0 has been substantially determined.

When a predetermined complementary bit line BLi, BLi is selected in this way, the level of one common data line connected to the other bit line whose attained level should be the ground voltage VsS is lowered, and the complementary common data line is A potential difference is created between lines CD and CD. This potential difference is amplified by the main amplifier included in the input/output circuit 9, so that the current memory cell data is read out.

At time t3, the memory read cycle ends and the row address strobe signal RAS and column address
When both strobe signals CAS are negated to high level, control signal φ1 is returned to low level and MO8FE
TQ8. When Q8 is turned off, all bit line selection switches are turned off and all sense amplifiers 10 are also deactivated, so the complementary bit lines and complementary common data lines become floating.

In this floating state, the complementary bit lines have reached the level of pairing the power supply voltage Vdd and the ground voltage Vss by the amplification operation of the sense amplifier 10, and the complementary common data lines CD, CD are connected from the power supply voltage Vdd to the MO
They are maintained at levels with a slight difference from each other based on the level dropped by the threshold voltage of 3FETQ8.

Then, the control signal φ3 is inverted to low level to turn on all the bit line selection switches, and the control signal φ2 is inverted to high level to turn on the equalizing MO8FET.
When Q9 is turned on, all complementary bit lines with supply voltage Vdd and ground voltage vss as a pair are connected to the bit line selection switch and equalizing MO8FET in the on state.
Electrical conduction is established via the complementary common data line via Q9, whereby all the complementary bit lines are balanced and half precharged to a voltage approximately half of the power supply voltage Vdd.

According to the above embodiment, the following effects can be obtained.

(1) That is, complementary common data lines CD, 'C to which complementary bit lines are commonly connected via a bit line selection switch
By arranging the equalizing MO8FETQ9 at D and controlling the bit line selection switch and the equalizing MO8FETQ9 to the on state during the non-selection period of the memory cell,
During the memory cell non-selection period, the bit line selection switch and equalizing MO8FETQ9 electrically conduct the complementary bit lines forced to the complementary attainment levels Vdd and Vss in response to the memory cell selection period, so that they are mutually connected. It can be precharged to a balanced level.

(2) Due to the above effects, it is possible to perform half precharging of the bit line without requiring a dedicated precharging circuit for each complementary bit line. This eliminates the need to provide a precharge circuit. In the case of this embodiment, the complementary common data line C
It is only necessary to arrange the equalizing MO8FETQ9 at the required positions of D and CD, and to add logic to the timing control circuit 12 to control all the bit line selection switches to be in the on state during the chip non-selection period. Therefore, the chip area occupied by dedicated circuit elements provided for precharging the complementary bit lines can be significantly reduced, thereby further increasing the storage capacity within the limited chip area. It becomes like this.

(3) As the number of equalized MO5FETQ9 increases, the number of short-circuit paths for complementary bit lines increases, and accordingly, the bit line precharge speed can be increased.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, in the above embodiment, the installation location of the equalizing MO8FETQ9 with respect to the complementary common data line is not particularly limited.
When adopting a word shunt structure for the word line, in which an aluminum wiring is connected to a polysilicon wiring that also serves as the gate electrode of the ET, and the polysilicon wiring is divided at strategic points, the shunt section is free. Equalizing MO8FETs for the common data line can be placed in the area.

Further, when the memory cell array is divided into a plurality of memory mats, equalizing MO8FETs can be arranged in the boundary areas of the memory mats.

In the above explanation, the invention made by the present inventor was mainly applied to DRAM, which is the field of application that formed the background of the invention, but the present invention is not limited thereto, and is applicable to pseudo-static RAM and other semiconductors. It can be widely applied to storage devices. The present invention can be applied at least to conditions where complementary bit lines are precharged.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, an equalize switch is placed on a complementary common data line to which complementary bit lines are commonly connected via a bit line selection switch, and the above-mentioned pin 1-
By controlling the line selection switch and the equalization switch to be in the on state, there is an effect that half precharging of the pin 1 to line can be performed without requiring a dedicated precharging circuit for each complementary bit line.

Therefore, it is no longer necessary to provide a dedicated precharge circuit for each complementary bit line as in the past, and the area occupied by the circuit elements for precharging the complementary bit lines can be significantly reduced. and this allows
This can contribute to improving the storage capacity and degree of integration of semiconductor memory devices.

By arranging a plurality of equalization switches at different positions on the complementary common data line depending on the length of the allowable precharge period, the bit line precharge speed can be easily increased.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the main parts of a DRAM according to an embodiment of the present invention, FIG. 2 is a block diagram schematically showing the entire DRAM shown in FIG. 1, and FIG. 5 is a timing chart showing an example of a bit line precharge operation. 1...Memory cell array, 2...Y switch circuit,
5...X address decoder, 7...Y address decoder, 8...Sense amplifier array, 9...Bit line selection switch, 10...Sense amplifier, 11...Memory cell, 12...・Timing control circuit, BLi, B
Li complementary bit line, CD, CD...complementary common data line, Q8...pull-up MO8FET, Q9...equalize MO8FET, φ□, φ2. φ3...Control signal, YSWi...Bit line selection signal.

Claims (1)

[Claims] 1. A plurality of memory cells arranged in a matrix, a word line coupled to a selection terminal of the memory cell, a complementary bit line coupled to a data input/output terminal of the memory cell, and a complementary bit. A bit line selection switch connected to each complementary bit line to select a line, a complementary common data line to which the bit line selection switches are commonly connected, and an equalization switch that selectively shorts the complementary common data line. ,
A semiconductor memory device comprising: a control circuit that controls the bit line selection switch and the equalization switch to be in an on state during a non-selection period of a memory cell. 2. Claim 1, wherein a plurality of the equalize switches are arranged at different positions on the complementary common data line.
The semiconductor storage device described in 1.