JPH02249178A - Compressed voice signal reproducing device - Google Patents

Abstract

PURPOSE:To reproduce every kind of recorded pattern in conformity with a format by managing whether or not a memory is set at a writable state by a system control part. CONSTITUTION:A writable signal is generated by detecting whether or not the compressed voice signal of the next track can be written on the memory 33 by a writable signal generating part 10. The writable signal is managed by the system control part 52. In such a way, it is possible to supply a write instruction timely, and to easily reproduce even every kind of recorded pattern in conformity with the format without generating interruption even when the small capacity memory is used.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a compressed audio signal reproducing apparatus for reproducing a time-base compressed audio signal recorded on a magnetic disk by, for example, a video floppy recorder.

Conventional technology In recent years, instead of cameras that use film, video floppy recorders that record still images on 2-inch floppy disks (hereinafter referred to as video floppy disks) have been commercialized, and in the future, various products will be used to record still images. is expected to produce.

The compressed audio signal reproducing apparatus as described above will be described below with reference to the drawings.

FIG. 4 is a block diagram showing a video floppy audio recording device as an example of a device for recording and reproducing time-base compressed audio signals;
FIG. 5 shows the recording format of the audio signal. Figure 5 (
5A is a diagram showing a track format, FIG. 3B is a diagram showing a sector format, and FIG. Further, FIG. 6 is a block diagram of the video floppy audio reproducing apparatus, and FIG. 7 is a diagram showing memory address values and waveforms of various parts during reproduction.

This will be explained below using FIG. 4.

As is well known, the video floppy 40 has 50 concentric tracks extending from the outside to the inside, and a video signal (still image) or an audio signal is recorded on each track. Also, the rotation speed of the video floppy 40 is 3 B 00 r p
ml In other words, since it rotates once every 1760 seconds, a video signal is compressed into one field on each track, and an audio signal is compressed into 1760 seconds on the time axis and recorded.

The time axis compression ratio of the audio signal is 320 times, 640 times,
Three modes of 1280x are available, and it is possible to record audio signals of approximately 5 seconds, approximately IO seconds, and approximately 20 seconds on one track, respectively.

As shown in FIG. 4, the audio signal is input from an input terminal 1 to a low pass filter (LPF) 30 to be band limited, and then input to a time axis compression circuit 31.

The time axis compression circuit 31 is well known and includes an A/D converter 32 that converts an analog audio signal into a digital signal, a memory 33 that stores the digital signal, and a D/A converter that converts the digital signal into an analog signal. It is constituted by a container 34.

The signal input to the time axis conversion circuit 31 is converted into a digital signal by the A/D converter 32. Thereafter, it is written into the memory 33 at the write clock frequency fw. After this writing is completed, the data is read out at the read clock frequency fr, and converted into an analog signal by the D/A converter 34. Time axis conversion rate K of time axis conversion circuit 31
c is expressed by the following formula.

Kc=fw/fr When Kc<1, the time axis conversion circuit 31 operates as a time axis compression circuit, and when Kc>1, the time axis conversion circuit 31 operates as a time axis expansion circuit.

During recording, the time axis conversion circuit 31 operates as a time axis compression circuit and outputs a compressed audio signal whose time axis has been compressed to 1/GO seconds. The adder 35 adds a control code and a flag to this compressed audio signal. After that, a pre-emphasis circuit 38, an FM modulation circuit 37. The video floppy 4 passes through the amplifier 38 and is read by the magnetic head 39.
Recorded as 0.

Next, the recording format of the audio signal will be explained using FIG. FIG. 5(a) is a diagram showing the track format. DSP stands for data Φ start φ point and corresponds to the conventional PG yoke. The compressed audio signal and control code are recorded divided into four sectors, with a space between each sector. Figure (b) and (
-C) is a diagram showing the sector format. The start flag and end flag indicate the beginning and end of a sector, and serve as a time axis reference when reproducing a compressed audio signal. The control code is information possessed by the audio signal (for example, the track number where the corresponding video signal is recorded, the audio compression ratio, the track number where the continuation of this compressed audio signal is recorded, etc.). The same compressed audio signal as the last part of the compressed audio signal of the previous sector is recorded in the overlap.

Furthermore, although the start flag is a positive signal in FIG. 5(b), it becomes a negative signal when, for example, no compressed audio signal is recorded in this sector. Further, the end flag is a negative signal, but becomes a positive signal when, for example, recording of the compressed audio signal ends in this sector and does not continue to the next sector. That is, the polarity of these two flags represents the sector type. There are four types of sectors: Type 1 is the type that continues on the next sector on the same track. Type 2 is the type that follows sector 0 of the next track. Type 3 indicates the last sector of the sequence and type 4 indicates an unused sector.

The reproduction operation of a compressed audio signal recorded in the above format will be explained using FIGS. 6 and 7.

40 is a video floppy, 50 is a magnetic head, and 51 is a head access section for moving the magnetic head 50 to an arbitrary track. 52 is a system control unit which gives access instructions to the head access unit 51 so that the magnetic head 50 accesses a desired track;
It gives a write instruction to the read/write signal generating section 56. 53 is an amplifier that amplifies the audio signal read from the magnetic head 50, 54 is an FM demodulation circuit, and 55 is a de-emphasis circuit. Reference numeral 31 denotes the time axis conversion circuit mentioned earlier, which operates as a time axis expansion circuit during reproduction. 32 is an A/D converter, 33 is a memory, 34 is a D/A
It is a converter. 33a is a digital data input terminal;
33b is a read/write terminal, 33c is an address designation terminal, and 33d is a digital data output terminal. The memory 33 inputs the digital data input terminal 33 when a high level signal is input to the read/write terminal 33b.
The data input to a is written to the address of the address designation terminal 33c. Also, when a low level signal is input to the read/write terminal 33b, the address designation terminal 3
Data is read from address 3c and output to digital data input terminal 33d. 56 is a read/write signal generation section, which includes a flag detection control circuit 56a, a flag detection circuit 56b, and a read/write signal generation circuit 56C.
Consists of. The flag detection control circuit 56a receives the write instruction signal and outputs a low level flag detection instruction signal (FIG. 7(a)) synchronized with the rotation of the video floppy 40 for one rotation period (one track). The flag detection circuit 56b detects a start flag and an end flag, and detects the flag only while the flag detection instruction signal is at a low level. The read/write signal generation circuit 56C receives the output of the flag detection circuit 5f3b, and
Outputs read write signal. Based on this read/write signal, the memory 55b performs a write operation and a read operation. 57 is an address control circuit, which includes a write address counter 57a and a read address counter 5.
7b and an address selection circuit 57c. The address selection circuit 57c inputs the above-mentioned read fist write signal and switches between the output of the write address counter 57a and the output of the read address counter 57b alternately as appropriate.
Give the address to c.

The operation of the above circuit will be explained.

FIG. 7 shows an example of the reproduction operation of a continuous compressed audio signal over two tracks, the first track and the second track. During reproduction, the output of the magnetic head 50 passes through the amplifier 53,
The frequency is demodulated by the FM demodulation circuit 54. after that,
Passing through the de-emphasis circuit 55, the time axis conversion circuit 31
(time axis expansion circuit). Time axis conversion circuit 31
The input signal is converted into a digital signal by the A/D converter 32. Thereafter, it is written into the memory 33 at the write clock frequency fw. After this writing is completed, it is read out at the read clock frequency fr,
The D/A converter 34 converts the signal into an analog audio signal.

A write instruction signal is output from the system control unit 52 to the flag detection control circuit 56a, and a write instruction is given.

As a result, the flag detection control circuit 56a outputs a low-level flak detection instruction signal (FIG. 7(a)) synchronized with the rotation of the video floppy 40. This is the period shown in FIG. 7(A). The detection of the flag is performed only during the period when the flag shown in FIG. be done.

The compressed audio signal of sector 0 of the first track, which is input to the time axis conversion circuit 31 and converted into a digital signal by the A/D converter 32, is written to addresses AB of the memory 33.

FIG. 7(b) shows the address value of the write address counter 57a, and FIG. 7(C) shows the address value of the read address counter 57b, and the shaded area indicates that the address counter is in an incrementing state. Similarly,
The compressed audio signal of sector 1 of the first track is placed at address B-C, the compressed audio signal of sector 2 of the first track is placed at address CD, and the compressed audio signal of sector 3 of the first track is placed at address D-E.
A compressed audio signal is written. After the writing of compressed audio signals in the four sectors (sectors 0 to 3) of the first track is completed, a reading operation from the memory 33 is started. The address is sequentially incremented from address A, passing through address B, address C, and address D. This situation is shown in FIG. 7(C).

The read signal is converted into an analog signal by the D/A converter 34. However, since the first track and the second track are continuous audio signals, writing of the compressed audio signal on the second track must be completed by the time address E is reached. For this purpose, after writing the compressed audio of the first track into the memory 33, the system control section 52 gives an access instruction to the head access section 51 to cause the magnetic head 50 to access the second track.

Then, a write instruction signal is output from the system control section 52, and the compressed audio signal of the second track is written into the memory 33. This is the period shown in FIG. 7(B).

In period (B), the compressed audio signal of sector O of the second track is written to addresses EF of the memory 33, as in period (A). Similarly, the compressed audio signal of sector 1 is written to addresses FG, the compressed audio signal of sector 2 is written to address GH, and the compressed audio signal of sector 3 is written to address HI.

After the writing of the compressed audio signal in the four sectors (sectors 0 to 3) of the second track is completed, and after the reading of the compressed audio signal of the first track is completed (address E), the read operation for the second track is continued. is started. Ink is indented in order from address E, passing through address F, address G, and address H. This situation can be seen in the seventh
Shown in Figure (C). When the read address reaches I, this series of reproduction operations ends.

Problems to be Solved by the Invention However, in order to realize the above operation, it is necessary to give a write instruction from the system control unit 52 to the flag detection control circuit 56a in a timely manner.

As a conventional example, it is assumed that up to sector 3 of the first track is used, but sector 3 may be unused. In that case, only addresses A to D are used for writing into the memory 33 of the first track, and the write instruction must be given before the read address reaches D. Similarly, it is possible that only sector 2 of the first track is used, and in extreme cases, only sector O may be used. Further, even if all four sectors are used, sector 3 is a type 2 or type 3 compressed audio signal in which the length is not constant. For this reason, the address required to write one track's worth of compressed audio signals from sector O to sector 3 is not uniquely determined. Therefore, in order to issue write instructions in a timely manner and reproduce sound without interruption, it is necessary to increase the memory capacity, for example, by providing a memory for two tracks.

Furthermore, in order to achieve this with the memory 33 having a capacity of less than two tracks, it is not possible to write immediately after writing, and it is necessary to wait until the writable memory capacity becomes one track. , it becomes very difficult. The smaller the memory capacity, the more sensitive the timing of issuing a write instruction, and it was almost impossible to achieve this using a memory of less than two tracks.

The present invention has been made in view of the above problems, and has the advantage of being able to reproduce any recording pattern that conforms to the format by having the system control unit 52 manage whether or not the memory 33 is in a writable state. The present invention provides a compressed audio signal reproducing device.

Means for Solving the Problems In order to achieve the above object, the present invention provides a compressed audio signal reproducing apparatus comprising: a medium having sector areas provided at predetermined intervals and into which compressed audio signals are divided and recorded; A head for reproducing the medium on which a compressed audio signal of an arbitrary length has been recorded; a head access unit for moving the head to an optimal position on the medium; and a reproduction signal processing unit for performing signal processing using the output signal of the head as input. an A/D converter that converts the compressed audio signal output from the reproduced signal processing section into an analog/digital signal; a memory section that stores the audio data output from the A/D converter; and the memory section. an address control unit that controls write and read addresses of the memory unit; a read/write signal generator that receives the output of the playback signal processing unit and controls write and read addresses of the memory unit; and an address control unit that controls write and read addresses of the memory unit; a D/A converter that converts output data from digital to analog and outputs an audio output signal; and a write device that detects whether or not writing to the memory section is possible based on the output address signal by the address control and outputs a write enable signal. a enable signal generation unit; receiving the write enable signal as input and giving an access instruction to the head access unit to move the head to a desired position on the medium; and if the memory unit is writable, the A and a system control section that gives a write instruction to the read/write signal generation section to write the audio data output from the /D converter into the memory.

Effect of the Invention With the above-described configuration, the present invention detects whether or not the compressed audio signal of the next track can be written to the memory by the write enable signal generating section, and generates the write enable signal. By managing this write enable signal in the system control unit, it is possible to give write instructions in a timely manner, and even if a small capacity memory is used, any recording pattern that conforms to the format can be easily reproduced without interruption. becomes possible.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a video floppy audio reproducing apparatus according to an embodiment of the present invention. In the figure, 40 is a video floppy, 50 is a magnetic head, and 51 is a head access unit that moves the magnetic head 50 to an arbitrary track. It constitutes a signal processing circuit.

53 is an amplifier, 54 is an FM demodulation circuit, and 55 is a de-emphasis circuit. Reference numeral 52 denotes a system control unit, which inputs the write enable signal and gives an access instruction to the head access unit 51 so that the magnetic head 50 accesses a desired track, and also controls the read/write signal generation unit 56.
It gives writing instructions to. 31 is the time base conversion circuit mentioned above, 32 is an A/D converter, 33 is a memory, and 34 is a D/A converter. 33a is a digital data input terminal, 33b is a read/write terminal, 33
C is an address designation terminal, and 33d is a digital data output terminal. Reference numeral 56 is a read/write signal generating section, and a flag detection control circuit 56a.

It consists of a flag detection circuit 58b and an IJ-do/write signal generation circuit 5Eic. Reference numeral 57 denotes an address control circuit, which includes a write address counter 57a, a read address counter 57b, and an address selection circuit 57c.

The above is the same as the conventional example, and will not be explained here.

10 is a write enable signal generation circuit. The write enable signal generation circuit 10 includes a final address holding circuit 10a,
It is composed of an arithmetic circuit 10b and a comparison circuit 10c. The final address holding circuit 10a temporarily holds the final address of the write address counter 57a when the compressed audio signal of each sector is written to the memory. The arithmetic circuit 10b subtracts a predetermined value from the output of the final address holding circuit 10a and outputs the result. Further, the comparison circuit 10c compares the output of the arithmetic circuit 10b and the output of the read address counter 57b, and outputs a write enable signal to the system control unit 52.

As in the conventional example, the operation of reproducing a continuous compressed audio signal over two tracks, the first track and the second track, will be explained using FIG. 2 as an example.

FIG. 2(a) shows a flag detection instruction signal which is an output of the flag detection control circuit 56a, and a low level indicates a flag detection period. The figure (b) shows the write address counter 57.
The address value W(t) of a, and FIG. 5C shows the address value Y(1) of the read address counter 57b, and the shaded area indicates that the address counter is in an incrementing state. 4(d) shows the output of the final address holding circuit 10a, and FIG. 2(e) shows the output of the arithmetic circuit 10b. Further, (f) in the same figure shows the output of the write enable signal generation circuit, and a high level indicates that writing is possible.

The period (A) in FIG. 2 shows the writing of the compressed audio signal on the first track, and the period (B) shows the writing of the compressed audio signal on the second track.

First, a write instruction signal from the system control unit 52 is output to the flag control circuit 5ea, and a write instruction is given. As a result, the flag detection control circuit 58a
outputs a low level flag detection instruction signal (FIG. 2(a)) synchronized with the rotation of the video floppy 40. This is the period shown in FIG. 2(A). The detection of the flag is performed only during the period when the flag shown in FIG. be done.

The compressed audio signal of sector 0 of the first track, which is input to the time axis conversion circuit 31 and converted into a digital signal by the A/D converter 32, is written to addresses A-H of the memory 33.

At this time, since the final address of sector O is address B, the output of the final address holding circuit 10a (see FIG.
d)) becomes B. This value B is held until the final address C of sector 1 is input. Similarly, address B
The compressed audio signal of sector 1 of the first track is written to -C, the compressed audio signal of sector 2 of the first track is written to address CD, and the compressed audio signal of sector 3 of the first track is written to address D-E. , when all the compressed audio signals of the first track have been written, the final address holding circuit 10a outputs E. Also, at this time, the arithmetic circuit 10b outputs (EX) by subtracting the predetermined value x (x>O) (see FIG.
e)).

After the writing of compressed audio signals in the four sectors (sectors 0 to 3) of the first track is completed, the reading operation from the memory 33 is started. The read address counter increments sequentially starting from address A.
It passes through address B, address C, and address D.

This situation is shown in FIG. 2(c).

However, since the first track and the second track are continuous audio signals, the compressed audio signal of the second track is transferred to the memory 3 by the time the read address Y(t) reaches the address E.
It is necessary to write to 3.

By the way, since the read address Y(t) is sequentially incremented, (E-x) always exists before reaching the address E. Therefore, the comparison circuit 10c compares the output (E-X) of the arithmetic circuit 10b (FIG. 2(e)) with the read address Y(t) (FIG. 2(C)), and (E-x) ≦Y (t)≦E A high level signal is output while (1) is satisfied. Although X will be described later, the fact that this equation holds indicates that the memory 33 is writable, and hereinafter this will be referred to as a writable signal.

Next, a write operation of the compressed signal of the second track is performed.

After writing the compressed audio signal of the first track into the memory 33, the system control section 52 instructs the head access section 51 to move the magnetic head 50 to the second track. Then, after confirming that the memory is in a writable state based on the writable signal, a write instruction is given. (B) The compressed audio signal of sector O of the second track is written to F. Similarly, the compressed audio signal of sector 1 is written to address FG, the compressed audio signal of sector 2 is written to address GH, and the compressed audio signal of sector 3 is written to addresses H to ■.

After the writing of the compressed audio signal in the four sectors (sectors O to Sector 3) of the second track is completed, and after the reading of the compressed audio signal of the first track is completed (address E), the read operation for the second track continues. is started. Increment sequentially from address E, address F,
It passes through address G and address H. This situation is shown in FIG. 2(d). When the read address value Y(t) becomes I, this series of reproduction operations ends.

Next, the above-mentioned X will be described.

Consider implementing the above operation using a memory with a capacity greater than one track and less than two tracks.

Initially, nothing is stored in memory. Therefore, the first track can be written without any problem. However, since the memory capacity is less than two tracks, the remaining unrecorded portion is less than the capacity of one track. Therefore, it is not possible to continue writing to the second track. The second track becomes writable when the first track begins to be read and the remaining unrecorded portion and the read portion of the first track total one track.

Here, let M be the total number of addresses that the memory has.

If the number of addresses required to store one sector of compressed audio signal is S, then one track is 4*S. Since the memory capacity is less than 2 tracks, 4*S<M<8*
M Therefore, after writing the compressed audio signal on the first track, the remaining unrecorded address is (M-4*S), and M-4*S<4*S. When reading of the written first track starts and there are X addresses remaining, the number of new addresses that can be recorded is the number of addresses that have already been read (4*5-x) and the unrecorded addresses (M-4*S). ) is the sum of

When this sum becomes one track, the write instruction signal for the second track can be output for the first time.

(M-4*S) +(4*5-x)≧4*S, °, X
5M-4*S Therefore, it is sufficient to set X within the above range, for example, x=M
By setting -4*S, it becomes possible to output a write enable signal.

As described above, according to this embodiment, the system control unit can easily issue a write instruction by managing this write enable signal.

Furthermore, the present invention is very effective even when the compressed audio signal recorded on one track is very short and may extend over a plurality of tracks as described below.

FIG. 3 shows an example of this, in which only sector O of the first track is used and the recorded compressed audio signal is very short. In such a case, a write enable signal may be output even though data has been written to the memory 33. This is because (B-A) < x holds true because the compressed audio signal written to the memory 33 is short, and (B-x) < A. In other words, when the writing is finished, the expression (1) is already satisfied. ) is established. In other words, memory 33
This indicates that there is still room to write one or more tracks worth of compressed audio signals in the unrecorded portion. In this case,
Before reading from the memory 33, the compressed audio signal of the first track is written again. System control unit 52
As a result, an access instruction is given to the head moving unit 51 to cause the magnetic head 50 to access the second track. Then, the compressed audio signal of the second track is written into the memory 33. After writing is completed, read operation is performed after confirming that the write enable signal is not output.

However, if the write enable signal is still being output, the third track is accessed again and writing is performed. This process is continued until writing is no longer possible, and a read operation is performed only when writing becomes impossible.

This also applies during reading.
If the write enable signal is output even though writing has been performed, the magnetic head 5 is immediately moved to the next track.
0 is accessed and written to the memory 33.

As described above, even if there is a track in which a very short compressed audio signal is recorded, it can be detected at the time of writing. Therefore, it is possible to write the compressed audio signal recorded on the next track in advance, and it is possible to reproduce the sound without interruption.

In addition, in the formula (1) of the above example, for convenience, (E-x
)≦Y (t)≦E However, the memory address is usually in a loop, and in the case of a loop, the above equation holds true only when E≧X, and when E<x, Y (t)≦Eor(E-x)≦Y(t).

Also, in the above embodiment, x=M-4*S, but for example, if the number of addresses of the read address counter that is incremented per second is X, then X9≦xmax, (=M-4*S ), it is possible to set X = X II. In this case, the write enable signal will be output from one second before the end of reading of the audio signal currently written in the memory.

Furthermore, if this write enable signal is output even though writing has been performed, this indicates that the written compressed audio signal is 1 second or less.

This is very effective as a time reference for writing and reading when accessing and reproducing a track in which an image corresponding to an audio signal is recorded during a free time between writing compressed audio signals.

Effects of the Invention As is clear from the above embodiments, the present invention is capable of detecting whether or not a memory is writable by comparing a write address and a read address, and outputting a writable signal. By managing this write enable signal in the system control section, it becomes possible to sufficiently realize the present invention even using a small capacity memory that is less than two tracks worth.

In addition, even if there is a track on which a very short compressed audio signal is recorded, this can be detected when writing to memory, so the compressed audio signal of the next track can be written in advance, and the audio signal can be played without interruption.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a compressed audio signal reproducing device according to an embodiment of the present invention, FIGS. 2 and 3 are relational diagrams showing waveforms and values of each part of the device, and FIG. 4 is a video floppy audio Figure 5 is a block diagram of a recording device that records signals and shows the same track format. FIG. 6 is a block diagram showing an example of a video floppy audio reproducing device, and FIG. 7 is a relational diagram showing waveforms and values of each part thereof. 10...Writable signal generation circuit, 10a...
・Final address holding circuit, 10b... arithmetic circuit,
10c... Comparison circuit, 32... A/D converter,
33...Memory, 34...D/A converter,
40... Video floppy, 50... Magnetic head, 51... Head access section, 56... Read/write signal generation section, 52... System control section, 57... Address control circuit. Name of agent: Patent attorney Shigetaka Awano

Claims (2)

[Claims] (1) A medium having sector areas provided at predetermined intervals and into which compressed audio signals are divided and recorded; a head for reproducing the medium on which compressed audio signals of arbitrary length are recorded; a head access unit that moves the head to an optimal position; a playback signal processing unit that inputs and processes the output signal of the head; and an A/D conversion unit that converts the compressed audio signal output from the playback signal processing unit from analog to digital. a memory section that stores audio data output from the A/D converter; an address control section that controls write and read addresses of the memory section; a read/write signal generation section that controls writing and reading to and from the memory section; a D/A converter that converts audio output data read from the memory section into digital/analog and outputs an audio output signal; a writable signal generating section that detects whether or not writing to the memory section is possible based on an output address signal and outputs a writable signal; and a writable signal generating section that receives the writable signal and moves the head to a desired position on the medium. give an access instruction to the head access section, and if the memory section is writable, write instructions to the read/write signal generation section to write the audio data output from the A/D converter into the memory; A compressed audio signal reproducing device comprising: a system control unit that provides (2) The address control unit includes a write address counter, a read address counter, and an address selection circuit that selects an output of the write address counter and an output of the read address counter, and the address control unit is configured to generate the write enable signal. The unit includes a final address holding circuit that holds the final address of the write address counter, an arithmetic circuit that subtracts a predetermined value from the output of the final address holding circuit, and a comparison between the output of the arithmetic circuit and the output of the read address counter. 2. The compressed audio signal reproducing apparatus according to claim 1, further comprising a comparison circuit that performs the following.