JPH02248874A - Trouble judging system - Google Patents

Abstract

PURPOSE:To judge the presence of troubles of individual circuits to be tested accurately by displaying an input/output data, a simulation signal and an observation data based on a program incorporated by the same logic as the circuits to be tested in correspondence together with a logic diagram of the circuits. CONSTITUTION:In a security case disc 1, an input signal is normally OFF while a security operation is not demanded. Test interfaces 4b and 4c of a fault judging device 4 output a simulation signal to an input point of a semiconductor logic circuit 2 as security system circuit to be tested to pick up observation data obtained an intermediate point and an output point of a semiconductor logic circuit 2. A microprocessor and a process input/output section 4a obtains an input/output data according to a program incorporated by the same logic as that of the semiconductor logic circuit 2. Input/output data of the microprocessor and the process input/output section 4a and the simulation signal and the observation data at the semiconductor logic circuit 2 are shown on a CRT display device 4e together with a logic diagram of the semiconductor logic circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a failure determination system for determining the presence or absence of a failure in a measurement control device in a nuclear reactor control protection system or the like.

[Conventional technology]

Figure 6 shows, for example, Mitsubishi Electric Technical Report Vol. 1-49, No.
4 +1975, P2S5-P365 is a circuit configuration diagram showing a conventional test device for measurement and control equipment, in which 101a to 101d are detectors of protection system channels, 102a to 102d are instrument racks, and 103
a to 103d are bistables, 104 is a safety protection relay rack, 105a to 105d are bistable relays, 106a to 106d are test switches, 107 is a relay logic circuit, 10B is a test indicator light, 109 is a resistor, and 110a is a mask relay 110b is a contact point of mask relay 110a, 111a is a slave relay 111
b is the auxiliary contact of the slave relay 111a, 112a, 1
12b is a relay power line, 113 is a switchgear, 11
3a is a closing coil of the switching device 113, and 113b is a power source for the closing coil 113a.

The measurement and control equipment of the nuclear reactor control protection system is required to periodically check the health of the Ja capacity even during plant operation. For this reason, the measurement control device of the control protection system is made redundant, and includes the above-mentioned test device for functional confirmation testing.

Next, the operation will be explained. Detectors 101a to 101d
The signals from the bistables 103a to 103d of the instrument ranks 102a to 102d are converted into on/off signals. The outputs of the bistables 103a to 103d are connected to each bistable relay 105a of the safety protection relay rack.
~105d is driven. The high stable relays 105a to 105d are normally energized to ensure a fail-safe safety protection system such as a reactor control protection system.

For this purpose, the contacts of bistable relays 105a to 105d and an auxiliary relay (not shown) constitute a necessary relay logic circuit 107, and this output drives master relay 110a. Furthermore, this mask relay 1
The contact 110b of 10a is further connected to the slave relay 111a.
Then, the auxiliary contact 1llb of this slave relay 111a drives the switching device 113.

Next, we will describe the function confirmation test method. In the test, one of the test switches 106a to 106d is manually pressed, and the corresponding bistable relay 105a-10
5d is de-energized and the logic condition is satisfied.
The mask relay 110a is energized, that is, the test indicator light 10B lights up, and the return of the test switch 106 is confirmed by the mask relay 110a being de-energized, that is, the test indicator light 10B turns off. do.

For example, if the relay logic circuit 107 is a 2/40 thick circuit, there are 16 combinations of human input signals. Basically, it is impossible to confirm that the relay logic circuit is sound unless all of these combinations are implemented.

It is also possible to install the test indicator light 10B inside the relay logic circuit 107, but since the circuit becomes complicated and the installation space becomes a problem, one test indicator light 10B is installed at the final stage of the relay logic circuit 107. There is.

[Problem to be solved by the invention]

Since the conventional measurement control device test device is configured as described above, if the test target circuit that constitutes the measurement control device is in failure, for example, the bistable relay 105 a
-It is not possible to identify and display which of the 105d is faulty.
When the operator detects the manual conditions under which a defect has occurred, for example, the detector 101
There are problems in that it is necessary to estimate from the output state of a-101d or to actually measure the voltage at each part of the circuit.

This invention was made to solve the above problems, and by applying a simulated signal to the circuit under test in the measurement control device, it is possible to determine the presence or absence of a failure in each circuit under test as a positive value. The purpose of this study is to obtain a failure determination system for measurement and control equipment.

[Means to solve the problem]

The failure determination system according to the present invention outputs observed data from the intermediate point and output point of the circuit under test by inputting a simulated signal from the output test interface to the human input point of the circuit under test. is input into the input test interface, and on the other hand, the microprocessor and process input/output section obtain input/output data based on a program configured with the same logic as the circuit under test, and combine this input/output data with the above simulated signal and observation. The data is displayed on a CRT display along with a logic diagram of the circuit under test.

[For production]

The failure determination system of the present invention is executed using a program that uses simulated signals to the input points of a plurality of circuits under test, observation data obtained at each intermediate output point, and the same logic as the circuit under test. By displaying the input/output data along with the logic diagram on the CRT screen of the failure determination device, it is possible to easily find logic elements for which observed data different from the input/output data executed by the above program has been obtained. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a solid-state safety protection sequence board, 2 is a semiconductor logic circuit as a circuit to be tested, 3 is a power interface card, and 4 is a failure determination device, which includes a microprocessor sensor, process input/output section (hereinafter referred to as C
(referred to as PU, PIO) 4a, test interface (output) 4b, test interface (human power) 4c, CRT
It consists of an interface (communication) 4d and a CRT display 4e. Reference numeral 5 denotes a switching device, which is composed of a closing coil 5a and a power source 5b. The CRT display 4e displays the status of input/output data based on logic diagrams, observation data, and built-in programs, and is connected to the CRT interface 4d as necessary.

Next, the operation will be explained. First, the semiconductor logic circuit 2 is composed of a majority logic such as an AND gate, an OR gate, 2/4, and a timer circuit module, and receives an input signal from another device (not shown) and when a logic condition is satisfied. , outputs the switchgear MU at signal to the power interface car F'3. The power ink face card 3 is composed of an interboring logic section 3a and a power output section 3b. The power of the Vosing logic signal is amplified so that it can drive the switching device 5. Failure determination device 4 Test interface (output) 4
A simulated input signal SS is injected into the input of the semiconductor logic circuit 2 through the test interface (input) 4c, and observed data at intermediate points and output points in the semiconductor logic circuit 2 are read through the test interface (input) 4c.

In the safety protection sequence panel l, human input signals from other devices are basically contact signals or open collector signals, and during normal operation, that is, when no safety protection operation is required, the input signal is normally OFF. There is.

The test interfaces 4b and 4c have a function of separating the semiconductor logic circuit 2 and power interface card 3, which are safety protection circuits, from the CPU and the PI04a, and also have a function of reducing the number of digital input points and digital output points. have

If you reduce the range of circuits to be tested (fine division and increase the number of test circuits) and increase the number of signal feedback points, it will be easier to identify faulty hardware, but test interface cards and P Since the number of 0 cards increases and the test data also increases, it is necessary to consider the trade-off between the two and decide on the division of the test target circuit and intermediate signal points.

FIG. 2 shows an example of the semiconductor logic circuit 2 shown in FIG. 1, which includes logic components PI, P2, . P3. Consists of P4, and gate,
OR GATE 2 NOT GATE.

Each circuit such as majority logic and timer is configured as a logic module. TPI to TP8 are test points connected to the output line of the logic module. When the entire semiconductor logic circuit 2 shown in FIG.
P4 becomes the simulated signal injection point, and test point TP
5~TPIII is medium L'? and becomes the observation point for the output signal.

FIG. 3 shows a specific logic applied to the logic components PI-P4 of the semiconductor logic circuit 2 shown in FIG. That is, the logic component Pl is an AND gate, P
2 is an OR gate, P3 is a NOT gate, and P4 is an AND gate. In addition, in this invention, the failure determination device 4 shown in FIG. 1 also has a built-in program that performs the same operation as the logic shown in FIG. Set it and run the program. And test points TP5~TP
The program execution result for the point corresponding to O can be checked. On the other hand, the CRT display 4e in FIG. 1 displays the same logic diagram as in FIG. Make it possible to display output data simultaneously on the logic diagram. For example, as shown in Figure 4, the simulated signal injected into the actual logic circuit and the observed data observed from the intermediate point and output point are shown as solid lines, and the status of input/output data according to the built-in program is shown as broken lines. In addition, the ON signal is represented by a yellow line, and the OFF signal is represented by a green line (.If you do this, you can immediately visually find out where the signal status differs between the solid line and the broken line. , a faulty logic component can be easily determined.

In the above embodiment, a case was described in which failure determination was made in a logic circuit, but in the case of analog circuits such as differentiation, integration, and -order lag, if the same behavior as the circuit under test can be realized by a program, Cf? The T display 4e has a differential element,
Integral elements, -order lag elements, etc. can be displayed as a package, and the voltage applied to and observed in the analog circuit is CR
Numerical values can also be displayed on the input and output lines of the analog circuit components on the T display 4e. In this case, as shown in Fig. 5, the voltage values applied and observed to the circuit under test having circuit components 51, 52, 53 are shown on each line, and the input/output data of the program is shown on each line. One possible method is to display them individually by enclosing them in parentheses below.

〔Effect of the invention〕

As described above, according to the present invention, the circuit under test is
The CRT display simultaneously displays the states of the simulated signals and observed signals applied for testing, and the correct input/output signal states of the circuit under test obtained by executing the built-in program. Since it is configured so that it can be displayed on the top, there is an effect that the fault location of the circuit under test can be easily determined visually.

[Brief explanation of drawings]

Fig. 1 is a block connection diagram showing a failure determination system according to an embodiment of the present invention, Fig. 2 is a block connection diagram showing a circuit to be tested in this invention, and Fig. 3 is a concrete diagram of the circuit to be tested in Fig. 2. 4 is a display diagram showing the logic circuit shown in FIG. 3 displayed on a CRT display of a failure determination device. FIG. 5 is a logic circuit diagram showing the logic circuit shown in FIG. A display diagram showing a state in which the circuit is displayed on a CRT display of a failure determination device, and FIG. 6 is a block connection diagram showing a measurement control device incorporating a conventional test circuit. 2 is a circuit to be tested, and 4a is a microprocessor. Process input/output section, 4b is an output test interface, 4C is an input test interface, and 4e is a CRT display. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation

Claims (1)

[Claims] A test target circuit consisting of multiple test targets, an output test interface that outputs a simulated signal to the input point of this test target circuit, and observation data obtained at the intermediate point and output point of the test target circuit. A test interface for input to be imported, a microprocessor and process input/output unit that obtains input/output data by a program configured with the same logic as the circuit under test, and the input/output data of this microprocessor and process input/output unit, and the above test target. A failure determination system comprising a CRT display that displays the simulated signal and observed data in the circuit together with a logic diagram of the circuit to be tested.