JPH02246548A - Method and device for step-out decision making - Google Patents

Abstract

PURPOSE:To correctly discriminate between carrier nondetection due to variation of transmission characteristics of a transmission line and carrier nondetection due to the end of a communication by making a step-out decision only when a carrier is not detected continuously for specific plural cycles. CONSTITUTION:Whether or not there is the carrier is detected according to the correlation signal between a received signal and a code sequence with specific code length. A step-out decision circuit 29 makes the step-out decision unless a carrier detection signal PAS is outputted continuously for specific plural data sections. Consequently, the temporary carrier nondetection due to the variation of the transmission characteristics of the transmission line, etc., and the carrier nondetection (correctly is step-out) due to the end of the communication are clearly discriminated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a receiving device for spread spectrum (SS) communication, particularly for code shift keying (Code Shift Keying).
The present invention relates to a method and apparatus for determining out-of-synchronization in a receiving apparatus using a modulation method.

The conventional SSa communication system has a wide range of applications, including satellite communication, mobile communication, and power line communication. The conventional SS communication system will be explained with reference to FIG. m14 and FIG. 15. On the transmitting side, the output a of the PN (pseudo-noise) code sequence generator 1 is subjected to an EX-OR operation (signal C) with the transmitting data b in the EX-OR circuit 2 (signal C), and then sent to the transmission line as a transmitting signal by the amplifier 3. On the receiving side, the received signal is amplified by an amplifier 4, then correlated with the output d of the synchronous PN code sequence generator 5 by a correlator 6, and the correlation value (signal e) is compared with a predetermined threshold value by a comparator 7. Demodulate the received data f.

The transmission path may be wireless, wired, or other transmission media. Therefore, the transmission signal is not only sent directly to the transmission medium, but also often converted into a signal suitable for transmission through the transmission medium and sent. Also, power line communication requires an interface that separates it from commercial power. The connection portion with the transmission medium that performs such signal conversion and separation is hereinafter referred to as a reception interface and a transmission interface.

Problems to be Solved by the Invention In conventional communication systems, it is necessary to synchronize the PN sequence generated by the synchronous PN code sequence generator 5 on the receiving side with the PN sequence on the transmitting side. There is a need to. If there is no problem with the transmission characteristics of the transmission path, a peak is detected in the correlation waveform at the synchronization point. However, in power line communications, where the transmission characteristics are extremely poor and there is a dip reference point within the transmission band, the correlation waveform deteriorates and the relationship between positive and negative correlation values is reversed.

This may result in a 1.0 error in the data. Another drawback was that synchronization could not be maintained due to waveform deterioration.

The applicant has proposed a new C8K communication system that overcomes the drawbacks of the conventional SSa communication system described above.

In the C8K communication system, on the transmitting side, two binary PN code sequences with low cross-correlation and the same code length are generated at a constant cycle, and at each constant cycle, the above two PN code sequences are generated depending on whether the transmitted data is 1 or 0. One of the two different PN code sequences is selected and sent as a transmission signal. On the other hand, on the receiving side.

Two correlation outputs are obtained by correlating the received signal with the two PN code sequences used on the transmitting side. A correlation peak always appears in one of these two correlation outputs at each of the above-mentioned fixed periods. Therefore, based on the comparison of the peak values of the two correlation outputs, ti:a of l or 0 is calculated.
Create data.

In such a C9K communication system, the receiving side compares two correlation outputs and assigns 0 or 1 to the received data depending on the magnitude of the peak value, so the code sequence on the receiving side is the same as that on the transmitting side. There is no need to strictly synchronize with this, and data demodulation errors will not occur. Also as the output of the correlator.

By taking the absolute value, there is an effect that no error occurs even in the case of a transmission line whose characteristics are deteriorated such that the transmission peak value becomes negative.

As described above, a correlation peak appears in one of the two correlation outputs at each of the above-mentioned fixed periods. In order to correctly detect this correlation peak on the receiving side, it is necessary to synchronize the operation of the receiving side device with the received signal so that the correlation peak appears periodically within a certain period. especially,
In the case of tU power line communication, in a poor transmission path such as a commercial AC power line, the transmission characteristics may change rapidly and the peak position may vary greatly.

It is also necessary to correctly determine that the a transmission has ended (referred to as synchronization loss). Since a carrier is always detected during data reception, it is possible to determine whether or not data is being received based on the carrier detection signal.
Due to variations in transmission characteristics, carriers may not be detected even during data reception.

The present invention provides a method and apparatus that are suitable for a receiving apparatus for the CSK borrowing system having the excellent features described above, and that can always accurately determine out-of-synchronization.

Means for Solving the Problems The out-of-sync determination method according to the present invention detects the presence or absence of a carrier based on a correlation signal between a received signal and a code sequence having a predetermined code length, and detects the presence or absence of a carrier based on a correlation signal between a received signal and a code sequence having a predetermined code length. It is characterized in that it is determined that the synchronization is out of synchronization when no carrier is detected continuously over a period of multiple times.

The out-of-synchronization determination device according to the present invention includes a carrier detection circuit that outputs a signal indicating the presence or absence of a carrier based on a correlation signal between a received signal and a code sequence having a predetermined code length, a carrier detection circuit that is reset by a signal indicating the presence of a carrier, and a carrier detection circuit that outputs a signal indicating the presence or absence of a carrier. A counter that is put into an operating state by a signal representing nothing, and counts the signals generated every cycle corresponding to the code length when it is put into the operating state, and a counter that compares the count value of the counter with a predetermined threshold value and calculates the count value. The present invention is characterized in that it includes a comparison circuit that outputs a period deviation detection signal when the period coincides with a threshold value.

The presence or absence of a carrier is detected based on a correlation signal between the active received signal and a code sequence having a predetermined code length.

It is determined that synchronization is out of synchronization when carrier absence is detected continuously over a period that is multiple times the period corresponding to the predetermined code length. Even if carrier absence is detected, unless this state continues for a predetermined number of cycles, it will not be determined that the synchronization is out of synchronization.

EXAMPLES Below, an example will be described in detail in which the present invention is applied to a C8K;a borrowing system using a Manchester code M sequence as a PN code.

(1) Overall configuration of CSK communication system FIG. 1 shows the overall configuration of a CSK type communication system using the Manchester code M sequence.

On the transmitting side, the modulation device (transmission bag 11) is provided with two Manchester M-sequence generators 31 and 32 that each synchronize and generate Manchester code M-sequences with low cross-correlation and the same code length. The code output of W31 is given to the switching circuit 33. This switching circuit 33 is controlled according to the binary transmission data (1 or 0). For example, when the transmission data is 0, the code output of the generator W31 is output, and when it is 1, the generator 32 code outputs are selected respectively.The code output signal selected by this switching circuit 33 becomes the transmission signal TKO.Switching control in the switching circuit 33 is performed in synchronization with the cycle of the Manchester code M sequence to be generated. One piece of binary data (1 or 0) is expressed by a Manchester code M sequence with -period.

This modulation method is called code shift keying (CSK) because the switching or selection of two different Manchester code M sequences is performed depending on the code (1 or O) of the data to be transmitted.

Of course, CSK is not limited to the Manchester M sequence, and other PN code sequences may be used.

The transmission signal TXO is sent out to the transmission line or transmission medium via the transmission interface 12A. As described in the "Prior Art" section, the transmission interface 12A is a connection section in a broad sense, and is a section that performs carrier modulation, mixing processing into a power line, and the like.

The reception interface 12B also demodulates 8 carriers.

It performs separation from the power line, A/D conversion, etc., and converts the signal input from the transmission path or transmission medium into a digital reception signal RXI and outputs it.

The receiving device on the receiving side includes two correlators 21.22°tU.
Adjustment device 23. Carrier detection circuit 24. Synchronous control circuit 25
etc. are included. The digital reception signal RXI output from the reception interface 12B is branched into two and input into correlators 21 and 22, respectively. One correlation 1021
A Manchester code M sequence generated from one Manchester M sequence generator 3L is set in , and the correlation between this set sequence and the received signal RXI is taken. Similarly, the other Manchester M-sequence generator 3 is connected to the other correlator 22.
2 is set, and the correlation between this set sequence and the received signal RXI is taken. The correlation outputs obtained from these correlators 21 and 22 are given to a demodulation bag 'It23, and in this demodulation device 23, a demodulation signal 1 or O is assigned according to the correlation value and outputted as received data RXD. That is, the correlator 21
If correlator 21 shows a larger correlation peak value among the correlation outputs of received data are generated respectively.

The correlation output is also input to carrier detection circuit 24 and synchronization control circuit 25. The carrier detection circuit 24 detects the presence or absence of a carrier based on the correlation output, and provides the detection signal to the synchronization control circuit 25. The presence or absence of a carrier is determined by the received signal RX.
This is used to determine whether or not I is being received. When a carrier is being detected, the synchronization control circuit 25 creates a timing signal for demodulation and carrier detection based on the correlation output, and provides it to the demodulation device 23 and the carrier detection circuit 24.

As described above, in the C8K borrowing system, two correlation outputs are compared on the receiving side, and depending on the magnitude, 0 of the received data is
Since the Manchester M sequence on the receiving side does not need to be strictly synchronized with that on the transmitting side, data demodulation errors do not occur. Furthermore, if the absolute value is taken as the output of the correlator, no error will occur even in the case of a transmission line with degraded characteristics such that the transmission peak value becomes negative. Furthermore, by using the Manchester code M sequence, it is possible to reduce the low-frequency components of the received signal and suppress the coupling loss with the transmission path.

(2) Configuration example of C5K modulation device FIG. 2 shows a specific configuration example of the C8K modulation device 11. Further, output signal waveforms of each part of this circuit are shown in FIG.

In this embodiment, each Manchester M-sequence generator 31, 32
is a three-stage (n=3) shift register FF11 to FF
FF-FF23, and these Schiff 13'
21 The register performs a data shift operation at the timing of the clock signal CK output from the clock generator 34. The feedback circuits of these shift registers are different from each other. That is, in shift register FF - FF, 3,! The codes of the cells in the J2 and 3rd stages are determined by the exclusive OR circuit (
In contrast, in the shift register FF-FF23, the codes of the first and third stage cells are fed back via the EX-OR circuit 32a. The shift register and its feedback circuit are M
Sequence generator (PN code generator, PN code-Pseude
Each of them constitutes N0IS (3 codes-pseudo noise code).

A Manchester code is created by exclusive ORing the code output of the final stage of each shift register and the clock signal CK in EX-OR circuits 37 and 38, respectively.

When one Manchester M-sequence generator 31 has a specific phase (all 1), the other Manchester M-sequence generator 32
A phase synchronization circuit is provided so that the phase always remains constant (initial phase). This phase synchronization circuit includes a NAND circuit 3B and an initial phase setter 35. The initial phase setter 35 is used to set an initial code to each stage of the shift registers FF-FF23.
(a code other than that) can be set. shift register FF
- When the codes of all stages of F F ta become 1 (this state occurs once in one period T of the Manchester code M series), an L level signal is generated from the NAND circuit 3B, and the clock signal At the next rising edge of CK, the sign set in the initial phase setter 35 is transferred to shift register FF2□
˜loaded into each stage of the FF 23.

As mentioned above, the outputs of the Manchester M sequence generators 31 and 32, that is, the outputs of the EX-OR circuits 81 and 38, are given to the switching circuit 33, and transmitted every period (data interval) T of the Manchester code M sequence by the transmission data TXD. A switching operation is performed. Further, the output of the NAND circuit 3B is given to a transmission data processing section (for example, a microprocessor) as a transmission request signal. The transmission data processing unit processes one bit of the transmission data TXD (
1 or 0) and provides it to the switching circuit 33.

FIG. 4 shows a modification. Comparing with FIG. 2, we can see that EX-
The OR circuits 37 and 38 are removed, and instead, the output of the switching circuit 33 and the clock signal C are connected to the output side of the switching circuit 33.
An EX-OR circuit 39 which receives K as an input is provided to create a Manchester code.

Reference numerals 31A and 32A each refer to an M-sequence generator, and their outputs (signs of the final stage of the shift register) are provided to a switching circuit 33, respectively. This modification has the advantage that the EX-OR circuit can be made smaller by one.

Note that the output side of the switching circuit 33 in FIG. 2 and the EX- in FIG.
It is preferable to provide a one-clock latch circuit on the output side of the OR circuit 39 to shape the waveform of the transmission signal TXO.

(3) Configuration Example of Correlator Next, the configuration of the correlators 21 and 22 will be explained in detail with reference to FIG.

The correlators 21 and 22 each have N stages of registers 41a.

41b, and these registers 41a, 41b.

Modulation device! The Manchester code M sequences generated by the Manchester M sequence generators 31 and 32 included in fll are each set in advance. The code length of the M sequence generated using an n-stage shift register is 2n-1 bits. Since the M sequence is Manchester encoded in the modulation device 11, the number of stages N of the registers 41a and 41b is N-2.
(2”-1).

On the other hand, the digital reception signal RXI input from the reception interface 12B is branched into two and input to shift registers 42a and 42b provided in each correlator 21, 22. These shift registers 42a and 42b also have N stages and are driven by a clock CK having twice the frequency of the clock signal in the modulator 'gR11.

In the correlator 21, the code of each set stage of the register 41a and the code of the received signal sent to the corresponding stage of the shift register 42a are respectively output to an EX-OR circuit 43.
Compare at a. The output signals of all EX-OR circuits 43a are given to an adder 44a and added. Adder 4
The output signal 4a represents the degree of coincidence between the code of each stage of the register 41a and the code of each corresponding stage of the shift register 42a, and this is the correlation output R of one correlator 21.
It becomes a. This is because the received signal RXI is sequentially shifted through the shift register 42a every clock signal CK.

The correlation output R also changes accordingly for each clock signal CK.

Similarly, in the other correlator 22, the register 41
The EX-OR circuit 43b checks whether the sign of each stage set in b matches the sign of the received signal sent to the corresponding stage of the shift register 42b. The output signals of all EX-OR circuits 43b are sent to the adder 4
4b and is added. The adder outputs a correlation output R1 representing the degree of correlation between the Manchester M sequence set in the register 41b and the input digital reception signal RXI.
will be output.

FIG. 6 shows a modification of the correlator 21. register 4
1a and shift register 42H, the number of stages is NXm.
(m is a positive integer of 2 or more) register 41A and shift register 42A are provided. shift register 4
2A is driven by a clock signal CK having a frequency m times that of the clock signal CK. EX-OR circuit 43
A b N

The adder 44A adds the output signals of all the EX-OR circuits 43A and outputs the result as a correlation output R. In this way, by increasing the number of stages of registers and shift registers by rn times, the accuracy of correlation calculation is improved.

It goes without saying that the correlation 'a22 can also be transformed in the same way.

FIG. 7 shows yet another embodiment. Here, the shift register 42 to which the received signal RXI is input is the correlator 21.
and 22. By doing so, the number of shift registers can be reduced and the configuration can be simplified. It goes without saying that a shift register with the number of stages multiplied by m as shown in FIG. 6 can also be used as the correlators 21 and 22 in the same way.

(4) Demodulator and carrier detection circuit FIG. 8 shows an example of the structure of the demodulator 23 and the carrier detection circuit 24. Also, the signal waveforms of each part in FIG.
As shown in the figure. In this figure, correlation outputs R, Rb
is drawn in analog form for easier understanding.

Correlation outputs R and R output from a pair of correlators 21 and 22
First, the principle of demodulating data based on b. Referring to FIG. 9, one data interval T (this is equivalent to one period of the Manchester M series) is divided into a central window part (referred to as the W part) and parts before and after it (this is referred to as the E part). Divide into The front and rear E portions are set at equal intervals.

However, it is not necessary to set the E parts before and after the W part equally (
, W portion need not be set at the center of the data section. Q<
Using d that satisfies d<T.

The W part is an area from (T-d)/2 to (T+d)/2.

Part E is the section from 0 to (T-d)/2 and from (T+d)/2 to T.

It can be expressed as The W section is also called the viewing fil1 section.

When data is being transmitted, a correlation peak appears in one of the correlation outputs R and Rb within the data interval T. In the synchronization control circuit 25, this correlation peak is detected, and a data section end signal ED is created which defines the end point of the data section so that the correlation peak is located at the center of the data section T. Then, based on this data section end signal ED, a window start pulse WL and a window stop pulse WH, which respectively define the start point and end point of the W section, are created by the synchronization control circuit 25.

The meanings of the symbols P, P, AA are as follows: aw by
aI? ' bE.

P: Peak value av of correlation output R at W part
a (maximum tn> P: peak value v (maximum value) of the correlation output Rb at the W section A - total sum of the correlation output R at the E section (addition aE'
a calculation value) A: summation (addition bl? calculation value) of the correlation output Rh in the E part Demodulated data (received data RXD) is generated as follows.

If P number A > P −A, the data is 1° by
aE ay bH P φA <P @A, then the data is 0°fJ
w aB ay bETheoretically speaking, Pb
If w〉Paw, the data is 1゜If the opposite is true, the data is 0
You may judge that. However, if noise is included, demodulation errors may occur when comparing peak values in correlation outputs. Generally, in a correlation output that has a correlation peak, the levels before and after the peak are smaller than the correlation level of a correlation output that does not have a correlation peak.

For example, if the correlation output R6 has a correlation peak, the sum AbE before and after it is smaller than the sum AaE of the correlation outputs R without a correlation peak. Utilizing this property, in order to prevent demodulation errors as much as possible, the product of the peak value and the sum of mutually separate correlation outputs, that is, P ψA and P −A
This means that the demodulated data is created by performing a large comparison with aE ay bE.

This makes it possible to perform stable demodulation even when the transmission characteristics of the transmission path are poor and noise is likely to occur.

Next, the principle of carrier detection will be explained. That is,
The absolute value of (P φA - P life A) is by
Carrier detection is performed when aE ay bE exceeds a predetermined threshold level ThP. The presence of a carrier means that a correlation peak appears on either one of the correlation outputs.

Therefore, the absolute value of the difference between the products of the peak values and the sums of the mutually separate correlation outputs exhibits a large value. On the other hand, when there is no carrier, the absolute value of the product difference is very close to zero. As a result, the presence or absence of a carrier can be determined without being affected by noise or the like, as in the case of data demodulation.

Since the circuit shown in FIG. 8 is a digital circuit, it operates in synchronization with the clock signal CK or CK, but the illustration of the clock signal is omitted to simplify the explanation.

In this circuit, the correlation output R is 1 in the latch circuit 51a.
After being latched for a clock period, the signal is converted into an absolute value by an absolute value circuit 52a, and further provided to an adder circuit 55a and a maximum value hold circuit 54a. on the other hand.

A window start φ pulse WL and a window stop pulse WH are inputted to the window generating circuit 53, and a window signal WS which becomes H level at the W portion is outputted from this circuit 53. This window No. 913 WS is applied to the latch circuit 4B of the adder circuit 55a and the latch circuit 4B of the maximum value hold circuit 54a as an operation control signal.
operates only in the E portion where the window signal WS is at L level.

The latch number timing is of course defined by the clock signal. The correlation output R converted into an absolute value, which is inputted sequentially, is added to the previous addition result provided from the latch circuit 48 for each clock signal by the adder 47, and this addition result is latched again by the latch circuit 48. In this way, data representing the total sum AaE is obtained from the adder circuit 55a and is applied to the squaring multiplier 56a.

The latch circuit 46 of the maximum value hold circuit 54a operates only in the W portion where the window signal WS is at H level. The maximum value latched in the latch circuit 46 up to the previous time and the absolute value of the correlation value R8 input this time are compared in the comparator 45, and if the current correlation value is larger, this current correlation value is used as the new correlation value. It is latched in the latch circuit 46 as the maximum value. In this way, the peak value P is output from the maximum value hold circuit 54a.
Data representing av is obtained and applied to 1 multiplier 58b.

The same goes for the other correlation output Rb.

A latch circuit 51b, an absolute value circuit 52b, a maximum value hold circuit 54b, and an adder circuit 55b are provided.

Then, the peak value P is output from the maximum value hold circuit 54b.
A total sum AbE is obtained from the adder circuit 55b, respectively, and is applied to squaring multipliers 511a and 58b.

In the multiplier 56a, the multiplication of P −A is performed by 1 multiplier
In aE 58b, multiplication of P and A is performed respectively.

ay blE The multiplication result is sent to the comparator 57 and the subtraction/absolute value circuit 59.
are given to each.

The comparator 57 compares the magnitude ratio by aU av LIB of P -A and P -A, outputs a signal representing 1 or 0 according to the comparison result, and outputs a signal representing 1 or 0 to the latch circuit 58 at the timing of the data interval end signal ED. latched to.

It is output as received data RXD. Addition circuits 55a and 55b are activated by this data section end signal ED.

Maximum value hold circuits 54a and 54b are reset.

On the other hand, in the subtraction/absolute value circuit 59, (P −Aby
The subtraction of alE P−A) and its absolute value are performed.

ay bE This calculation result is secondarily compared with a threshold Th in a comparator circuit 80, and if it is larger than Th, the carrier detection signal P is
AS is output.

(5) Configuration example of synchronous control circuit FIG. 10 shows an example of the configuration of the synchronous control circuit 25.

The synchronization control circuit 25 includes a peak position detection circuit 26A, a peak position determination circuit 26B, a synchronization establishment determination circuit 28. It includes an out-of-synchronization determination circuit 29 and the like.

The peak position detection circuit 20A is a circuit for detecting where the peak of the correlation output is located within the data interval T, and as shown in FIG. 11, the peak position PP is the point at which the maximum value of the correlation output appears. It is measured as the time from to the data section end signal ED.

In this embodiment, the peak position is the position where the absolute value of the sum of the two correlation outputs R and R6 has the maximum value.

The two correlation outputs R and R6 are each given to an adder 61, added, and then converted into an absolute value by an absolute value circuit 64.

This absolute value signal is applied to one input terminal of comparator SG2 and latch circuit 63. When the signal ED indicating the end of the previous data section is applied to the latch circuit B3 as a latch timing signal via the OR circuit 65A, the output of the absolute value circuit 64 is latched as an initial value. The value latched in the latch circuit 63 is given as another input to the comparator 82. Therefore, from then on, the latch circuit 6
3 and the output value of the absolute value circuit 84 are compared sequentially (for each clock pulse of the clock signal CK) in the comparator circuit B2, and the output value larger than the latched value is determined as the absolute value. When obtained from the circuit 64, the output of the comparison 5G2 is sent to the latch circuit 63 via the OR circuit [i5A].
, the output of the absolute value circuit G4 is latched into the latch circuit 03 as a new value. In this way, the maximum value is always latched in the latch circuit 83.

On the other hand, the counter B8 that counts the clock signal CK is
Reset (clear) by data section end signal ED input via R circuit 65B or comparison output of comparator 62
and starts counting again from zero. The count output of counter 8B is latched by latch circuit 67 when the next data period end signal ED is applied. The counter 8G counts the clock signal CK from the time when the peak value appears in the data interval T until the time when the signal ED indicating the end of the data interval T is applied. This count value is then latched by the latch circuit 67 and represents the peak position PP.

Data P representing the peak position detected in this way
P is then given to the peak position determination circuit 28B. This determination circuit 26B is operated by a W in which the detected peak position is set.
This is to determine whether it is within the department. As described above, in both demodulation processing of received data and carrier detection processing, it is necessary that the correlation peak exists in the W portion, otherwise correct demodulation processing and carrier detection processing cannot be performed.

In the peak position determination circuit 26B, the comparator 68°69
A window type digital comparator circuit is provided, which is composed of an AND circuit 70 and an AND circuit 70.

One comparator 68 contains data representing the start position of the W part, and the other comparator 69 contains data representing the stop (end) position of the W part.
Data representing the position is set respectively, and the peak position i1! AND circuit 70 only when data representing PP is between these start and stop positions.
A peak position determination signal PH of H level is output from.

Next, the configuration and operation of the synchronization establishment circuit including the synchronization establishment determination circuit 2B will be described with reference to FIG.

Two registers 72 and 73 are provided. Data representing the peak position PP is given to the register 72, and data representing (3/2)T-PP is set in this register 72. T is data representing the length (time) of the data section. On the other hand, data T is set in the register 73. The selector 74 selects one of the setting data of these registers 72 and 73 according to the state of the peak position determination signal PH, and applies it to one input of the digital comparator 75.

On the other hand, the counter 71 counts the clock signal CK and provides the count output to the other input of the digital comparator 75. Comparator 75 generates a data period end signal (match signal) ED when the count value of counter 71 becomes equal to the setting data applied through selector 74. The counter 71 is reset by this signal ED and starts counting again from zero.

Now, since the correlation output and the data section are not synchronized when the power is turned on, there may be no correlation peak in the W section. At this time, the peak position determination signal PH is L
The selector 74 selects the setting data of the register 72 and supplies it to the comparator 75. This setting data (3
/2) T-PP is.

The primary data interval end signal ED is set so that the length (time) from the next peak to the next data interval end signal is T/2.
It is intended to generate. In this way, when the peak position is located within the W section, the peak position determination signal PH becomes H level, and the selector 74
Since the setting data T of No. 3 is selected, the data section end signal ED will be generated at the period T from then on.

Synchronization is said to be established when a state in which the peak position exists within the W part of the data interval continues for a predetermined number of times X times. The counter 82 is set to a clock enable state by the H level peak position determination signal PH inputted through the AND gate 81, and counts the inputted data section end signal ED. This counter 82 outputs NO when the signal PH is at L level.
It is reset by this L level signal via a T circuit 84 and an OR circuit 85. The count output of the counter 82 is given to a digital comparator 83. On the other hand, this comparator 8
3 is set as a predetermined number of times X at which it should be determined that synchronization has been established. When the count value of the counter 82 reaches this X, a match signal is generated from the comparator 83.

Flip-flop 19 is set and synchronization establishment signal DS
R (L level) is output. The match signal from comparator 83 passes through OR circuit 85 and resets counter 82 . Further, the AND gate 81 is closed by the synchronization establishment signal DSR,
Therefore, the peak position determination signal PH is no longer input.

Note that if the peak position determination signal PH becomes L level even once while the counter 82 is counting the signals ED, the counter 82 is reset, so when the signal qPH is at the H level, X signals ED are counted. It is determined that synchronization has been established only if the input is continuous. When the signal PH becomes L level before it is determined that synchronization is established, the selector 74 selects the register 72 as described above, and the generation timing of the data section end signal ED is adjusted again.

The out-of-synchronization determination circuit 29 determines that out-of-synchronization occurs when the carrier detection signal PAS is not continuously output over a predetermined plurality (Y times) of data sections.

Referring to FIG. 13, once synchronization is established, NAND gate 91 is opened by synchronization establishment signal DSR at L level. If a carrier is detected, carrier detection signal PAS is at H level. When the carrier is no longer delivered, the carrier detection signal PAS becomes L level, and the NAND
Through gate 91.

An H-level enable signal is applied to the clock φ enable terminal CE of the counter 92. The counter 92 is activated by the NAND gate 91 in response to the H level carrier detection signal PAS.
．． It has already been reset via the NOT circuit 94 and 0R95. When the counter 92 is enabled, it counts the input data period end signal ED and provides the counted value to the digital comparator 93. Data representing a predetermined number Y is set in advance in this comparator 93. Therefore, when the count value of the counter 92 reaches Y, the comparator 9
3, a coincidence signal is generated, the flip-flop 19 is reset, and the synchronization establishment signal DSR becomes H level. This H
The NAND gate 91 is closed by the level signal DSR. Further, the counter 92 is reset by the output signal of the comparator 93 via the OR circuit 95.

When the carrier detection signal PAS becomes H level while the counter 92 is performing a counting operation, the counter 92 is reset. That is, it is determined that the synchronization is out of synchronization only when a state in which no carrier is detected continues for Y data intervals.

As a result, temporary carrier non-detection due to fluctuations in transmission characteristics of the transmission path, etc., and carrier non-detection due to 0 communication termination (
It is possible to clearly distinguish between correct and out-of-synchronization).

Effects of the Invention According to the present invention, the presence or absence of a carrier is detected based on a correlation signal between a received signal and a code sequence having a predetermined code length. It is determined that synchronization is out of synchronization when carrier absence is detected continuously over a period that is multiple times the period corresponding to the predetermined code length.

Even if carrier absence is detected, unless this state continues for a predetermined number of cycles, it will not be determined that the synchronization is out of synchronization.

In this way, it is determined that the synchronization is out of synchronization only when no carrier is detected continuously over a predetermined plurality of periods, and in other cases, it is not determined that the synchronization is out of synchronization. It becomes possible to correctly distinguish between non-detection of a carrier and non-detection of a carrier due to termination of communication, and to recognize only termination of communication.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a CSK communication system. FIG. 2 is a circuit diagram showing an example of the configuration of the modulation device, and FIG. 3 is a time chart showing its operation. FIG. 4 is a circuit diagram showing another example of the modulation device. FIG. 5 is a circuit diagram showing an example of the configuration of a pair of correlators. FIG. 6 is a circuit diagram showing a modification thereof, and FIG. 7 is a circuit diagram showing another example of the configuration of the correlator. FIG. 8 is a circuit diagram showing an example of the configuration of the demodulator, and FIG. 9 is a waveform diagram showing its operation. FIG. 10 is a circuit diagram showing a configuration example of a synchronous control circuit. FIG. 11 is a waveform diagram showing the peak position detection operation, FIG. 12 is a waveform diagram showing the synchronization establishment determination operation, and FIG. 13 is a waveform diagram showing the synchronization loss determination operation. 14 and 15 show a conventional SS communication system, FIG. 14 is a circuit diagram showing the configuration, and FIG. jfl15 is a time chart showing its operation. 24...Carrier detection circuit. 29...Out-of-synchronization determination circuit. 92...Counter. 93... Comparator. that's all

Claims (2)

[Claims] (1) When the presence or absence of a carrier is detected based on a correlation signal between a received signal and a code sequence with a predetermined code length, and no carrier is detected continuously over a period that is multiple times the period corresponding to the predetermined code length. A method for determining out-of-synchronization. (2) A carrier detection circuit that outputs a signal indicating the presence or absence of a carrier based on a correlation signal between a received signal and a code sequence having a predetermined code length, which is reset by a signal indicating the presence of a carrier and operates by a signal indicating the absence of a carrier. A counter that counts signals generated every cycle corresponding to the code length when the state is set to the operating state, and the count value of the counter is compared with a predetermined threshold value, and when the count value matches the threshold value. A comparison circuit that outputs a period deviation detection signal to a period deviation determination device.