JPH0224621U - - Google Patents

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Publication number
JPH0224621U
JPH0224621U JP10286188U JP10286188U JPH0224621U JP H0224621 U JPH0224621 U JP H0224621U JP 10286188 U JP10286188 U JP 10286188U JP 10286188 U JP10286188 U JP 10286188U JP H0224621 U JPH0224621 U JP H0224621U
Authority
JP
Japan
Prior art keywords
outputs
input signal
amplifier
control signal
automatic gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10286188U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10286188U priority Critical patent/JPH0224621U/ja
Publication of JPH0224621U publication Critical patent/JPH0224621U/ja
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例のブロツク図、第3
図a〜dは自動利得制御回路の動作を説明するた
めの波形図、第2図はFETの入力電圧VSGに
対する抵抗値RDSの相関図、第4図は従来の自
動利得制御回路の一例のブロツク図である。 1…増幅器、2…FET、3…汎用増幅器、4
…比較器、4a…基準電圧、5…可変抵抗器。
Figure 1 is a block diagram of an embodiment of the present invention;
Figures a to d are waveform diagrams for explaining the operation of the automatic gain control circuit, Figure 2 is a correlation diagram of the resistance value RDS with respect to the input voltage VSG of the FET, and Figure 4 is a block diagram of an example of a conventional automatic gain control circuit. It is a diagram. 1...Amplifier, 2...FET, 3...General-purpose amplifier, 4
... Comparator, 4a... Reference voltage, 5... Variable resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号を増幅して出力する増幅器と、この増
幅器からの出力を制御信号に応じて減衰させるF
ETと、前記入力信号とあらかじめ設定した基準
値を比較して前記制御信号を出力する比較器とを
有することを特徴とする自動利得制御回路。
An amplifier that amplifies the input signal and outputs it, and an F that attenuates the output from this amplifier according to the control signal.
An automatic gain control circuit comprising: an ET; and a comparator that compares the input signal with a preset reference value and outputs the control signal.
JP10286188U 1988-08-02 1988-08-02 Pending JPH0224621U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10286188U JPH0224621U (en) 1988-08-02 1988-08-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10286188U JPH0224621U (en) 1988-08-02 1988-08-02

Publications (1)

Publication Number Publication Date
JPH0224621U true JPH0224621U (en) 1990-02-19

Family

ID=31333161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10286188U Pending JPH0224621U (en) 1988-08-02 1988-08-02

Country Status (1)

Country Link
JP (1) JPH0224621U (en)

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