JPH02245672A - Signal processor - Google Patents

Abstract

PURPOSE:To take out an only required frequency component by selecting the waveform and the waveform width of a waveform signal which is multiplied by an input signal in an analog multiplier circuit in response to the band width and the component of the required frequency. CONSTITUTION:An input signal through an input terminal 11 is supplied to an analog multiplier circuit 13 by way of a preamplifier 12. A trigger signal through a terminal 14 is synchronized with the input signal and supplied to a pulse generator 15. Pulses whose repeating frequency is twice or more the frequency of the input signal are obtained based on a sampling theorem. The pulses are supplied to a waveform-signal generating circuit 16 having the func tion of an arbitrary-waveform-signal generating circuit. The output waveform signal from the circuit 16 is supplied to the circuit 13 and multiplied by the input signal from the amplifier 12. The multiplied output is further supplied into an integrating circuit 17. As the integrated output, a signal comprising only the frequency component determined in response to the waveform width and the waveform of the waveform signal in the input signal is obtained. Thus only the required frequency component can be taken out.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a signal processing device suitable for use in, for example, a measuring instrument to extract a necessary frequency component from a signal under measurement.

[Conventional technology]

For example, in measuring instruments such as storage scopes, sampling and holding circuits are used for sampling as preprocessing to convert signals under measurement into digital signals. As this sampling and holding circuit, a circuit as shown in FIG. 3 is generally used. That is, an input signal SA, which is a signal to be measured, passed through an input terminal 1 is supplied to a sampling gate circuit 3 via a preamplifier 2. A tri-force signal synchronized with the input signal is supplied to the pulse generation circuit 5 through the terminal 4, which generates a pulse TG whose repetition frequency is more than twice the frequency of the input signal SA according to the sampling theorem (Fig. 4A). ) is obtained. This pulse TG is supplied to the gate pulse generation circuit 6, from which a square wave pulse SC for sampling (FIG. B) synchronized with the pulse TG is obtained. This square wave pulse SC
The pulse width of the gate 1 is made variable by a pulse width variable signal supplied to the pulse generating circuit 6 through the terminal 7. This square wave pulse SC is supplied to the sampling gate circuit 3, and the signal under test SA from the preamplifier 2 is gated in its pulse width period. The gated signal is
It is integrated by the integrating capacitor of the integrating circuit 8, and the integrated output is delivered to the output terminal 9. By the way, in the sampling and hold circuit shown in FIG. 3, if the input signal is Vsinωt and the pulse width of the square wave pulse SC is τ, then the output V(t
+) is the integral value from t, -υ/2 to t1+τ/2. In other words, it becomes ω 2 . Output V. Let Yo(ω) be the maximum amplitude of (t,) for a certain frequency, then Yo(ω)=<2V/ω) sin(ωr/
2) E, sin ωτ 2 ωτ/2Vτ When ω=0, Yo (0)=RimYo (ω) =Vvω→O Therefore, each frequency response to ω=0, that is, DC (direct current), is If the above equation is represented as a graph, it will be as shown in FIG. 6. Here, the frequency that becomes -3 dB (1/no) with respect to DC, that is, the upper limit of the frequency characteristic, is ω0τ/2=2πfo
Since τ/2=πτt'0ζ0.44π, τfo L:IO,44. As is clear from the above, the frequency bandwidth up to the -3 dB drop frequency of the integrated output voltage derived at the output terminal 9, that is, the frequency bandwidth of the sampling and hold circuit, is determined by the pulse width of the square wave pulse SC. It is something.

[Problem to be solved by the invention]

As mentioned above, the sampling and hold circuit in Fig. 3 is
By changing the pulse width of the sampling square wave pulse, the frequency bandwidth of the sampling and holding circuit can be changed. However, since the sampling gate circuit is only gated on and off using square wave pulses, it is not possible to extract only the necessary frequency components of the input signal. When only the frequency f1 of the input signal having the component is required, the conventional sampling and holding circuit shown in FIG. 3 changes the pulse width of the square wave pulse SC to include the frequency f1. However, as described above, the conventional sampling and holding circuit has frequency characteristics as shown in FIG. 7B, so that the frequency f2 component of the input signal is also included. Therefore, conventionally, when performing frequency analysis by performing FFT (Fast Fourier Transform), it is not necessary to perform processing such as removing unnecessary frequency components. In view of the above points, this invention combines a sampling hold circuit and a filter circuit that extracts only necessary frequency components! ! The purpose of the present invention is to provide a signal processing device that has the following functions.

[Means to solve the problem]

The signal processing device according to the present invention prompts signal generation by a trigger signal that is synchronized with an input signal, has a repetition frequency that is more than twice that of the input signal, and is responsive to the frequency component that is desired to be extracted from the input signal. a waveform signal generation circuit that generates a signal with a variable waveform and waveform width; an analog multiplication circuit that multiplies the input signal by the signal from the waveform signal generation circuit; and an analog multiplication circuit that integrates the output of the analog multiplication circuit. It consists of an integrating circuit.

[Operation] The signal from the waveform signal generation circuit and the input signal are multiplied by the analog multiplication circuit, and the multiplication output is integrated by the integration circuit. As an output of the integrating circuit, a required frequency component in the input signal is obtained according to the waveform and waveform width of the signal from the waveform signal generating circuit.

【Example】

FIG. 1 is a block diagram of an embodiment of a signal processing device according to the present invention, in which an input signal SA through an input terminal 11 is supplied to an analog multiplier circuit 13 via a preamplifier 12. Further, a trigger signal not synchronized with the input signal is supplied to the pulse generation circuit 15 through the terminal 14, and from this, a pulse TG (pulse TG) whose repetition frequency is in accordance with the sampling theorem twice or more than the frequency of the input signal SA is supplied. Figure 2A) is obtained. This pulse TG is supplied to the waveform signal generation port 111816. This waveform signal generation circuit 16 has the function of an arbitrary waveform generation circuit, and in this example, a microcomputer 21 that calculates and generates waveform data of an arbitrary waveform and waveform width according to the operator's request (such as key manual input).
A multiplication circuit 1i! is made up of a RAM 22 into which the waveform data generated by the microcomputer 21 is written, an address generation counter 23 that generates an address for this RAM 22, and, for example, a PLL circuit that generates a clock for this counter 23. 824, a D/A conversion circuit 25, and a low-pass filter 26. In this case, waveform data consisting of 1024 (10 bits) samples is written into the RAM 22, where one sample is 10 bits, for example. The address generation counter 23 is a 10-pin counter. The pulse TG from the pulse generation circuit 15 is transmitted to the multiplier circuit 24.
The pulse TG is multiplied by 1024 times by 1t.
A clock CK (FIG. 2B) obtained by one cycle is obtained. This clock CK is supplied to the clock terminal of the address generation counter 23, and the counter 23 counts this clock CK and sequentially increments the count value. The count value of the at1/s generation counter 23 sequentially repeats 0 to 1023 in response to the pulse T G 4. The RAM 22 is addressed by the 10-bit count value information from the address generation counter 23, and waveform data is repeatedly read out in synchronization with the pulse TG. The waveform data read from the RAM 22 is D/A converted by a D/A conversion circuit 25 to an analog signal (C in the figure), and this analog signal is supplied to a low-pass filter 26. An output waveform signal SM (D in the figure) is obtained from this low-pass filter 26. The output waveform signal SM from this waveform signal generation circuit 16 is
It is supplied to an analog multiplier circuit 13 and multiplied by the input signal SA from the preamplifier 12. Then, the multiplication output is supplied to the integrating circuit 17 and integrated, and a signal consisting only of frequency components determined according to the waveform width and waveform of the waveform signal SM of the input signal SA is obtained as the integrated output. Its integral output is led out to output terminal 18. In this case, the waveform width (corresponding to the pulse width) of the signal SM from the waveform signal generation circuit 16 determines the frequency bandwidth up to the -3 dB drop frequency of the input signal. Then, the frequency component to be extracted is determined based on the waveform (for example, see literature: ``Easy Fourier Transform'' (for digital/analog signal processing) published by Morikita Publishing Co., Ltd., written by Hiroshi Matsuzuke). The waveform and waveform width W (see second diagram) of the output waveform signal MP are selected by the operator according to the required frequency component of the input signal SA. For example, as mentioned above, in Fig. 7, the frequency is 1
When not extracting only the component, a Gaussian curve waveform as shown in the second diagram is used, and the waveform width tw is
The signal is returned according to the frequency f1. Then, the frequency characteristic of the integrated output voltage becomes as shown in FIG. 7C, and the unnecessary frequency f2 component is not included in the output, and only the necessary frequency f is obtained. Note that various waveforms such as a triangular wave are used as the waveform of the waveform signal SM depending on the frequency component desired to be obtained as an output signal.

【Effect of the invention】

In this invention, by selecting the waveform and waveform width of the waveform signal to be multiplied by the input signal and the analog multiplication circuit according to the required frequency bandwidth and frequency components,
Only the desired frequency component in the input signal can be obtained3 For example, if only the frequency component of the input signal shown in FIG. , the waveform width may be set according to the frequency. Therefore, according to the signal processing circuit according to the present invention, it is possible to obtain the effect that processing such as removing unnecessary frequencies in the t& stage circuit, as in the conventional sampling and holding circuit, is not necessary.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a positional embodiment of a signal processing circuit according to the present invention, FIG. 2 is a time chart for explaining the same, FIG. 3 is a diagram showing an example of a sampling and holding circuit, and FIG. , a time chart for explaining the example in Figure 3,
5 is a diagram for explaining the integral operation of the circuit of FIG. 3, FIG. 6 is a diagram showing the frequency characteristics of the output signal of the circuit of FIG. 3, and FIG. 7 is a diagram showing the circuit of FIG. 3 and the signal according to the present invention. FIG. 2 is a diagram for explaining the effects of an example of a processing circuit. 13; Analog multiplication circuit 15; Pulse generation circuit 16; Waveform signal generation circuit 17; Integration circuit Agent Patent attorney Masami Sato A (TG) Daiminf'° chart Figure 2 Signal study training 1 Figure 1 Serve link Figure 3: The timing is like Figure 4. Figure 6: Machida Ward, where the number of people closing down is at the bottom.

Claims (1)

[Claims] The signal is generated by a trigger signal synchronized with the input signal, has a repetition frequency that is twice or more that of the input signal, and is variable depending on the frequency component to be extracted from the input signal. a waveform signal generation circuit that generates a signal with a waveform and waveform width; an analog multiplication circuit that multiplies the input signal by the signal from the waveform signal generation circuit; and an integration circuit that integrates the output of the analog multiplication circuit. A signal processing device consisting of.