JPH02244771A - Inp series compound semiconductor - Google Patents
Inp series compound semiconductorInfo
- Publication number
- JPH02244771A JPH02244771A JP1066712A JP6671289A JPH02244771A JP H02244771 A JPH02244771 A JP H02244771A JP 1066712 A JP1066712 A JP 1066712A JP 6671289 A JP6671289 A JP 6671289A JP H02244771 A JPH02244771 A JP H02244771A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- light
- inp
- carrier concentration
- compound semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 150000001875 compounds Chemical class 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000013078 crystal Substances 0.000 claims description 21
- 230000031700 light absorption Effects 0.000 abstract description 8
- 230000035945 sensitivity Effects 0.000 abstract description 8
- 238000006073 displacement reaction Methods 0.000 abstract 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000002834 transmittance Methods 0.000 description 8
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000000155 melt Substances 0.000 description 4
- 229910052717 sulfur Inorganic materials 0.000 description 4
- 239000011593 sulfur Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 241000132500 Dahlia <angiosperm> Species 0.000 description 1
- 235000012040 Dahlia pinnata Nutrition 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000012050 conventional carrier Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Led Devices (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は、光がＩｎＰ単結晶基板中を通過して受光ま
たは発光等がなされるＩｎＰ系化合物半導体装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an InP-based compound semiconductor device in which light passes through an InP single crystal substrate to receive or emit light.
［従来の技術］
光がＩｎＰ単結晶基板中を通過して受光するＩｎＰ系化
合物半導体装置としては、第１図に示すようなＰＩＮフ
ォトダイオードがある。第１図を参照して、ｎ−ＩｎＰ
基板１の上にはｎ−１ｎＧａＡｓ層２が形成されている
。ｎ−１ｎＧａＡｓ層２の中央部分には、ｐ−１ｎＧａ
Ａｓ層３が形成されており、この上にはｐ電極５が形成
されている。ｐ電極５の周囲にはパッシベーション４が
設けられている。ｎ−ＩｎＰ基板１の反対側の面には反
射防止膜６が設けられている。反射防止膜６の周囲には
ｎ電極７が設けられている。[Prior Art] As an InP-based compound semiconductor device in which light passes through an InP single crystal substrate and is received, there is a PIN photodiode as shown in FIG. Referring to FIG. 1, n-InP
An n-1n GaAs layer 2 is formed on the substrate 1. In the central part of the n-1nGaAs layer 2, p-1nGa
An As layer 3 is formed, and a p-electrode 5 is formed thereon. A passivation 4 is provided around the p-electrode 5. An antireflection film 6 is provided on the opposite surface of the n-InP substrate 1. An n-electrode 7 is provided around the anti-reflection film 6.
第１図に示すＰＩＮフォトダイオードは、裏面入射タイ
プのものであり、反射防止膜６が設けられている側から
光が入射し、ｎ−ＩｎＰ基板１中を通過した光が受光さ
れる。通常、ｎ−ＩｎＰ基板１には、転位を少なくする
ため硫黄がドープされており、キャリア濃度は５Ｘ１０
” ｃｍ−’以上である。The PIN photodiode shown in FIG. 1 is of a back-illuminated type, and light enters from the side where the antireflection film 6 is provided, and the light that passes through the n-InP substrate 1 is received. Normally, the n-InP substrate 1 is doped with sulfur to reduce dislocations, and the carrier concentration is 5×10
”cm-' or more.
〔発明が解決しようとする課題］
このような光が基板中を通過するタイプのＩｎＰ系化合
物半導体装置においては、受光感度や発光効率などを向
上させるため、基板による光の吸収ができるだけ少ない
ことが望ましい。このような光吸収を向上させるための
方法の１つとして、基板の厚みを薄くすることが考えら
れるが、基板を薄くすると、ウェハの加工工程において
基板が割れたり欠けたりする頻度が高まり、歩留りの低
下をもたらす。通常、基板の厚みは、少なくとも３００
μｍ以上であることが望ましい。[Problems to be Solved by the Invention] In this type of InP-based compound semiconductor device in which light passes through the substrate, in order to improve the light receiving sensitivity and luminous efficiency, it is necessary to minimize the absorption of light by the substrate. desirable. One way to improve such light absorption is to reduce the thickness of the substrate, but thinning the substrate increases the frequency of cracking or chipping of the substrate during the wafer processing process, which reduces yield. resulting in a decrease in Typically, the substrate thickness is at least 300 mm
It is desirable that the thickness is μm or more.
この発明の目的は、基板の厚みを薄くすることなく、基
板の光透過率を向上させたＩｎＰ系化合物半導体装置を
提供することにある。An object of the present invention is to provide an InP-based compound semiconductor device in which the light transmittance of the substrate is improved without reducing the thickness of the substrate.
［課題を解決するための手段および作用］この発明のＩ
ｒｎＰ系化合物半導体装置では、ＩｎＰ単結晶基板のキ
ャリア濃度がｌＸｌ０”〜３Ｘ１０” ｃｍ−”であり
、かつ該基板が無転位であることを特徴としている。[Means and effects for solving the problem] I of this invention
The rnP compound semiconductor device is characterized in that the carrier concentration of the InP single crystal substrate is 1X10'' to 3X10''cm-'' and that the substrate is dislocation-free.
第２図は、ＩｎＰ基板中のキャリア濃度と光透過率との
関係を示す図である。第２図に示されるように、キャリ
ア濃度が低下するにつれて、基板の光透過率が増加する
。この発明において、キャリア濃度を３Ｘ１０” ｃｒ
ｒＶ ’以下としているのは、高い光透過率を確保し、
基板内における光の吸収をできるだけ少なくするためで
ある。FIG. 2 is a diagram showing the relationship between carrier concentration and light transmittance in an InP substrate. As shown in FIG. 2, as the carrier concentration decreases, the light transmittance of the substrate increases. In this invention, the carrier concentration is set to 3×10” cr
The reason why it is below rV' is to ensure high light transmittance,
This is to minimize absorption of light within the substrate.
また、この発明において、キャリア濃度をＩ×１０１７
以上としているのは、キャリア濃度が低下すると、一般
に動作時の電気抵抗が上昇する傾向があるので、通常の
光通信に使用する周波数帯域に応答するためには、ｌＸ
ｌ０” ｃｍ−”以上のキャリア濃度が必要だからであ
る。In addition, in this invention, the carrier concentration is I×1017
The reason for the above is that when the carrier concentration decreases, the electrical resistance during operation generally tends to increase, so in order to respond to the frequency band used for normal optical communication,
This is because a carrier concentration of 10"cm-" or more is required.
この発明においてはキャリア濃度を１． Ｘ １０ ’
７〜３Ｘ１０” ｃｍ−’としており、従来一般に用い
られているＩｎＰ基板中のキャリア濃度５ＸＩＯ” ａ
ｍ−’ ”以上よりも小さな値となっている。このため
、第２図に示されるように、この発明に従えば基板の光
透過率を増大させ、基板における光吸収を少なくするこ
とができる。In this invention, the carrier concentration is set to 1. X 10'
7 to 3X10"cm-', and the carrier concentration in the conventionally commonly used InP substrate is 5XIO" a
Therefore, as shown in FIG. 2, according to the present invention, the light transmittance of the substrate can be increased and the light absorption in the substrate can be reduced. .
しかしながら、単にキャリア濃度を低下させるために硫
黄のドープ量を減少させた場合、基板に多数の結晶欠陥
が生じ、この結果暗電流が大きくなり、デバイス特性が
低下する。However, if the amount of sulfur doped is reduced simply to lower the carrier concentration, a large number of crystal defects will occur in the substrate, resulting in an increase in dark current and deterioration in device characteristics.
この発明は、このようなデバイス特性の低下を抑制する
ため、ＩｎＰ単結晶基板として上記範囲のキャリア濃度
になるよう硫黄のドープ量を低下させても、なおかつ無
転位である基板を使用している。In order to suppress such deterioration of device characteristics, the present invention uses an InP single crystal substrate that is free of dislocations even if the amount of sulfur doped is reduced so that the carrier concentration falls within the above range. .
ここで、無転位とは、スリップ（線状欠陥）がなく、Ｅ
ＰＤ （エッチ・ビット番デンシティ：結晶欠陥密度）
が５００個／ ｅ ｍ ２以下であることをいう。スリ
ップについては、たとえばＪ、Ａｐｐｉ、Ｐｈｙｓ、５
４ （２）、Ｆｅｂｒｕａｒｙ１９８３、ｐ６６６〜６
７２に詳細な説明がなされている。ＥＰＤは、フーバエ
ッチ観察により測定される結晶欠陥の密度である。Here, dislocation-free means that there is no slip (linear defect) and E
PD (etch bit number density: crystal defect density)
is 500 pieces/em2 or less. For slips, see e.g. J, Appi, Phys, 5
4 (2), February 1983, p666-6
A detailed explanation is given in 72. EPD is the density of crystal defects measured by Huber etch observation.
このように硫黄のドープ量を減少させても、なおかつ無
転位状態であるようなＩｎＰ基板は１．たとえばＶＣＺ
（Ｖａｐｏｒ ＰｒｅｓｓｕｒｅＣｏｎｔｒｏｌ
Ｃｚｏｃｈｒａｌｓｈｋｉ）法などにより得られるイ
ンゴットをスライスして得ることができる。このＶＣＺ
法は、たとえばｍ−Ｖ族化合物半導体単結晶を製造させ
る場合、Ｖ族元素の蒸気圧中で結晶成長させる液体封止
チョクラルスキー法である。このＶＣＺ法については、
１ｒｉｓｔ、Ｐｈｙｓ、Ｃｏｎｆ、Ｓｅｒ、Ｎｏ、９１
：ｃｈａｐｔｅｒ ５に詳細な説明がなされている。Even if the amount of sulfur doped is reduced in this way, an InP substrate that is still in a dislocation-free state is 1. For example, VCZ
(Vapor Pressure Control
It can be obtained by slicing an ingot obtained by the Czochralshki method or the like. This VCZ
For example, when producing an m-V group compound semiconductor single crystal, the method is a liquid-sealed Czochralski method in which crystal growth is performed under the vapor pressure of a V group element. Regarding this VCZ method,
1list,Phys,Conf,Ser,No,91
:Chapter 5 provides a detailed explanation.
また、ＶＧＦ （Ｖｅｒｔｉｃａｌ Ｇｒａｄｔｅｎ
ｔ Ｆｒｅｅｚｅ）法により得られる単結晶も無転位
であるので、これを利用することもできる。この方法は
、原料として既に合成された化合物半導体多結晶を用い
、これをるつぼに入れて溶融させた後、融液をるつぼ下
端に配置した種子結晶と接触させて種子っけを行ない、
融液に垂直な方向の温度勾配をつけた状態で下端より徐
々に冷却して上方に向かって化合物半導体単結晶を成長
させていく方法である。このＶＧＦ法については、Ｊ、
Ｅｌｅｅｔｒｏｃｈｅｍ、Ｓｏｃ、５ｏｌｉｄ−８ｔａ
ｔｅ ５ＣＩＥＮＣＥ ＡＮＤ ＴＥＣＨＮＯＬ
ＯＧＹ、 Ｆ ｅ ｂ ｒ ｕ ａ ｒ ｙ １９
８８、特開昭６３−８５０８２号公報および特開昭６３
２７４６８４号公報などに説明がなされている。In addition, VGF (Vertical Gradten
Since the single crystal obtained by the t Freeze method is also dislocation-free, it can also be used. This method uses a compound semiconductor polycrystal that has already been synthesized as a raw material, puts it in a crucible and melts it, and then seeds the melt by bringing it into contact with a seed crystal placed at the lower end of the crucible.
In this method, a compound semiconductor single crystal is grown upward by gradually cooling the melt from the bottom with a temperature gradient perpendicular to the melt. Regarding this VGF method, see J.
Eleetrochem, Soc, 5olid-8ta
te 5CIENCE AND TECHNOL
OGY, F e b r u a r y 19
88, JP-A-63-85082 and JP-A-63
This is explained in JP-A No. 274684 and the like.
この発明に従えば、従来のＩｎＰ単結晶基板よりもキャ
リア濃度が低いため、高い光透過率を得ることができ、
基板による光吸収を少なくして受光感度や発光効率等を
向上させることができる。According to this invention, since the carrier concentration is lower than that of a conventional InP single crystal substrate, high light transmittance can be obtained.
By reducing light absorption by the substrate, light receiving sensitivity, light emitting efficiency, etc. can be improved.
また、基板が無転位であるため、暗電流が高くなってデ
バイス特性を低下させることもない。Furthermore, since the substrate is dislocation-free, dark current does not increase and device characteristics do not deteriorate.
［実施例］
ＶＣＺ法によりＩｎＰ単結晶インゴットを製造し、これ
をスライスしてｎ＋型ＩｎＰ単結晶基板を得た。面指数
は（１００）２°オフであり、キャリア濃度は２Ｘ１０
” ｃｒｒｖ ”であった。また基板の厚みは３５０μ
ｍであった。スリップはなく、転位密度（ＥＰＤ）は５
００個／ｃｍ−２以下であった。[Example] An InP single crystal ingot was manufactured by the VCZ method and sliced to obtain an n+ type InP single crystal substrate. The plane index is (100)2°off and the carrier concentration is 2X10
It was "crrv". Also, the thickness of the board is 350μ
It was m. No slip, dislocation density (EPD) is 5
00 pieces/cm-2 or less.
この基板の上に、気相成長法で、ｎ−型１ｎＧａＡｓ光
吸収層３を形成した。このエピタキシャル成長層の厚み
は約６ Ｉｔ ｍであり、キャリア濃度は約３Ｘ１０”
ｃｍ−’であった。On this substrate, an n-type 1nGaAs light absorption layer 3 was formed by vapor phase growth. The thickness of this epitaxially grown layer is about 6 It m, and the carrier concentration is about 3 x 10"
cm-'.
以上のようにして得られたウェハを用い、第１図に示す
ような裏面入射型のＰＩＮフォトダイオド受光素子を作
製し、受光感度を評価した。その結果、受光感度は、従
来のキャリア濃度が５×１０” ｃｍ−’以上のＩｎＰ
単結晶基板を用いたフォトダイオード受光素子よりも向
上することが確認された。Using the wafer obtained as described above, a back-illuminated PIN photodiode light-receiving element as shown in FIG. 1 was manufactured, and its light-receiving sensitivity was evaluated. As a result, the light-receiving sensitivity is lower than that of InP with a conventional carrier concentration of 5 x 10"cm-' or more.
It was confirmed that this device is improved compared to a photodiode light-receiving element using a single-crystal substrate.
以上の実施例では、この発明のＩｎＰ系化合物半導体装
置として、受光素子であるＰＩＮフォトダイオードを例
にして説明したが、この発明の化合物半導体装置はこの
ようなものに限定されることはなく、たとえば面発光Ｌ
ＥＤ等のような発光素子にも適用されるものである。こ
の場合、基板が無転位であるので、素子の寿命や信頼性
を低下させることなく、発光効率を向上させることがで
きる。In the above embodiments, the InP-based compound semiconductor device of the present invention was explained using a PIN photodiode as a light receiving element, but the compound semiconductor device of the present invention is not limited to such a device. For example, surface emitting L
It is also applicable to light emitting elements such as EDs. In this case, since the substrate is dislocation-free, the light emitting efficiency can be improved without reducing the lifetime or reliability of the device.
［発明の効果］
以上説明したように、この発明のＩｎＰ系化合物半導体
装置は、キャリア濃度がｌＸｌ０”〜３Ｘ１０” ｃｍ
−’であるので、従来よりもキャリア濃度が低く、基板
の光透過率を増大し、基板による光吸収を少なくして、
半導体装置の受光感度や発光効率等を向上させることが
できる。[Effects of the Invention] As explained above, the InP-based compound semiconductor device of the present invention has a carrier concentration of 1X10" to 3X10" cm.
-', the carrier concentration is lower than before, increasing the light transmittance of the substrate and reducing light absorption by the substrate.
The light receiving sensitivity, light emitting efficiency, etc. of a semiconductor device can be improved.
またＩｎＰ単結晶基板が無転位であるので、暗電流等の
特性を低下させることなく、受光感度等の向上を図るこ
とができる。Furthermore, since the InP single crystal substrate is dislocation-free, it is possible to improve light-receiving sensitivity and the like without deteriorating characteristics such as dark current.
【図面の簡単な説明】
第１図は、ＰＩＮフォトダイオードの構造を示す断面図
である。第２図は、ＩｎＰ基板中のキャリア濃度と光透
過率との関係を示す図である。
図において、１はｎ−ＩｎＰ基板、２はｎ−１ｎＧ ａ
Ａ ｓ層、３はｐ−１ｎＧａＡｓ層、４はパッシベー
ション、５はｐ電極、６は反射防止膜、７はｎ電極を示
す。
第１図
第２図
（ほか２名）−−１
★ダリア；９ （ｃ−ｎ−リBRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing the structure of a PIN photodiode. FIG. 2 is a diagram showing the relationship between carrier concentration and light transmittance in an InP substrate. In the figure, 1 is an n-InP substrate, 2 is an n-1nGa
3 is a p-1nGaAs layer, 4 is passivation, 5 is a p-electrode, 6 is an antireflection film, and 7 is an n-electrode. Figure 1 Figure 2 (and 2 others) --1 ★Dahlia; 9 (c-n-ri)
Claims (2)
物半導体装置において、 前記ＩｎＰ単結晶基板のキャリア濃度が、１×１０＾１
＾７〜３×１０＾１＾８ｃｍ＾−＾３であり、かつ該基
板が無転位であることを特徴とする、ＩｎＰ系化合物半
導体装置。(1) In an InP-based compound semiconductor device in which light passes through an InP single crystal substrate, the carrier concentration of the InP single crystal substrate is 1×10^1
An InP-based compound semiconductor device, characterized in that the substrate has a thickness of ^7 to 3 x 10^1^8 cm^-^3 and is dislocation-free.
れた基板であることを特徴とする、請求項１記載のＩｎ
Ｐ系化合物半導体装置。(2) The InP single crystal substrate according to claim 1, wherein the InP single crystal substrate is a substrate manufactured by a VCZ method.
P-based compound semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6671289A JP2705016B2 (en) | 1989-03-17 | 1989-03-17 | InP-based compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6671289A JP2705016B2 (en) | 1989-03-17 | 1989-03-17 | InP-based compound semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02244771A true JPH02244771A (en) | 1990-09-28 |
| JP2705016B2 JP2705016B2 (en) | 1998-01-26 |
Family
ID=13323804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6671289A Expired - Lifetime JP2705016B2 (en) | 1989-03-17 | 1989-03-17 | InP-based compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2705016B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015079763A1 (en) * | 2013-11-27 | 2015-06-04 | 住友電気工業株式会社 | Light receiving element |
-
1989
- 1989-03-17 JP JP6671289A patent/JP2705016B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015079763A1 (en) * | 2013-11-27 | 2015-06-04 | 住友電気工業株式会社 | Light receiving element |
| JPWO2015079763A1 (en) * | 2013-11-27 | 2017-03-16 | 住友電気工業株式会社 | Light receiving element |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2705016B2 (en) | 1998-01-26 |
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