JPH02244489A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To reduce the current consumption and to execute the operation at a high speed by converting a bit line load circuit to low impedance for a prescribed period after a line selection line is varied from an active state to an inactive state. CONSTITUTION:When an address signal is varied, an address input variation detecting circuit 40 generates a pulse signal phi, and a clock generator 90 which receives this signal generates a signal phiWL for activating a line selection line WL. An activation period gammaWL of phiWL is set to the time required for reading out data to a bit line BL from a memory cell 70, and it falls after the necessary time elapses, and brings the line selection line WL to non-activation. Simultaneously, a low impedance converting signal phiEQ of a bit line load circuit 60 rises. Subsequently, the low impedance signal phiEQ does not continue a low impedance state until the next address signal is varied, and brought to non-activation after the time gammaEQ required for equalizing the bit line BL elapses. In such a way, the current consumption of the memory cell part is reduced, and the operation can be executed at a high speed.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor memory circuit, and aims to reduce current consumption in a memory cell portion and improve operating speed at the same time. In a semiconductor memory circuit in which a row selection line is activated for the time required for a read or write operation, a bit line load circuit is made to have a low impedance for a predetermined period after the row selection line changes from an active state to an inactive state. Configure it as follows.

[Industrial application field]

The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit using a method of activating a row selection line for the time required for reading or writing in response to a reading or writing command.

[Conventional technology]

The semiconductor memory circuit according to the present invention can be used in general semiconductor memory circuits using the above-described method, but since there are many common technologies, a conventional example will be described here, taking the famous static RAM as an example.

FIG. 4 shows the basic prior art 1 of a semiconductor memory circuit, which is composed of an address buffer IO, a decoder (word line selection) 20, and a self 0, and in a bit line load circuit 60, each bit line BL, Load transistors 61 and 62 are connected to supply charge to BL. Although only one column of memory cells is shown in FIG. 4, in reality, multiple columns are arranged to form a matrix.
A bit line selection circuit is usually mounted on a chip to select a desired column, but is not shown. In the operation of such a semiconductor memory circuit, as shown in FIG. 5, a word line WLk is selected by a change in an address signal, and a corresponding cell is selected.

In self 0-k on word line WLk,
Now, if the transistor 72 side is H and the transistor 71 side is H, L information is output to the BLi side and H information is output to the TT''i side.This is the read data of the previous cycle. A new word line WLj rises.At this time, the bit line moves at the point where the previous word line WLk falls and the transistor in the memory cell turns off, so the bit BLL is switched off from the power supply level by the transistors 61 and 62. However, the bit line W remains fixed at a potential lowered by VtN of transistor 62.

In the meantime, a new word line WLj is selected and Bl
″- is the beginning of the BL, and the data of the anus is reversed.

Therefore, in this semiconductor memory circuit, there is a time delay in data inversion as shown in FIG. flows, so in order to keep this current consumption low, it is necessary to set the dimension to a certain degree.

In other words, since the conductance (gm) cannot be increased and the shape is constricted, it takes time for the BL, which was previously L, to rise to H, resulting in a slow speed.

In order to improve the drawbacks of such basic semiconductor memory circuits, a semiconductor memory circuit (prior art example 2) shown in FIG. 6 has been proposed.

FIG. 6 is an example of a conventional semiconductor memory circuit using an address input change detection circuit (hereinafter abbreviated as 470 circuit). For ATD circuits, see U.S. Patent No. 4,099.
, No. 265, No. 4.355.377, etc., so a detailed explanation will be omitted, but when a new row is selected, the level based on the successive data of the previous cycle remaining on the bit line is determined. , ATD pulse signal is used for resetting to speed up the memory read operation, and it has been widely used in recent years.

The memory shown in FIG.
, a decoder circuit 20, a word line drive circuit 30, an ATD circuit 40, a clock generator 50, a bit line load circuit 60, and a memory self 0. 7th
The figure shows the operation timing of the semiconductor memory circuit of FIG. 5. An outline of the operation will be explained below.

Address input signal aO applied to address input terminal
Based on ai, the address buffer circuit receives the in-phase signal A
0 to A, and reverse phase signals A and -A.

occurs. The decoder circuit receives these complementary signals and generates output signals X, .about.X, so as to select a desired row from memory rows 0 to m. Memory row selection lines WL, ~WL, usually have a fairly large capacitive load, and to drive this, it is common to place a word line drive circuit between the decoder output and the row selection line. It is.

On the other hand, the address complementary signal described above is input to the ATD circuit 40. When the ATD circuit 40 detects a change in the address input level, it outputs a pulse signal φ. The clock generator 50 generates a bit line equalizing clock signal φ, based on this pulse. Create. This clock signal φ,. is supplied to the bit line load circuit 60 and used to equalize the levels of the complementary bit lines prior to successive new rows.

Furthermore, the bit line load circuit 60 in this conventional example includes a transistor 20 between the bit lines BL and BL, as shown in FIG.
65 is inserted and its gate receives a bit line equalizing clock signal φ. It has a structure connected to. In some cases, in addition to the above configuration, a configuration is adopted in which transistors 63 and 64 are connected in parallel with the transistors 61 and 62 in the conventional example described above, and the gates of each are connected to the gate of the transistor 65. Sometimes I do.

That is, in the conventional example described above, complementary signals on the bit line are equalized only by transistors 61 and 62 of the bit line load circuit, whereas in this example, the previous word line is equalized by transistors 63 to 65, which will be described later. It is configured so that it is forced to equalize quickly until it comes. In reality, as the address changes as shown in FIG. 7, the previously selected word line falls down, and as it does, a new word line is selected and rises up, but in the middle is φ. The timing is set so that it occurs.

This makes the transistor T65 conductive to short-circuit the selected bit lines BL, that is, to equalize them.

Also, as mentioned above, φ. . When the transistors 63 and 64, which are activated in the same way by ing.

In this conventional example, the clock signal φ,. The pulse width τ,
. is set to such an extent that the bit lines can be sufficiently equalized within that time. To briefly describe the operation of such a semiconductor memory circuit, the state of the selected bit lines BL and BL before a new address signal is input is as described above, and the read level difference between BL and BL is canceled. When φo0 rises, the transistor 63 supplies current to the BL line on the L side, and the transistor 65 supplies current from the BL line on the H side to the BL line on the L side, thereby increasing the BL line on the L side. You can go up faster.

Here, the transistors 63 to 65 operate only when the address signal changes, and are called an AC load as opposed to a C load as described above.

In other words, since the transistors 63 to 65 are activated only when it is desired to cancel the level difference between the bit lines, they are not limited in terms of power, and therefore transistors with relatively large capacitance can be used. In other words, since transistors with large conductance (gm) can be used, changes in the levels of the bit lines BL and BL can be made faster.

However, such semiconductor memory circuits also have the following problems.

First, in this type of semiconductor memory circuit, the row selection line WL, which consumes a large amount of power in the memory cell portion, is activated, for example, in FIG.
−〇 is selected. Furthermore, the data stored in this cell is at H level (that is, the connection point between transistor 71 and transistor 73 is at H level, and the connection point between transistor 71 and transistor 73 is at H level,
At this time, a steady current flows from transistor 62 in the bit line load circuit to transistors 72 and 74 in the memory cell.

When the stored data in the cell is at L level (that is, the connection point between transistors 71 and 73 is at L level, and the connection point between transistors 72 and 74 is at H level), data is transferred from transistor 61 in the bit line load circuit to the memory cell. A steady current flows through the transistors 71 and 73 inside. This steady state current is 10
Although it is about 0 μ8, it cannot be ignored because the chip as a whole is consumed by the number of columns.

Second, in this type of semiconductor memory circuit, the row selection line W
L operates according to the address input from the outside in terms of timing, and as shown in Figure 7, the W selected in the new cycle starts from the falling edge of WL selected in the previous cycle.
There is almost no time margin between the falling edge of L. Therefore, the bit line equalize signal φ,. is generated at a timing that overlaps with the rising edge of WL selected in the new cycle. On the other hand, in order to effectively equalize the bit lines, the bit line load circuit
As shown in the figure, the equalizing transistor 65 activated by φE0 and φ, as well.

The precharging transistor 63 is activated by
, 64, the transistors 63, 64 have a limited time τ,. Since it is necessary to precharge the focus line within the bit line DC load transistors 61 and 62, the bit line DC load transistors are usually configured with transistors having a higher conductance value than the bit line DC load transistors 61 and 62.

Therefore, as mentioned above, WL and φ. In the case that the AC through current between the load circuit and the memory cell (i.e., the current passing through transistors 63 to 71 to 73, or the current flowing through transistor 6
4 to 72 to 74) is a major problem.

That is, as shown in FIG. 7, the current Ice is a composite of a part that constantly flows and a part that forms a peak value.

Thirdly, the above WL and φ. The overlap also has the disadvantage of slowing down the speed at which data is read from the memory cells to the bit lines. That is, even if WL is selected and data starts to be output from the memory cell to the bit line, the load transistors 63 and 64 having a high gm value are connected to the bit line at this time, so the memory cell cannot pull down this bit line at high speed, and valid data actually appears on the bit line only when φ. It will be after the fall.

As a method for further improving the conventional example, a semiconductor memory circuit (prior art example 3) shown in FIG. 8 has been proposed.

That is, this conventional example employs a pulsed word line method, and uses the signal φ used in the conventional example described above to determine the time T required to output cells one after another. , only the word line is opened.

FIG. 8 shows an example of an improved memory of the conventional example of FIG. 6 using an ATD circuit. In FIG. 8, the same circuit parts as in FIG. 6 are given the same numbers.

The differences between the memory in FIG. 8 and the memory in FIG. 6 are as follows. That is, in the example of FIG. 6, the ATD pulse signal φ
The clock generator 50 receives the bit line equalization pulse φ,. However, in the example of FIG. 8, the clock generator 90 generates the row selection line WL.
It also generates activation signals φ and IL. Further, in the example of FIG. 6, the row selection line drive circuit 30 only softens the output signal of the previous stage decoder circuit so that it can drive a large capacity load, but in the example of FIG. 8
0 has a function of forming an AND logic between the output signal of the decoder circuit and the output signal φWL of the clock generator.

That is, as can be seen by comparing the timing chart of FIG. 9 with the timing chart of FIG. 7, when an address signal selects a certain address for a certain period of time, the word line is opened for example only in the first half, and then closed. It is. That is, in this conventional example, the row selection line activation signal φ is generated based on the pulse signal φ generated by the ATD circuit. , is generated. φ8. rises in response to the pulse φ, and is activated (at H level) for a time (τML) required for reading out the memory information of the cell from the memory cell to the bit line. When this required time has elapsed, φ,L falls, and the bit line equalize signal φ, takes its place. stands up.

φ,. After that, the ATD signal continues to hold the H level, and when the address signal changes next time, the ATD signal falls.

In such a conventional example, the row selection line is activated only for the necessary time, so that the first problem in the conventional example described above, that is, the constant flow of current from the bit line load circuit to the memory cell can be avoided.

However, the second and third problems still remain as drawbacks. That is, as described above, the clock signal φ. and φII
Both ILs are generated in response to the rising of the ATD signal chamber. Therefore, φ,. It is difficult to secure a sufficient timing margin between the falling edge of φ and the rising edge of φ, . On the other hand, if a sufficient margin is to be secured, the rising edge of the clock φ8L must be delayed. Furthermore, since the above-mentioned peak current (ICCP) exists, it is necessary for the cell to read out information while drawing this peak current, which is inconsistent with the demand for higher speed memory.

(Problems to be Solved by the Invention) An object of the present invention is to solve the above problems and provide a semiconductor memory circuit that consumes low power and enables high-speed reading.

[Means to solve the problem]

In order to achieve the above object, the present invention configures a semiconductor memory circuit to have the following configuration. That is, in a semiconductor memory circuit that activates a row selection line for the time required for a read or write operation in response to a read or write command, the bit line load circuit changes from the active state to the inactive state of the row selection line. This is a semiconductor memory circuit configured to have low impedance for a predetermined period after the change in impedance.

In other words, in the present invention, the signal φ is generated in response to a change in the address signal, and the signal φ8L is generated in response to the signal φ to open the word line and provide sufficient time for the cell to read data to the bit line. After securing (τ8L), close this and then φ. However, in the conventional example, when the address changes, φ is lowered at the same time as φ8L rises, that is, the word line opens, and φ,L falls at the same time as the word line closes. Whereas in the present invention, φ was increased. After raising φ,. The timing for lowering φ is different. Specifically, the idea is that it is only necessary to secure enough time for the bit line to lower its impedance and be precharged and equalized, and after that necessary time, φ, I try to lower it. By doing this, φ,. In the present invention, as described above, the bit line load circuit composed of the transistor 65 alone or a combination of transistors 63 to 65 is connected to the signal φ. ,. It is activated by the output of
Moreover, the period τ is sufficient for this impedance reduction to be performed by precharging and/or equalizing the bit line. The device is forced to return to the inactive state after continuing for a while.

Although the transistor used in the bit line load circuit in the present invention is not particularly limited, it is preferable to use a transistor (FET). Further, the semiconductor memory circuit according to the present invention can be used as either a synchronous type semiconductor memory circuit or an asynchronous type semiconductor memory circuit.

The period during which the impedance of the bit line load circuit in the present invention is kept low may be arbitrarily determined depending on the characteristics of the memory cell, the bit line load characteristics, etc.

[Function] In the present invention, in order to activate the row selection line for the time necessary for the read or write operation in response to a read or write command, the steady state of the memory cell portion as described above is activated. Current consumption is eliminated. Furthermore, the bit line load circuit of the memory is activated only for a predetermined time after the row selection line changes from the active state to the inactive state.
The period during which the row selection line has a value does not overlap with the activation period of the row selection line, so that it is possible to both reduce the current consumption of the memory cell portion and increase the speed of operation.

[Embodiment] FIG. 1 shows an operation timing diagram of the memory of the present invention. Note that the structure of the memory of the present invention may be the same as that shown in FIG. 8. As shown in FIG. 1, when the address signal changes, the ATD circuit generates a pulse signal φ, and upon receiving this, the clock generator generates a signal φ that activates the row selection line WL.
Generates 8L.

The activation period (τWL) of φ1L is set to the time required to read data from the memory cell to the bit line, and after the required time has elapsed, it falls to inactivate the row selection line. At the same time, a low impedance signal φ is applied to the bit line load circuit. . stands up. The operation up to this point is similar to the conventional example, but in the present invention, φ. does not remain in a low impedance state until the next change in the address signal, and is deactivated after the time required to equalize the bit line (τ) has elapsed.

In order to perform such an operation, the present invention can avoid all of the first to third problems described in the description of the conventional example.

FIG. 2 shows φ used in the semiconductor memory circuit of the present invention,
φ,. τWL, and τ. FIG. 3 is a configuration example of a clock generator that controls the clock generator and its operation timing diagram. In FIG. 2, 14 is an inverter, 3 is a NOR logic circuit, and 6 is an AND logic circuit. Also, 2.5
is a delay inverter, and a Schmitt trigger circuit or the like can be used.

The explanation so far has been about asynchronous memory (memory whose address signal can be changed without synchronizing with signals such as the system clock), but the present invention can also be applied to synchronous memory. It is.

FIG. 3 is an example in which the present invention is applied to a synchronous memory.

In a synchronous memory, an input signal such as an address signal is input in synchronization with a system clock signal CLK. For example, as shown in FIG. 3, the address input signal is the clock C.
In response to the rise of LK, the setup type also
and hold time tH. In the case of a synchronous memory, there is no need to detect changes in the address input signal, and it is sufficient to detect the rising edge of the clock signal CLK and generate the reference signal φ. The row selection line activation signal φw and bit line equalization signal φ1° are generated from this reference signal φ, and these signals are used to perform the memory operation, as in the case of the asynchronous memory described above. .

〔effect〕

According to the present invention, in order to activate the row selection line for the time required for a read or write operation in response to a read or write command, the steady current consumption of the memory cell portion as described above is reduced. It can be avoided. In addition, since the bit line load circuit of the memory has a low impedance for a predetermined period of time after the row selection line changes from the active state to the inactive state, the bit line load circuit has a high gm value and the row selection line has low impedance. There is no overlap between the activation periods of the selection lines, and therefore it is possible to both reduce the current consumption of the memory cell portion and increase the speed of operation. Therefore, a memory that operates at high speed with low power consumption can be realized.

[Brief explanation of drawings]

FIG. 1 is an operation timing diagram of the semiconductor memory circuit of the present invention. FIG. 2 shows an example of the configuration of a clock generator and its operation timing diagram. FIG. 3 is a diagram showing operation timing in an example in which the present invention is applied to a synchronous memory. FIG. 4 is a diagram showing an outline of a semiconductor memory circuit of Conventional Example 1. FIG. 5 is an operation timing diagram of Conventional Example 1. FIG. 6 is a diagram showing an example of a semiconductor memory circuit of Conventional Example 2. FIG. 7 is an operation timing chart of conventional example 2. FIG. 8 is a diagram showing an example of a semiconductor memory circuit of Conventional Example 3. FIG. 9 is an operation timing diagram of Conventional Example 3. 1.4...Inverter, 2.5...Delay inverter, 3...NOR circuit, 6...AND circuit, 1
0... Address buffer, 20... Decoder, 30... Word line drive circuit, 40... ATD circuit, 50... Clock generator, 60... Bit line load circuit, 70... Memory Cell, 80... Row selection line drive circuit, 100... Bit line selection decoder.

Claims (1)

[Claims] 1. In a semiconductor memory circuit that activates a row selection line for the time required for a read or write operation in response to a read or write command, the bit line load circuit changes the row selection line from an active state to an inactive state. 1. A semiconductor memory circuit characterized in that the impedance becomes low for a predetermined period after changing to .