JPH02244253A - Multiprocessor system containing common spread memories - Google Patents

Abstract

PURPOSE:To assure the consistency between a physical address space of a processor and an entire system physical address space and to attain the sequence of processes among processes by preparing a physical address space connected to all memory devices. CONSTITUTION:The number of instruction process means connected to a communication bus 7 is decided at starting of a system and the physical addresses assigned to the memory devices 3a to 3d are decided in an entire physical address space of the system via an address deciding means 6. Then the means 6 assigns the different addresses to the devices 3a to 3d of each processor according to their capacities as well as the number of instruction process means connected to the bus 7 at starting of the system. Thus a continuous address space is formed in a system as a whole. As a result, the number of processors can be freely selected in the system and a flexible system constitution is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system having a single distributed shared memory, and more particularly to a multiprocessor system having a distributed shared memory suitable for general-purpose multiprogramming.

[Conventional technology]

A conventional distributed shared memory multiprocessor system includes multiple processors (each having its own memory device), as described in Japanese Patent Laid-Open No. 56-155465.
and the shared memory device are connected by a switching control device,
There is a method of allocating a part of the physical address space to a processor-specific memory device. In this method, when a processor determines that the reference is not to its own memory device and issues a request to the outside, the switching control device notifies either the shared memory device or the memory device of another processor of the request.

Also, JP-A-63-109563 and JP-A-63-
The technology described in No. 111563 has a configuration in which a plurality of processors are connected on a communication bus. The former defines an area with a communication bus and a common address for each processor, and when a processor refers to this area, it refers to the shared memory space, and when a processor refers to another address area, it refers to the processor-specific address area. This method refers to the memory device. The latter allocates memory devices unique to each processor to different parts of the physical address space, and when a processor refers to an address outside its own memory device, it converts the processor's address to an address on the communication bus, and This method notifies the request to other memory devices via the .

[Problem to be solved by the invention]

In the technique of JP-A-56-155465 mentioned above, when data is shared between processors, and due to the capacity limitations of the memory device specific to the processor, the program area and data area are stored in the shared memory device or in the memory device of other processors. If the switching control device is installed, requests to the switching control device may be made frequently, which may cause speed reduction. other,
There is a physical limit to the number of processors that can be connected to a switching control device.

In the technique disclosed in Japanese Patent Laid-Open No. 63-109563, a processor cannot refer to the memory device of another processor unless it is set as a shared address area, and therefore the memory device specific to the processor cannot be used efficiently.

Furthermore, in the technique disclosed in Japanese Patent Application Laid-Open No. 111563/1983, there is an address mismatch between processors, and a request is issued to the memory device of another processor by performing address translation. Therefore, it is impossible to transfer processes between processors, and processors cannot be used efficiently.

Furthermore, JP-A-63-109563 and JP-A-63-
In the technology of 111563, JP-A-56-1554
Similar to the technique of No. 65, when data is shared between processors, and when the program area and data area cannot fit into the processor's own memory device, one communication bus request may occur frequently, resulting in a reduction in speed.

An object of the present invention is to realize a physical address space connected to all memory devices regardless of the number of processors, so that the number of processors can be freely selected, each memory device can be used effectively, and To provide a multiprocessor system having a distributed shared memory, which can easily perform inter-processing migration, realize a memory management method that requires low communication bus requirements, and can perform multiprogramming processing at high speed.

[Means for Solving Problem 1] The above object is to solve the problem by using a multiprocessor system in which each processor is provided with a distributed memory device. .

This is achieved by providing an address determining means that determines the number of units consisting of memory devices, and determines the physical address to be assigned to each memory device within the physical address space of the entire system. same area,
It is divided into a common area and a local area, and the memory management device of each instruction processing means determines whether the access address from the processor is to its own memory device or to the memory device of another instruction processing means, and processes other instructions. An address determining means outputs an access request via a communication bus when it is determined that the memory device is a memory device of a means, and a cache storage device for temporarily storing data referenced via the communication bus is provided. Coincidence control when data is written to one of the devices and the memory device that temporarily stores data, and control between all memory devices when the same area of one memory device is rewritten. This is achieved by providing a matching north machine that performs matching control.

[For production]

The address determining means depends on the number of instruction processing means connected to the communication bus at the time of system startup and the capacity of the memory device installed in each processor.

Assign a different address to each memory device,
The system as a whole forms a continuous address space. As a result, the number of processors in the system can be freely selected, making it possible to have a flexible system configuration.Also, by installing an address determination means, all memory devices can be accessed as one address space by any processor.
Each memory Ml can be used effectively, processes can be easily moved between processors, and the system is suitable for multiprogramming. The installation of a cache storage device has the effect of reducing the number of accesses to the memory device by other instruction processing means by dividing the communication bus, and also increases the speed of access even when not via the communication bus. Each memory device is divided into areas, and the same area is used for programs and data that are commonly used among processors and requires high-speed processing, such as O8 kernels, and the common area is used for user text whose size varies. If the local area is used as a work area only for that processor, each memory device can be used effectively, and a multiprocessor environment capable of high-speed processing can be realized.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

The processors 18 to 1d (PEO to 3) have memory management units I2a to 2d (MCU O to 3), respectively.
) is connected, and the memory device corresponding to the own processor is connected according to the logical address passed from each corresponding processor! 3a~
In addition to accessing 3d (MS 1 to 3), other memory devices can also be accessed by notifying a request to the communication bus. These memory devices 38 to 3d are connected to the processor 18
~1d stores instructions and data to be executed. The shared memory unit [4 (GM) is an input/output unit [15 (Il) that may be omitted depending on the configuration of the multiprocessor system.
o) generally refers to a disk device, display, keyboard, etc., but since they are not directly related to the present invention, they are shown together. 0 Interrupt distribution device [6 (DIST) is the input/output disconnection device [6 (DIST)] is the interrupt distribution device from input/output [5] The communication bus 7 that distributes the signal 12 to each processor via the signal line 8 is a bus consisting of an address line, a data line, and a control line, but it is possible to replace this with a network using metal or optical fiber. It is.

In the above overall configuration, the configuration and operation of the memory management device, which is a feature of the present invention, will be described below.

2, 3, and 4, the memory management device 12a
(Others have the same mechanism).

The second @ has a configuration in which only the data referenced from one communication bus 7 is stored in the cache storage device 25a (Cachθ). In the figure, an address conversion circuit 19a (A
T ) converts the logical address output from the processor 1a into a physical address. Address determination circuit 20a (
AJ) checks the physical address from the address conversion circuit 19a by a mechanism described in detail later, and if it matches the address of the memory device M3a, the memory device i3 is transferred via the memory interface 21a (MS-Inf).
Notify a of the request.

If the addresses do not match, the cache storage device 25a
Notify the request to. By installing this address determination circuit, each processor can access any memory device, and the address space of the entire system can be treated as one.

The cache storage table W258 is stored in the address determination circuit 20a.
If there is a request from , it performs a data read or write operation.

However, if a copy of the data corresponding to the address from the address determination circuit 20a does not exist in the cache storage device 25a (miss).

Bus interface 22a (Bus-I nf)
The request is notified to the communication bus 7 via. When this request is to read data and the data is sent via the communication bus (usually sent in a page-first data block), this cache storage device temporarily stores the data as a copy. By installing this, it is possible to speed up access to other memory devices and significantly reduce the frequency of access to the communication bus.

The bus monitoring circuit 23a (B Man) constantly monitors the communication bus 7 by a mechanism described in detail later, and when a request matching the address of the memory device [3a flows through the communication bus 7, the request is sent to the memory interface 21a. Notify the memory device [3a] via the memory device [3a]. Snoop circuit 24a (
S noop) performs matching control for the cache storage table [25a. That is, the cache storage device 25
Since a has a copy of the data in the memory device of another instruction processing means, when the other memory device updates the original data, it is necessary to invalidate or update the corresponding copy. Therefore, the soup circuit 24a constantly monitors the communication bus 7, compares the address of the write data flowing on the communication bus 7 with the address of the copy held in the cache storage device 25a, and copies the data to the cache storage device 258 if necessary. Disable or update.

These bus monitoring circuit and snoop circuit are a matching mechanism that matches the cache storage device and the memory device.

The memory interface 21a and the bus interface 22a are interface circuits that control two and three signal lines simultaneously, respectively.

Although it includes an arbitration means for processing multiple requests for the same resource, it is not directly related to the present invention and will therefore be omitted.

FIG. 3 shows a memory device 3 in addition to a cache storage device 125a that stores data referenced via the communication bus 7.
This configuration includes a second cache storage device 26a that stores data referenced from a.

If the second cache storage table [26a does not hold a copy of the data corresponding to the address requested by the address determination circuit 20a, the memory interface 21
The request is notified to the memory device 13a via a. The other components have the same configuration and the same operation as in FIG. 2.

At this time, two cache storage devices 25a and 26a
There are no copies of the same data, so there is no need to consider consistency control between the two cache storage devices.

FIG. 4 shows a configuration equipped with a cache storage device 27a for storing data referenced via the communication bus 7 and data referenced from the memory device 3a.

The cache storage device 27a includes an address conversion circuit 19a.
If a copy of the data corresponding to the address does not exist, the address determination circuit 20a is notified of the request. Based on the notified address, the address determination circuit 20a transfers the request to the communication bus 7 or the memory management device ll3a. Its components have the same configuration and operate in the same way as in FIG. In this configuration, the address determination circuit 20a does not intervene when referring to the cache storage table [27a, and the cache storage table ff1i 27a can be referenced faster than the configurations shown in FIGS. 2 and 3.

Next, FIGS. 5 and 6, address determination circuit 20
Two examples of a are shown.

In FIG. 5, registers are provided to store the upper and lower limits of physical addresses assigned to each memory device. The upper and lower limits of addresses of the memory device are stored in upper limit register 200a (U-Rag) and lower limit register 201a (L Reg), respectively. The address from the address conversion circuit 19a is sent to the comparator 20.
2a and 203a (CMP) are compared with the contents of the upper limit register 200a and lower limit register 201a, respectively, and when the address is between the upper and lower limit addresses of both registers, "On" is output from the AND element 204a when LL I II is not present. The exchanger 205a (EXC) converts the request from the address conversion circuit 19a to the memory interface 21a, according to the output of the AND element 204a.
Or connect to the cache storage bag [25a.

FIG. 6 shows a case where address determination is performed by storing the upper few bits of the address of each memory device in a register.For example, the address line is 32 bits.

Assume that each memory device has a capacity of 1 Mbyte.

Since the address inside the memory device can be specified using 20 bits, the length of the mask register 206a (M-Reg) is 12 bits, and by changing this content,
The address assigned to each memory device can be changed in units of IM bytes. Comparator 207a determines whether the upper 12 bits of the address from address conversion port j419a match the value in mask register 206a.

5 and 6 both show the case of the memory management device in FIG. 2, but by replacing the memory interface 21a in FIGS. 5 and 6 with the second cache storage device 26a, , can be made to correspond to FIG. 3, and by replacing the address conversion circuit L9a with the cache storage device 27a and the cache storage bag W125a with the bus interface 22a, it can be made to correspond with FIG.

Next, two types of bus monitoring circuits 23a will be explained with reference to FIGS. 7 and 8. Similar to FIG. 5, FIG. 7 shows the upper limit and lower limit of physical addresses assigned to each memory device stored in an upper limit register 230a (U-Reg) and a lower limit register 231a (L-Rag). .

The address from the bus interface 22a is the comparator 2.
32a and 233a (CM P ) are compared with the contents of the upper limit register 232a and lower limit register 233a, respectively, and the output of the AND element 234a (AND) becomes "1" only when the address is between the upper and lower limit addresses of both registers. The drive circuit 235a is turned on and the address line, data line, and control line from the communication bus are connected to the memory interface 21a.

On the other hand, in the bus monitoring circuit shown in FIG. 8, the upper few bits of the address of each memory device are stored in a mask register 236a (M-Rag), as in the example shown in FIG. Similarly, if the address line is 32 bits and each memory device is 1M byte, the address inside the memory device can be specified with 20 bits, so the mask register 23
The length of 6a is 12 bits. Therefore, comparator 23
7a determines whether the upper 12 bits of the address from the bus interface 22a match the value in the mask register 236a, and only when -M, the drive circuit 235
Turn on a.

Above, the detailed configuration of the parts related to the present invention and the operation of each part of the embodiment shown in FIG. 1 have been explained.

According to this embodiment, each processor can utilize the address space of the entire system spanning all the memory devices, and by distributing the memory devices to each instruction processing means and providing a cache storage device, access requests to the communication bus can be processed. can be reduced. However, in order for these effects to be fully realized, it is necessary to respond to requests from processors to secure memory areas.
It is necessary to allocate memory devices within the same instruction processing means as much as possible, and to minimize the overhead for matching control to always match the contents of each memory device and the cache storage device. Therefore, next, this memory allocation control and -M ratio control will be described in detail.

For memory allocation control, a memory management program is provided in the O8, and this program checks whether there is a necessary amount of free space in the memory device corresponding to the processor that has requested memory reservation. If so, this area is secured, and if not, a free area in the memory device of another instruction processing means is searched for and allocated.

Next is matching the cache storage devices, but first!
Cache storage bag in memory management device of I [25a
temporarily stores a copy of the data referenced via the communication bus 7, that is, the data stored in the memory device of the other instruction processing means. When writing from the processor 1a occurs in the cache storage device 125a, the write data and address are broadcast from the cache storage device 125a to the communication bus 7 via the bus interface 22a, and sent to the corresponding address in the memory device of other instruction processing means. Matching is achieved using a write-through method in which the data is also written. At this time, the memory device that has the relevant data is
As will be described later, this broadcast is detected by the bus monitoring circuit and its contents are updated.

Also, when the same data is in the cache storage device of another instruction processing means, the same broadcast is used. The store-through matching method described here is a conventionally known method, so its details will be omitted.

Note that when a write occurs to the cache storage device,
Cache storage 25 until the correct data is needed
A copy pack method in which a copy of a is not written to the original memory device is also known, but the memory device of the other instruction processing means is a ki yash memory device within the instruction processing means! 25
Since it can be referenced independently of a, the -number ratio becomes complicated and inefficient, and the same applies to the cache storage device described below, which is not used in the present invention.

Conversely, when the memory device containing the original data of the copy it holds is updated by the corresponding processor, the cache storage device 25a needs to invalidate or update the copy. The fact that this memory device is updated first does not occur in the cache storage device of the processor system, and for this purpose, the snoop circuit 24a as described above is provided to perform this matching. ing. The difference between invalidation and update is that when updating, the data rewritten in the original memory device is written to the cache storage device t25a via the snoop circuit 24a, but when invalidating, data is not written and the data is written to the corresponding address. The point is that all you have to do is turn off the bit that indicates the validity of the data. Therefore, in the following, updates and invalidations for numerical ratios may also be referred to as invalidation.

Next, the second cache storage device 26a shown in FIG. 3 stores only a copy of the data in the memory device 13a.

Hence, cache storage! There is no copy overlap with 25a, and there is no need for matching control between the two cache storage devices. Cache storage device [2] by processor 1a
When writing to 6a.

The write-through method described above always maintains the same value with the memory device 3a. Also.

When another processor broadcasts to update the value in the memory device 3a, the broadcast signal invalidates the corresponding copy in the cache storage device 126a to eliminate the mismatch.

Also for writing to the cache storage device 127a shown in FIG. 4, in order to simplify the -number ratio control, the data referenced from the 1 communication bus 7, which is a write-through type, and the data from the memory device 3a are Since the distinction is made by the address determination circuit 20a, this write-through control may be the same as in the case of the cache storage devices 125a and 26a.
On the other hand, in order to cope with updates to the memory device, the second
As shown in the figure, invalidation is performed by the snoop circuit 24a, and as shown in FIG. 3, invalidation is performed in response to a request from the memory group W3a.

Next, matching control from the perspective of memory group [3a] will be explained. When the cache storage device of the other instruction processing means holds a copy of the data at the address assigned to the memory group [3a, when data is written to the memory device 13a.

The memory device [3a needs to invalidate the copy by broadcasting] In this embodiment, a reference bit is provided to indicate whether or not a cache storage device of another instruction processing means owns the copy, By determining this, it is determined whether or not to broadcast the above-mentioned invalidation. This will prevent unnecessary broad strokes.1
communication bus.

The frequency of access to the cache storage device can be reduced.

FIG. 9 is an explanatory diagram of the reference bit 30a(R).

Transfer of data to cache storage.

This is usually done for the number of prefectural data called pages. This one transfer data is shown as a data line 31a (Data I, 1ne) in FIG. One reference bit 30a is provided for each data line. Then, the bus monitoring circuit 23a detects that the cache storage device misses due to an access by another processor and an access request is issued to the communication bus 7, and as a result, the data line 31a containing the access address is read from the memory device 3a. When the reference bit is set, the corresponding reference bit is set to '1', indicating that a copy of this data line is in the cache storage device of another instruction processing means.Therefore, when this reference bit is set, the data Only when a write operation to a line occurs, it is necessary to broadcast a request to invalidate the copy of the cache storage device of the other instruction processing means.After this broadcast, the copy is no longer available to the other instruction processing means.

Reset the reference bit to 0''.

Each data line is typically about 16 to 32 bytes. Therefore, assuming that the data line is 16 bytes and the capacity of the memory device 3a is 1 Mbyte, the storage capacity used for the reference bits may be 64 bits, or 8 bytes. It is free to provide this in the memory device [3a or in an external register, and has no effect on the effect.

Next, in 6 and above, which describes memory devices when area division is performed, it is assumed that the entire area of each memory device is allocated to one address space of the entire system.
By dividing each memory device into areas as described below, the effective use of each memory device and the system configuration suitable for multiprogramming can be further enhanced. Note that although the following description will also focus on the processor la, the memory management device 12a, and the memory device 3a, the same applies to the others.

FIG. 10 shows an example of the correspondence between physical addresses and the memory device 3a that has undergone area division. The address space 1 visible from the processor 1a is the space on the left side of FIG. 10, but the address space actually allocated to the memory device 3a is the space on the right side of FIG. The common region 310a (Common Region) on the left is associated with the common region 300a on the right, which is accessed by any processor with the same address and is set as a region having the same data in each memory device. Common area 311a on the left (SharedRegion O
) is associated with the common area 301a on the right, and the other common areas 312a to 314a are associated with the other memory devices 3b to 3d.
A common region (not shown) is associated with the global region 315a (Global Region) and register region 316a (ROgister Reg).
ion) is associated with the shared memory 4 and a register group (not shown), and these areas 311a to 316a are spaces having a series of addresses that can be accessed from any processor. Left local area 317a (Lo
calR+4ion) corresponds to the right local area 302a and can be accessed only from the processor 1a. The area is divided in this way, and the same area is divided like the OS kernel.
By using a processor such as the above for frequently used programs, the overhead of O8 processing can be reduced.

If possible, use the common area for user programs processed by processors in the same instruction processing means, and use the common area of the memory devices of other instruction processing means only when there is insufficient capacity, which will speed up the processing of user programs. A local area that can be used efficiently and effectively uses each memory device is used as a work area only for the processor in question, and does not require overall memory management for this area, which helps reduce the management load. .

In order to make the area division as described above effective, it is necessary to perform address determination and matching control for this division. For address determination, the address determination circuit 20a shown in FIG. 5 or 6 accesses the memory device 3a for the area 300a or 302a on the right side of FIG. In addition, the bus monitoring circuit 23a of FIG. 7 or 8
Area determination may be performed for the common area Wi, 301a.

Regarding the matching of the same area, similar to the above-mentioned matching control of the cache storage device, when there is a write to the same area, the data is written via one communication bus 7 or a matching bus provided separately from the communication bus 7. All you have to do is broadcast the write data and address. At this time, the bus monitoring circuit 23
In step a, area determination is also performed for the same area 300a to detect this.

Next, the matching of cache storage devices when area division is performed will be explained. FIG. 11 shows a memory access operation including -number ratio control of the cache storage device 27a (FIG. 4) in the memory device 3a that has undergone area division, and up to the seventh column are conditions (access contents). , and subsequent ones indicate behavior according to the conditions. 1st column (Acces
s5source) is P when the data reference request source is the processor 1a, and B when it is the communication bus 7. The second to fifth columns indicate to which area the read (R) or write (W) is requested, and the same area 310a (C
ommon).

Common area 311a (Inner 5hared),
Common areas 312a to 314a of other memory devices (Out
er 5hared), and local area 317a (
The sixth column (C
ache Hit) is H1 when a copy of the requested data exists in the cache storage device 27a, and M when a copy of the requested data does not exist. The seventh column (Migration) indicates whether a copy of the requested data exists in the cache storage device of the other instruction processing means, that is, whether the reference bit is set. Same area 300a (Common) of memory device, common area 30+, a (Inner Shared),
Local area 302a (Local), cache storage device 27a (Cache), and communication bus 7 (
Read (RD), write (w'r) to Cow,)
, indicates invalidation (INV). For example, in the first line, the processor 1a issues a read request for data in the local area 317a, and a copy of that data is sent to the cache storage device 1.
127a, it indicates that the read request is transmitted only to the cache storage device 27a.

Note that Fig. 11 is a diagram when the area is divided into three, but if the area is divided into two or if area division is not performed, requests and operations for areas that do not exist should be omitted. In addition, in the cache storage device 1125a in FIGS. 2 and 3, there is a copy of only the requested data to the common areas 312a to 314a, and in the second cache storage device 26a in FIG. , same area 3
10a, common area 311FM, and local area 317a, it is preferable to omit other conditions for the cache storage device. Further, the matching control mechanism in the operation shown in FIG. 11 may be the same as that shown previously in FIGS. 2 to 9.

Finally, using FIG. 1, address determination by the interrupt distribution device 6 at system start-up will be explained. When a reset signal is sent to the 1-interrupt distribution device 6 at system start-up, the interrupt distribution device 6 activates the processor 1a with the signal AIa8 to execute a hardware check in the instruction processing means. When the processor 1a finishes the hardware check, the capacity of the memory device 3a (
When the area is divided, the capacity of each area is checked and the interrupt distribution device 6 is notified. Thereafter, the interrupt distribution device 6 sequentially activates the processors lb, lc, and ld and executes the same operations. Finally, a continuous physical address space is constructed from the capacity of each memory device, and the address of each area is notified to each processor. Processor 1a sets this in the upper limit register and lower limit register or mask register in the memory management device. Other processors lb, l
The same applies to c and ld. As a result, the structure of the address space as explained in FIG. 10 can be configured dynamically depending on the number of processors, and a flexible system can be realized.

〔Effect of the invention〕

According to the present invention, there are four effects.6 The first effect is that consistency between the physical address space of the processor and the physical address space of the entire system is guaranteed, so that process migration between processors is possible. This allows efficient use of the processor.

Second, when starting up the system, the physical address space of the entire system and the physical addresses of the memory devices are re-determined depending on the number of instruction processing means, so the number of processors can be increased or decreased depending on the usage pattern.

It is possible to realize a flexible multiprocessor system that can make maximum use of the physical address space.

Third, by using cache storage, -
The data referenced via the communication bus can be stored, and subsequent data references can be made without going through the communication bus.
References can be made faster. Also.

References to the same area are guaranteed to be identical by the hardware that performs the identification, so the processor can refer to the shared memory device as if it were owned within its own instruction processing means. High-speed reference to shared data becomes possible.

Fourth, in a memory device with area division, it is possible to place operating system kernel data in the same area, user data in a common area, and work area in a local area, making it an environment suitable for multiprogramming. can be realized.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a system showing an embodiment of the present invention;
FIG. 2, FIG. 3, and FIG. 4 are diagrams showing configuration examples of three types of memory management devices, FIGS. 5 and 6 are diagrams showing configuration examples of two types of address determination circuits, and FIG. FIG. 8 is a diagram showing a configuration example of two types of bus monitoring circuits, FIG. 9 is an explanatory diagram of reference bits, and FIG. 10 is a diagram showing address correspondence when area division is performed. FIG. 11 is an explanatory diagram of matching control of the cache storage device. 18-1d... Processor, 28-2d... Memory management device, 38-3d... Memory device, 4... Shared memory, 6... Interrupt distribution device, 7... Communication bus,
19a...Address conversion circuit, 20a...Address determination circuit, 23a...Bus monitoring circuit, 24a...
Snoop circuit, 25a, 26a, 27a... Cache storage device, 30a... Reference bit, 300a
. 310a-same area, 301a, 311a, 31
2a, 313a, 314a... common area, 30
2a, 317a...local area. Representative Patent Attorney Tadashi Akimoto Actual Figure Figure 78 Oral Figure Figure 78

Claims (1)

[Scope of Claims] 1. A plurality of instruction processing means each having at least a processor, a memory device, and a memory management device for managing access to the memory device are connected by a communication bus;
Each of the memory devices is allocated a different part of the physical address space of the entire system, and the memory management device in the instruction processing means is configured to provide an address for converting a logical address from a processor in the instruction processing means into a physical address. If the conversion means and the physical address outputted from the means are in a memory device within the instruction processing means, an access request is output to the memory device, and if not, an access request is output to the memory device of the instruction processing means other than the instruction processing means. an address determination means for outputting an access request to the device; and a copy of some data in the other memory device to respond to the access request to the other memory device, and if the requested data does not exist; A first cache storage device that accesses the other memory device via a communication bus, and writing to the cache storage device or writing to the other memory device that has data that the cache storage device has as a copy occurs. and matching means for performing matching control to match the contents of the first cache storage device and the other memory device or invalidate the corresponding data in the first cache storage device when the first cache storage device and the other memory device A multiprocessor system with distributed shared memory featuring 2. Provided in each of the instruction processing means, having a copy of some data of the memory device of the instruction processing means, and responding to a request for access to the memory device from the address determination means, if requested. 2. The multiprocessor system with distributed shared memory according to claim 1, further comprising a second cache storage device that accesses said memory device when no data exists. 3. The first and second cache storage devices are integrated into one cache storage device and accessed using the physical address from the address conversion means, and when the corresponding data does not exist, the data is accessed via the address determination means. The configuration is such that the memory device within the instruction processing means or the other memory device of the other instruction processing means is accessed via the communication bus, and the matching means accesses the other memory device within the integrated cache storage device. 3. The multiprocessor system having a distributed shared memory according to claim 2, wherein the multiprocessor system with a distributed shared memory performs control to match the copy of the device with the corresponding data of the other memory device. 4. A shared memory is connected to the communication bus, and a portion of the physical address space that is different from the memory device is allocated to the shared memory.
A multiprocessor system having distributed shared memory as described in 2 or 3. 5. Address determining means for determining a physical address to be allocated to each of the memory devices, if any, and each of the shared memory devices, if any, to be allocated to the shared memory, in the physical address space of the entire system. 4. Distributed sharing according to claim 1, 2 or 3, characterized in that when the system is started up, a physical address to be allocated to each of the memory devices and the shared memory, if any, is determined according to the number of the instruction processing means. A multiprocessor system with memory. 6. Each of the memory devices is allocated to the same area that is controlled to always have the same value as the other memory devices, and to a different position in the physical address space, and is assigned to a different location in the physical address space, It is characterized by being divided into three areas, or two areas among the three areas: a common area that can be referenced from the processor via a communication bus, and a local area that can be referenced only within the instruction processing means. A multiprocessor system having a distributed shared memory according to claim 1, 2, 3 or 4. 7. An address determining means is provided for determining a physical address to be allocated to the common area of each of the memory devices and the shared memory, if any, in the physical address space of the entire system; 7. A multiprocessor system having a distributed shared memory according to claim 6, wherein physical addresses to be assigned to each of said common areas and said shared memory, if any, are determined in accordance with the number of instruction processing means. 8. The memory device has a reference bit indicating whether or not a copy of the data of the memory device exists in a cache storage device other than the other instruction processing means, and when writing to the memory device, If the reference bit indicates the existence of a copy, a matching request is output via the communication bus, and the matching means of the other instruction processing means invalidates or updates the corresponding data in the other cache storage device. Claims 1 and 2, characterized in that:
A multiprocessor system having distributed shared memory according to 3, 4, 5, 6 or 7. 9. A memory management program is provided in the instruction processing means, and when it becomes necessary to secure a certain amount of physical address area for the processor, the memory management program:
If the predetermined amount of address area exists in the memory device of the instruction processing means, the area is allocated, and if it does not exist, the address area of the memory device of another instruction processing means is controlled to be allocated. Claims 1, 2,
A multiprocessor system having a distributed shared memory according to 3, 4, 5, 6, 7 or 8. 10. When the memory device is divided to include the same area, when a write request to the same area occurs, the write address and data are sent via the communication bus or a separately provided identification bus. 8. A multiprocessor system having a distributed shared memory according to claim 6, wherein said instruction is broadcast to other instruction processing means and matched with data in the same area of another memory device.