JPH02243060A - Magnification and reduction circuit for picture data - Google Patents

Abstract

PURPOSE:To magnify and reduce a picture data at an optional magnification by inputting a value N to an circuit as a 1st value when the adder circuit outputs no carry signal and inputting a value 2P-M+N to the adder circuit when the circuit outputs the signal. CONSTITUTION:When a carry signal CY is not outputted from a P-bit adder 5, a multiplexer 10 selects a data of a register 8 and when the carry signal CY is outputted, the multiplexer 10 selects a data of a register 9 respectively and the data is latched in a latch 6. For example, when a picture data is magnified or reduced to a multiple of N/M, a numeral N is set the register 8 and a numeral (X+N) (=2P-M+N) is set to the register 9 respectively. In the case of reducing the picture data, a reference clock CLKB is outputted to a terminal S and given to a P/S circuit 1, and a clock CLKC is outputted to a terminal D and given to an S/P circuit 3. In the case of magnifying the picture data, the reference clock CLKB is outputted to the terminal D and given to the S/P circuit 3, and the clock CLKC outputted to a terminal S and given to the circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for enlarging/reducing image data such as a figure of a document converted into a digital signal in a facsimile machine or a document file system.

[Conventional technology]

In a facsimile machine or the like, if the processing size differs between the sending side and the receiving side, it is necessary to enlarge or reduce the image data. Furthermore, in devices that perform image processing such as document file systems, image data is frequently enlarged or reduced.

Many methods for enlarging/reducing image data have already been developed and put into practical use.Some methods apply advanced data interpolation processing, while others simply thin out data or duplicate the same data. Various methods are known.

The latter method, which is relatively easy to configure with high-speed processing and hardware, is recommended when low cost is required even though a large amount of data is handled, such as with a facsimile machine or document file system. They tend to be adopted.

For example, Japanese Patent Laid-Open No. 60-20632 discloses a parallel/serial conversion circuit that outputs source data bit by bit using a carry signal output from a P-focus adder circuit, and an output of this parallel/serial conversion circuit. By making the clock that operates the serial/parallel converter circuit that captures data one pin at a time and converts it into destination data variable according to the magnification/reduction ratio, the data can be increased from a minimum of 1/2' times to a maximum of 2r times. A circuit has been proposed for enlarging/reducing image data up to [Problem to be solved by the invention] By the way, in the above-mentioned invention of JP-A-60-20632, when reducing image data by a factor of 2, for example, one of the adder circuits is 2P/2=2P-' is set as 2 data. in this case,
2r-1 is an integer, but in the case of reduction by a factor of 173, for example, 2P/3 does not become an integer. Therefore, the above-mentioned invention of JP-A-60-20632 cannot reduce the size by 1 to 3 times.

More specifically, in the invention of JP-A No. 60-20632 mentioned above, when enlarging, the number is 2P/N, and when reducing, the number is N.
/21 times (N-1 to 2P-1) is possible.

However, in document file systems and the like, it is necessary to perform enlargement/reduction at an arbitrary magnification depending on the screen size, etc., so the invention of Japanese Patent Laid-Open No. 60-20632 mentioned above cannot handle this.

The present invention was made in view of these circumstances, and
The purpose of the present invention is to provide a circuit for enlarging/reducing image data that can be enlarged/reduced at any magnification.

[Means to solve the problem]

The present invention provides a parallel/serial conversion circuit that inputs parallel data and outputs it as serial data in synchronization with a first tarok;
a serial/parallel conversion circuit that sequentially inputs the output data of the parallel/serial conversion circuit at the timing of a second clock and outputs it as parallel data;
a P-bit adder circuit that inputs the value of and adds the first value and the second value in synchronization with a third clock, and generates a fourth clock from the carry signal output from the adder circuit. a clock generation circuit, the third clock and the fourth clock;
a selector circuit that selectively supplies the clock to the parallel/serial conversion circuit and the serial/parallel conversion circuit as the first and second clocks according to expansion/reduction, and the selector circuit is configured to multiply the original image data by M/N. Or N/M times (A-1~2P, N
=1 to 2ゝ-1, M>N), when the adder circuit does not output a carry signal, the value N is output, and the adder circuit outputs the carry signal. The present invention is characterized in that it includes means for inputting the value 2P-M+N to the adding circuit as the first value when the value 2P-M+N is being output.

(Function) In the image data enlargement/reduction circuit of the present invention, when using a P-bit addition circuit, image data is enlarged at an arbitrary magnification between the minimum reduction rate 1/2' times and the maximum expansion rate 2P times.・It is possible to reduce the size.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 is a block diagram showing the configuration of an image data enlargement/reduction circuit according to the present invention.

In the figure, 1 is a parallel/serial conversion circuit (hereinafter referred to as a P/S circuit). Bit image data is input to this P/S 73 circuit, for example, output from an image memory (not shown), and bits are input in parallel at the falling edge of the P/S clock output from the S terminal of the selector 11, which will be described later. The data is sequentially output one bit at a time as serial data to the S/P circuit 3, which will be described later.

2 is a counter, which counts the P/S clock output from the S terminal of the selector 11 mentioned above.
The number of bits output from the S circuit 1 is counted to control the input of data to the P/S circuit 1.

3 is a serial/parallel conversion circuit (hereinafter referred to as S/P circuit). This S/P circuit 3 receives the serial data output from the above-mentioned P/S circuit 1 and the S/P output from the D terminal of the selector 11.
The clock is inverted by an inverter 21 and then applied. Then, the S/P circuit 3 sequentially inputs the serial data output from the P/S circuit 1 one bit at a time at the rising edge of the S/P clock output from the D terminal of the selector 11, and inputs these data! It is output as bit parallel data to, for example, an image memory (not shown).

4 is a counter, which counts the S/P clock output from the D terminal of the selector 11 mentioned above.
The number of bits input from the P/S circuit 1 to the P circuit 3 is counted to control the output of data from the S/P circuit 3.

A P-bit adder 5 adds P-bit input data A from the latch 6 and P-pinto input data B from the latch 7, and outputs P-bit addition result data S and a carry signal cy.

Both the latch 6 and the latch 7 described above operate in synchronization with the basic clock, with the latch 6 latching the output of the multiplexer 10 and the latch 7 latching the output S of the P-bit adder 5.

Multiplexer 10 is provided with the outputs of two registers 8.9. Carry signal C from P-bit adder 5
If Y is not output, the multiplexer 10 selects the data in register 8, and if the carry signal cy is output from the P-bit adder 5, the multiplexer 10 selects the data in register 9 and sends it to launch 6. Have lunch.

The values set in both registers 8.9 are determined as follows. That is, for example, when enlarging or reducing image data by N/M times, the numerical value N is stored in the register 8, and the numerical value X+N(-
2P-M+N) are set in register 9, respectively.

11 is a selector which selects the reference clock CLKB and the clock CLKC obtained by extracting the carry signal CY from the P-bit adder 5 using the reference clock CLKB according to either enlargement or reduction, to the P/S circuit 1 and the S/P. Assign to circuit 3. Specifically, when reducing image data, the reference clock CLKB is output to the S terminal and applied to the P/S circuit 1, and the clock CLKC is output to the D terminal to provide the S/P circuit 1.
feed into circuit 3. Conversely, when enlarging image data, the reference clock CLKB is outputted to the D terminal and applied to the S/P circuit 3, and the clock CLKC is outputted to the S terminal and applied to the P/S circuit 1.

Next, the operation of the above-mentioned circuit of the present invention will be described first in the case of 2/3 times reduction.

Since it is 273 times, M=3. N=2. If the number of bits P of the P-bit adder 5 is 4 bits (P=4), then X+N-2P-M+N=2P-3+2.

Therefore, the value 2 is set in register 8, and the value 15 is set in register 9.

FIG. 2 is a table showing the relationship between the number of cycles of the reference clock CLKB and the input/output of the P-bit adder 5 in each cycle. In the first cycle of the reference clock CLKB, the input A of the P-bit adder 5 becomes 15, and the input B becomes 0.

In the first cycle of the reference clock CLKB, the input A-1
5. Since the input B=O, the output S of the P-bit adder 5
(A+B) becomes 15. However, in this case, no carry occurs, so the carry signal CY is 0'.

In the second cycle, the carry signal CY=
Since it is “O”, multiplexer IO selects register 8 as input A of P-bit adder 5, and input B is the output of P-bit adder 5. Therefore, input A-2. Since the input B=15, the addition result of the bit adder 5 becomes 17. Therefore, the output S of the P-bit adder 5 is l
Therefore, the carry signal CY becomes "1".

In the third cycle, the carry signal CY=
Since it is "1", multiplexer 10 selects register 9 as input A of P-bit adder 5, and input B is the output of P-bit adder 5. Therefore, input A-15. Since the input is B-1, the addition result of adder 5 (P peer) is 1.
It becomes 6. Therefore, the output S of the P-bit adder 5 becomes O, and the carry signal CY becomes "L".

Thereafter, operations are performed in the same manner as shown in the table of FIG.

FIG. 3 is a timing chart when the above-mentioned image data is reduced to 2/3 times.

When reducing image data, the selector 11 outputs the reference clock CLKB from the S terminal and outputs the P/S clock CLKB.
The clock CLKC is connected to the P/S circuit 1 as KP/S.
The signal is outputted from the terminal, inverted by an inverter 21 as an S/P clock CLKS/P, and then applied to the S/P circuit 3.

As is clear from FIG. 3, when reducing image data, the reference clock C is sent from the selector 11 to the P/S circuit l.
The same number of P/S clocks CLIP/S as IJBs are given. Therefore, the P/S circuit 1 sequentially outputs all input parallel data to the S/P circuit 3 in response to the P/S clock CLKP/S.

On the other hand, the S/P clock CLKS/P of 2 clocks is applied from the selector 11 to the SIP circuit 3 during 3 clocks of the reference clock CLKB. Therefore, the S/P circuit 3 has P
Two pins out of three bits of serial data sequentially inputted from the /S circuit 1 are converted into parallel data and output in response to the S/P clock CLKS/P.

That is, when reducing image data, the parallel data input to the P/S circuit 1 is output from the P/S circuit 1 as serial data as shown by 0.1, 2, etc. in FIG. 2 out of the 3 bits are output to the S/P circuit 3.
It is input as shown by ', 1', 2, . . .

In this case, the focus 0゛ input to the S/P circuit 3 is P/
Similarly, bit 0 output from S circuit 1 becomes 2 for 1', 4 for 2', 5 for 3°, and so on, and these data O'', 1', 2' ... is output as parallel data from the S/P circuit 3. Therefore, the image data output from the S/P circuit 3 is reduced to 273 times the image data input to the P/S circuit 1. become.

On the other hand, FIG. 4 is a timing chart when image data is enlarged 372 times.

When enlarging image data, the selector 11 outputs the reference clock CLKB from the D terminal and uses the S/P clock CL
The clock CCL is inverted by the inverter 21 as KS/P and outputted from the S terminal to the S/P circuit 3, and the clock CCL is outputted from the S terminal as P/S.
It is given to the P/S circuit 1 as a clock CLKP/S.

As is clear from FIG. 4, when expanding the image data, the reference clock C is sent from the selector 11 to the P/S circuit 1.
Two clocks of P/S clock CLKP/S are applied between three clocks of LKB. Therefore, the P/S circuit 1 outputs 2 bits out of 3 bits of input parallel data to the SIP circuit 3 bit by bit in correspondence with the P/S clock CLKP/S.

On the other hand, from the selector 11 to the S/P circuit 3, the same number of S/P clocks CL as the reference clock CLKB and the S/P are inverted by an inverter 22 and then provided. Therefore, S
The /P circuit 3 sequentially inputs all of the serial data output from the P/S circuit 1 in response to the S/P clock CLKS/P, and outputs it as parallel data.

That is, when enlarging image data, two of the three bits of the parallel data input to the P/S circuit 1 are
/S circuit l as serial data 0.1, 2.
. . , bit 0' is output to the S/P circuit 3 in synchronization with the reference clock CLKB.

The bit O° input to the S/P circuit 3 is inputted as shown at l"12°... At this time, the bit O° input to the S/P circuit 3 is equal to the bit O" outputted from the P/S circuit 1. l゛ is 0,
2° is 1, 3° is 2, and so on, and these data are output from the S/P circuit 3 as parallel data.

Therefore, the image data output from the S/P circuit 3 is
The image data input to the S circuit 1 will be enlarged 372 times.

〔Effect of the invention〕

As detailed above, according to the image data enlargement/reduction circuit of the present invention, enlargement/reduction is possible at any magnification,
Also, high-speed processing is possible. Furthermore, processing accuracy can be easily improved by increasing the number of bits in the adder circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the image data enlargement/reduction circuit of the present invention, and FIG.
A transition table for the input data and output of the adder circuit for a cycle of 2 times enlargement, FIG. 3 is a timing chart for 2 to 3 times reduction, and FIG. 4 is a timing chart for 372 times enlargement. 1... Parallel/serial conversion (P/S) circuit 3... Serial/parallel conversion (S/P) circuit 5... P-bit adder 6... Latch 7... U7 8. ...Register 9...Register lO...Multiplexer
11...Selector patent Applicant: Sanyo Electric Co., Ltd. Agent Patent attorney: Noboru Kono

Claims (1)

[Claims] 1. A parallel/serial conversion circuit that inputs parallel data and outputs it as serial data in synchronization with a first clock; and a parallel/serial conversion circuit that outputs the output data of the parallel/serial conversion circuit at the timing of a second clock. A serial/parallel conversion circuit inputs the first value and a second value which is its own output sequentially and outputs it as parallel data, and converts the first value and the second value in synchronization with a third clock. a P-bit addition circuit that adds a second value; a clock generation circuit that generates a fourth clock from a carry signal output from the addition circuit;
and the fourth clock according to the expansion/reduction of the parallel/serial conversion circuit and the serial/
A selector circuit selectively supplies the first and second clocks to the parallel conversion circuit, and the original image data is multiplied by M/N or N/M (M=1 to 2^).
In a circuit for enlarging/reducing image data to P, N=1 to 2^P-1, M>N, if the adder circuit is not outputting a carry signal, the value N is A circuit for enlarging/reducing image data, comprising means for inputting a value 2^P-M+N to the adding circuit as a first value when the circuit outputs a carry signal.