JPH02241044A - Mounting method for semiconductor element - Google Patents
Mounting method for semiconductor elementInfo
- Publication number
- JPH02241044A JPH02241044A JP6310589A JP6310589A JPH02241044A JP H02241044 A JPH02241044 A JP H02241044A JP 6310589 A JP6310589 A JP 6310589A JP 6310589 A JP6310589 A JP 6310589A JP H02241044 A JPH02241044 A JP H02241044A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- volume
- substrate
- cap
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 14
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 238000007789 sealing Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 238000003466 welding Methods 0.000 description 10
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- 238000000354 decomposition reaction Methods 0.000 description 5
- 230000035882 stress Effects 0.000 description 4
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 description 2
- OSGAYBCDTDRGGQ-UHFFFAOYSA-L calcium sulfate Chemical compound [Ca+2].[O-]S([O-])(=O)=O OSGAYBCDTDRGGQ-UHFFFAOYSA-L 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- GTQFGAJYMBBUSO-UHFFFAOYSA-N 2-diazoacetamide Chemical compound NC(=O)C=[N+]=[N-] GTQFGAJYMBBUSO-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- NPLNXWYFAJPNLA-UHFFFAOYSA-N aminosulfamic acid;benzene Chemical compound C1=CC=CC=C1.NNS(O)(=O)=O NPLNXWYFAJPNLA-UHFFFAOYSA-N 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 239000013013 elastic material Substances 0.000 description 1
- 239000006260 foam Substances 0.000 description 1
- 238000005187 foaming Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011344 liquid material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 150000002832 nitroso derivatives Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体素子の実装方法に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for mounting semiconductor elements.
［従来の技術］
従来、バンプを介して半導体素子と基板を接続するギヤ
ングボンディング法では、加熱圧着方法と加圧圧接方法
等がある。ここで、熱、機械的ストレスの耐性を強化す
るため、半導体素子と基板間の電掻を圧接する方法、す
なわち、加圧圧接方法が検討されてきている。−例とし
て、バネまたは圧接治具・を、加圧治具により固定し、
バンプに圧力を加える方法を第４図に示す、基板３の上
面に形成されたパターン４上仁バンプ２を介して半導体
素子１を実装し、略コ字型の金属バネ５で圧接し、半導
体素子１とバンプ２とパターン４とを圧接接続するもの
である。[Prior Art] Conventionally, in the gigantic bonding method for connecting a semiconductor element and a substrate via bumps, there are a heat pressure bonding method, a pressure pressure bonding method, and the like. Here, in order to strengthen the resistance to heat and mechanical stress, a method of press-welding an electric scraper between a semiconductor element and a substrate, that is, a pressure-welding method has been studied. -For example, a spring or pressure jig is fixed with a pressure jig,
The method of applying pressure to the bumps is shown in FIG. The element 1, the bumps 2, and the pattern 4 are connected by pressure contact.
また、第５図は半導体素子１と基板３との間に、光硬化
性、熱硬化性等の収縮性樹脂６を挿入し、その収縮力に
より半導体素子と基板（パターン４）３を圧接する方法
である。Further, in FIG. 5, a shrinkable resin 6 such as photocurable or thermosetting resin is inserted between the semiconductor element 1 and the substrate 3, and the semiconductor element and the substrate (pattern 4) 3 are pressed together by the contraction force. It's a method.
［発明が解決しようとする課題］
しかし、第４因昏こ示すバネまたは圧接治具による加圧
圧接方法は、高い精度を必要とする加圧治具が不可欠で
あり、このとき機械的ストレスは半導体素子１に加わる
という問題がある。また、工程が多く、半導体素子１の
パッケージングも行われていなく、耐湿性がない、また
、第５図に示す半導体素子１と基板３との間に挿入した
樹脂６の収縮力で半導体素子１と基板３を圧接方法では
、樹脂材料の選定が難しく、圧着力、収縮力の大きいも
のでなくてはならない、性能の悪い樹脂では半導体素子
１が基板３から外れてしまうという問題がある。[Problems to be Solved by the Invention] However, in the fourth factor, the pressure welding method using a spring or a pressure welding jig requires a pressure jig that requires high precision, and at this time, the mechanical stress is There is a problem in that it is added to the semiconductor element 1. In addition, there are many steps, packaging of the semiconductor element 1 is not performed, there is no moisture resistance, and the shrinkage force of the resin 6 inserted between the semiconductor element 1 and the substrate 3 as shown in FIG. In the method of press contacting the semiconductor element 1 and the substrate 3, it is difficult to select the resin material, and the resin material must have a large pressure bonding force and shrinkage force.If the resin has poor performance, the semiconductor element 1 may come off from the substrate 3.
本発明は、上述の点に鑑みて提供したものであって、半
導体素子の簡便に封止圧接できることを目的とした半導
体素子の圧接方法を提供するものである。The present invention has been provided in view of the above-mentioned points, and provides a method for press-welding semiconductor elements, which is intended to facilitate sealing and pressure-welding of semiconductor elements.
［課題を解決するための手段及び作用］本発明は、半導
体素子を封止用キャップで封止してその内部に加熱して
体積の増加する材料を充填し、加熱処理により内部の材
料の体積を膨張させ、その体積膨張力により半導体素子
に加重を加え、半導体素子とバンプと基板とを圧接する
ようにしている。[Means and effects for solving the problem] The present invention seals a semiconductor element with a sealing cap, fills the inside with a material whose volume increases by heating, and increases the volume of the internal material by heat treatment. The semiconductor element is expanded, and its volumetric expansion force applies weight to the semiconductor element, thereby bringing the semiconductor element, bump, and substrate into pressure contact.
［実施例］
以下、本発明の一実施例を図面を参照して説明する。第
１図において、半導体素子１を位置決めして基板３のパ
ターン４上に搭載する。このとき、バンプ２は半導体素
子１又は基板３に形成されている。もちろんバンプ２を
半導体素子１と基板３の両方に形成されていてもよい。[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. In FIG. 1, a semiconductor element 1 is positioned and mounted on a pattern 4 of a substrate 3. At this time, the bumps 2 are formed on the semiconductor element 1 or the substrate 3. Of course, the bumps 2 may be formed on both the semiconductor element 1 and the substrate 3.
半導体素子１を基板３上に固定するため、弾力性のある
シート７を用い、半導体素子１と基板（パターン４）３
との間に接着剤８等にてシート７を接着して半導体素子
１を固定する。ここで、シート７は、弾力性のある材料
を用い、例えばゴムシート、プラスチック、薄い金属等
を用いている。尚、薄い金属を用いた場合は、半導体素
子１の面には絶縁を施しておく。In order to fix the semiconductor element 1 on the substrate 3, an elastic sheet 7 is used to secure the semiconductor element 1 and the substrate (pattern 4) 3.
A sheet 7 is bonded between the two using an adhesive 8 or the like to fix the semiconductor element 1. Here, the sheet 7 is made of an elastic material, such as a rubber sheet, plastic, thin metal, or the like. Note that when a thin metal is used, the surface of the semiconductor element 1 is insulated.
次に、下面が開口した金属製の封止用キャップ９にて半
導体素子１を覆う、キャップ９を基板３に例えば半田付
けなどで固定する。キャップ９に穿孔された注入口１０
から液体又は粉末の発泡性プラスチック１１をキャップ
９内に充填する。Next, the semiconductor element 1 is covered with a metal sealing cap 9 having an open bottom surface, and the cap 9 is fixed to the substrate 3 by, for example, soldering. Inlet 10 drilled in cap 9
The cap 9 is filled with a liquid or powdered foamable plastic 11 from above.
尚、注入口は基板３側に設けてもよい０発泡性プラスチ
ック１１の充填後、約１００℃〜２００℃で加熱し、発
泡性プラスチック１１を分解させ窒素ガスを発生して発
泡させる。このとき、発生する発泡性プラスチック１１
の体積膨張力により、シート７上から半導体素子１に加
重を加え、半導体素子１とバンプ２と基板３が圧接摺動
される。The injection port may be provided on the side of the substrate 3. After filling with the foamable plastic 11, the foamable plastic 11 is heated at about 100° C. to 200° C. to decompose the foamable plastic 11 and generate nitrogen gas, thereby causing foaming. At this time, the foamable plastic 11 generated
Due to the volumetric expansion force, a load is applied to the semiconductor element 1 from above the sheet 7, and the semiconductor element 1, the bumps 2, and the substrate 3 are slid into pressure contact with each other.
そして、余分に発生した窒素ガスは注入口１０から外部
に放出される。熱処理後、発泡性プラスチック１１が硬
化したら、注入口１０を塞ぎ、密閉する。また、発泡性
プラスチック１１の硬化後は、体積膨張力と自重とによ
り半導体素子１を常に上から押えつけることになる。Then, the excess nitrogen gas generated is discharged to the outside from the injection port 10. After the foamable plastic 11 is cured after the heat treatment, the injection port 10 is closed and sealed. Moreover, after the foamable plastic 11 hardens, the semiconductor element 1 is always pressed down from above by its volumetric expansion force and its own weight.
第２図は他の実施例を示し、半導体素子１を基板３上に
搭載する場合、上記シート７を省略して発泡性プラスチ
ック１１の体積膨張角番こより圧接する方法である。す
なわち、基板３上に凹部１３を凹設し、この凹部１３の
上面開口部を塞ぐ形で半導体素子１を配置し、上記と同
様にキャップ９内に発泡性プラスチック１１を充填する
ようにしたものである。FIG. 2 shows another embodiment, in which when the semiconductor element 1 is mounted on the substrate 3, the sheet 7 is omitted and the semiconductor element 1 is pressed by a volume-expanding square board of the foamable plastic 11. That is, a recess 13 is formed on the substrate 3, the semiconductor element 1 is placed so as to close the upper opening of the recess 13, and the cap 9 is filled with foamable plastic 11 in the same manner as described above. It is.
第３図では、基板３上に半導体素子１を位置決めする枠
１４を接着剤等で固定し、同様に発泡性プラスチック１
１を充填したものである。尚、発泡性プラスチック（液
体）１１は、絶縁性が高いため、直接半導体素子１に接
触し、押えつけることが可能である。従って、発泡性プ
ラスチック１１の体積膨張力と自重とで半導体素子１を
押えつけ、半導体素子１とバンプ２と基板３とを圧接接
続している。In FIG. 3, a frame 14 for positioning a semiconductor element 1 on a substrate 3 is fixed with adhesive or the like, and a foamed plastic 1
1. Note that, since the foamable plastic (liquid) 11 has high insulating properties, it can directly contact the semiconductor element 1 and press it down. Therefore, the volumetric expansion force and dead weight of the foamable plastic 11 press down on the semiconductor element 1, and the semiconductor element 1, the bumps 2, and the substrate 3 are connected by pressure.
ここで、加熱して体積の増加する発泡性プラスチック１
１の材料としては、不活性ガスを分解して発生させ、気
泡を作るもので次のようなものがある。Here, expandable plastic 1 that increases in volume by heating
Materials No. 1 include the following materials that generate bubbles by decomposing inert gas.
ベンゼンスルホヒドラジン系（分解温度１０３〜１１０
℃）
アゾニトリル化合物系（分解温度１０３〜１０４℃）
アゾカルボン酸系（分解温度１０５〜１１０℃）ジアゾ
アセトアミド系（分解温度９７〜１１４℃）
ニトロソ化合物系（分解温度１２８〜１３０℃）いずれ
も分解して窒素ガスを発生し、発泡する。Benzene sulfohydrazine type (decomposition temperature 103-110
℃) Azonitrile compound type (decomposition temperature 103~104℃) Azocarboxylic acid type (decomposition temperature 105~110℃) Diazoacetamide type (decomposition temperature 97~114℃) Nitroso compound type (decomposition temperature 128~130℃) All decompose. to generate nitrogen gas and foam.
このように、発泡性プラスチック１１を使用することで
、絶縁性が高いため直接半導体素子１に加重を加え、半
導体素子１とバンプ２と基板３とを圧接することが可能
であり、また、液体の発泡性プラスチック１１を充填後
、低温で加熱するだけなので、電気的接触を得る圧接工
程が容易になる。また、半導体素子１上に発泡性プラス
チック１１があり、これ自体の自重が半導体素子１にか
かるため、バンプ２の電気的接合が熱的２機械的ストレ
スを与えても、容易に外れることがない。In this way, by using the foamable plastic 11, it is possible to apply pressure directly to the semiconductor element 1 and press the semiconductor element 1, the bumps 2, and the substrate 3 because of its high insulating properties. After filling the foamed plastic 11, it is only necessary to heat it at a low temperature, so the pressure welding process for obtaining electrical contact becomes easy. Further, since the foamed plastic 11 is placed on the semiconductor element 1 and its own weight is applied to the semiconductor element 1, the electrical bonding of the bumps 2 will not easily come off even if thermal or mechanical stress is applied. .
更に、発泡性プラスチック１１は不活性ガスを発生する
が、不純物、汚染物質を含まず、また、封止用キャップ
９の内部を埋めるため、水分のり一りバスが長くなり、
耐湿性も向上し、全体として信頼性が向上する。Furthermore, although the foamable plastic 11 generates an inert gas, it does not contain impurities or contaminants, and since it fills the inside of the sealing cap 9, the moisture bath becomes long.
Moisture resistance is also improved, and overall reliability is improved.
また、キャップ９内に充填する液体材料としては、液体
窒素、液体酸素、液化ＣＯ□、液化０１その他流化ガス
等があり、これらは、ガス圧で半導体素子１を押える。Further, liquid materials filled in the cap 9 include liquid nitrogen, liquid oxygen, liquefied CO□, liquefied 01, and other fluidized gases, which press the semiconductor element 1 with gas pressure.
更に、硫酸カルシウム、セメントスチレン等は体積膨張
力で半導体素子１を押えるようにしている。Further, calcium sulfate, cement styrene, etc. are used to press down the semiconductor element 1 by volumetric expansion force.
し発明の効果］
本発明は上述のように、半導体素子を封止用キャップで
封止してその内部に加熱して体積の増加する材料を充填
し、加熱処理により内部の材料の体積を膨張させ、その
体積膨張力により半導体素子に加重を加え、半導体素子
とバンプと基板とを圧接するようにしたものであるから
、封止用キャップ内に充填した材料の体積膨張力により
、半導体素子とバンプと基板が圧接され摺動するため、
熱的、機械的ストレスの耐性が向上するものであり、ま
た、従来のようにバネ、圧接治具等で加圧する工程が省
略できて簡便な圧接方法となり、さらに、圧接工程時は
低温で熱処理すれば良いので、熱的ストレスが半導体素
子にかからない効果を奏するものである。Effects of the Invention] As described above, the present invention seals a semiconductor element with a sealing cap, fills the inside thereof with a material whose volume increases by heating, and expands the volume of the internal material by heat treatment. The volume expansion force of the sealing cap applies weight to the semiconductor element, and the semiconductor element, bumps, and substrate are brought into pressure contact with each other. Because the bump and the board are pressed against each other and slide,
This improves resistance to thermal and mechanical stress, and it is a simple pressure welding method that eliminates the conventional process of pressurizing with springs, pressure welding jigs, etc. Furthermore, the pressure welding process requires heat treatment at low temperatures. This has the effect that thermal stress is not applied to the semiconductor element.
第１図は本発明の実施例の断面図、第２図は同上の他の
実施例の断面図、第３図は同上の更に他の実施例の断面
図、第４図は従来例の断面図、第５図は他の従来例の断
面図である。
１は半導体素子、２はバンプ、３は基板、９は封止用キ
ャップ、１１は発泡性プラスチックである。
第４図
代理人 弁理士 石 １）長 七
第５図
−へ（”Ｓ Ｑ、 −Fig. 1 is a sectional view of an embodiment of the present invention, Fig. 2 is a sectional view of another embodiment of the above, Fig. 3 is a sectional view of still another embodiment of the same, and Fig. 4 is a sectional view of a conventional example. 5 are sectional views of other conventional examples. 1 is a semiconductor element, 2 is a bump, 3 is a substrate, 9 is a sealing cap, and 11 is a foamable plastic. Figure 4 Agent Patent Attorney Stone 1) Chief 7 Figure 5 - ("S Q, -
Claims (1)
体素子の実装方法において、半導体素子を封止用キャッ
プで封止してその内部に加熱して体積の増加する材料を
充填し、加熱処理により内部の材料の体積を膨張させ、
その体積膨張力により半導体素子に加重を加え、半導体
素子とバンプと基板とを圧接するようにした半導体素子
の実装方法。(1) In a semiconductor device mounting method in which a semiconductor device and a substrate are bonded via bumps, the semiconductor device is sealed with a sealing cap, the inside of which is filled with a material whose volume increases by heating, and heat treatment is performed. expands the volume of the internal material,
A semiconductor device mounting method in which a load is applied to the semiconductor device by the volumetric expansion force, and the semiconductor device, bumps, and substrate are brought into pressure contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6310589A JPH02241044A (en) | 1989-03-15 | 1989-03-15 | Mounting method for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6310589A JPH02241044A (en) | 1989-03-15 | 1989-03-15 | Mounting method for semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02241044A true JPH02241044A (en) | 1990-09-25 |
Family
ID=13219681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6310589A Pending JPH02241044A (en) | 1989-03-15 | 1989-03-15 | Mounting method for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02241044A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03173436A (en) * | 1989-12-01 | 1991-07-26 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| AT414061B (en) * | 2002-06-03 | 2006-08-15 | Datacon Semiconductor Equip | METHOD AND DEVICE FOR PRODUCING AN IN PARTICULAR VERTICAL ARRANGEMENT OF AT LEAST TWO ELECTRONIC COMPONENTS |
| JP2010238945A (en) * | 2009-03-31 | 2010-10-21 | Nec Casio Mobile Communications Ltd | Method of manufacturing substrate, circuit board, and electronic apparatus |
-
1989
- 1989-03-15 JP JP6310589A patent/JPH02241044A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03173436A (en) * | 1989-12-01 | 1991-07-26 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| AT414061B (en) * | 2002-06-03 | 2006-08-15 | Datacon Semiconductor Equip | METHOD AND DEVICE FOR PRODUCING AN IN PARTICULAR VERTICAL ARRANGEMENT OF AT LEAST TWO ELECTRONIC COMPONENTS |
| JP2010238945A (en) * | 2009-03-31 | 2010-10-21 | Nec Casio Mobile Communications Ltd | Method of manufacturing substrate, circuit board, and electronic apparatus |
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