JPH02239296A - Method and device for synthesizing voice - Google Patents

Abstract

PURPOSE:To prevent the voice synthesis output from being unstable regardless of rough quantization of voice data by constituting a circuit, which generates plural sine waves different in frequency and amplitude as element signals of voice synthesis, of a digital circuit which reads out data from a digital storage device. CONSTITUTION:The read speed is determined by the output of a frequency value code read out from a voice data storage device 14 to control the read, and numerical data of sine waveforms is read out from a waveform storage device 16. Read-out numerical data is converted to an analog signal by a D/A converter 17. The converted analog output is applied to a variable gain amplifier 18. The output of an amplitude value code read out from a voice data storage device 14 is applied to the variable gain amplifier 18 whose gain is controlled, and respective sine waves outputted from the variable gain amplifier 18 are synthesized by a synthesizer 19 to obtain the voice synthesis output. Thus, the voice synthesis output is not unstable regardless of rough quantization of voice data.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a speech synthesis method and device, and in particular to a speech synthesis method and device that performs speech synthesis using a composite sine wave method that can be configured with a simple digital circuit. It is related to the device.

[Conventional technology]

Speech synthesis methods that have been developed can be broadly divided into waveform encoding methods that encode the speech waveform itself, and parameter synthesis methods that use the characteristics of the speech waveform to create parameters. Waveform encoding methods include PCM (pulse code modulation) and DP.
CM (differential PCM), DM (delta modulation), APC
M (adaptive PCM), ADPCM (adaptive DPCM),
There are methods such as ADM (adaptive DM), and parameter synthesis methods. LPG (linear predictive coding), PAR
There are methods such as COR (partial autocorrelation).

By the way, the waveform encoding method simplifies the synthesis circuit that performs speech synthesis, but because the degree of data compression is low, it is necessary to increase the memory capacity of the data memory. In addition, since the parameter synthesis method has a high degree of data compression, it is possible to reduce the memory capacity of the data memory, but on the other hand, the synthesis circuit that performs speech synthesis becomes complicated. 6 Recent advances in large-scale integrated circuit (LSI) technology As it has become easier to create complex synthesis circuits, the parameter synthesis method is becoming mainstream. Since only values can be taken and the waveform is synthesized by performing digital filter calculations, the characteristics of the digital filter may become unstable due to errors during parameter transmission, etc., resulting in pitch deviations and sharpness. There is a problem in that the result is a synthesized sound with no sound. Furthermore, if the quantization is coarsened in order to simplify the configuration, there is a problem that the characteristics of the filter become unstable.

On the other hand, there is a speech synthesis method using a complex sine wave model that can be configured with a simple analog circuit without using a digital filter. This models the voice as a sum of n sine waves with different frequencies f and amplitudes mL. Then, the frequency f and the amplitude mL (1≦i≦n) are determined so that the autocorrelation of the sample voice is equal to the autocorrelation of the model, and each sine wave that becomes an element signal for speech synthesis is defined.

A speech synthesis device that performs speech synthesis using such a speech synthesis method using a composite sine wave model, for example, uses a frequency fl
#Ltf3t...l n that generates a sine wave of ffl
It is constructed by combining n variable frequency oscillators and n amplifiers whose gain is variable with voltage. In this speech synthesis device, the important thing is to give the speech pitch, and for this purpose, for example, this type of composite sine synthesizer is equipped with a phase reset circuit that initializes the phase of the sine wave to O for each pitch period. By using the wave model-based speech synthesis method,
Publicly known documents related to speech synthesis devices that perform speech synthesis include, for example, Japanese Patent Application Laid-open No. 147798/1983,
1-21000, etc. [Problems to be Solved by the Invention] As described above, a speech synthesizer using a composite sine wave speech synthesis method that models speech as a sum of multiple sine waves with different frequencies and amplitudes cannot achieve the required synthesis. It has the advantage that the circuit operates stably even if the audio quantization is coarsened depending on the quality of the audio because no digital filter is used.However, the audio synthesizer uses multiple variable frequency oscillators and variable gain. Since it is constructed from an analog circuit that is a combination of a plurality of amplifiers, there is a problem that there are many analog circuits as circuit elements, and it is difficult to integrate the circuit.

The present invention has been made to solve the above problems.

SUMMARY OF THE INVENTION An object of the present invention is to provide a composite sine wave speech synthesis method that can synthesize speech using a simple digital circuit that can be easily integrated into an integrated circuit.

Another object of the present invention is to provide a speech synthesis device that can be configured using a simple digital circuit. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the ci* Problem] To achieve the above object, in the present invention, speech is modeled by a combination of a plurality of different sine waves, and each modeled sine wave is divided into a frequency value code and an amplitude value code. an audio data storage device that encodes and stores the sine wave waveform in combination with the sine wave, and a waveform storage device that digitizes and stores the waveform of the sine wave;
The successive output speed is determined by the output of the frequency value code read from the audio data storage device, the numerical data of the sine wave waveform is read from the waveform storage device, the read numerical data is converted into an analog signal, and the converted signal is read from the audio data storage device. The analog signal is outputted through an amplifier whose gain is controlled by the output of an amplitude value code to generate a sine wave having a different frequency and amplitude. The feature is that speech is synthesized by the sum of multiple generated sine waves. The present invention also includes an audio data storage device that encodes and stores each sine wave of the audio component using a combination of a frequency value code and an amplitude value code, a waveform storage device that digitizes and stores the waveform of the sine wave, and an audio data storage device. A readout control means that controls the readout by determining the readout speed based on the output of the frequency value code read from the device, a digital/analog converter that converts the readout output from the waveform storage device into an analog signal, and an audio data storage. The apparatus is characterized by comprising a variable gain amplifier whose gain is controlled by the output of an amplitude value code read from the apparatus.

A waveform storage device that digitizes and stores the waveform of a sine wave stores numerical data of the peak value of the sine wave at the phase angle at an address of an address code corresponding to the value of the phase angle of the sine wave.

[Effect]

According to the above means, the speech synthesis device includes a speech data storage device. A waveform storage device, a readout control means, a digital/analog converter, and a variable gain amplifier are provided.

The audio data storage device models audio using a combination of a plurality of different sine waves, codes each modeled sine wave using a combination of a frequency value code and an amplitude value code, and stores the code. Further, the waveform storage device converts the waveform of the sine wave into numerical values and stores it. The read control means determines the read speed based on the output of the frequency value code read from the audio data storage device, performs read control, and reads digitized data of the sine wave waveform from the waveform storage device. The read numerical data is converted into an analog signal by a digital/analog converter. The converted analog output is applied to a variable gain amplifier. In addition, the output of the amplitude value code read from the audio data storage device is applied to a variable gain amplifier that controls the gain, and each sine wave output from the variable gain amplifier is synthesized to generate an audio signal. Get the composite output.

In this way, in the sound synthesis device of the present invention, the circuit that generates a plurality of sine waves of different frequencies and amplitudes, which are the element signals of speech synthesis, is constructed of a simple digital circuit that reads data from a digital storage device. Therefore, multiple sine waves of any frequency and any amplitude can be generated by providing control data for data readout corresponding to the audio signal to be synthesized. As a result, the main part of the sound synthesis device can be configured with a simple digital circuit, and it can be easily integrated into an integrated circuit. Also,
Since speech synthesis is performed using the composite sine wave method, it is possible to provide a speech synthesis apparatus in which the speech synthesis output does not become unstable even if the quantization of speech data for speech synthesis is made coarse.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

In all the figures for explaining the embodiments, the same elements are given the same reference numerals, and repeated explanations thereof will be omitted.

FIG. 1 is a block diagram of the main parts of a speech synthesis device constructed from digital circuits according to an embodiment of the present invention. In FIG. 1, 10 is a speech synthesis circuit which is the main part that performs speech synthesis. 11 is an oscillator, 12 is a force counter, 13 is an address counter, and 19 is a synthesizer for outputting the synthesized voice. The main part of the speech synthesis circuit 10 stores speech data in which the frequency and amplitude values of each sine wave, which are elemental component signals for speech synthesis, are coded by a combination of a frequency value code and an amplitude value code. A ROM group 14 of storage devices including an audio data storage device, a frequency divider group 15, a sine wave generator group 16 including a waveform storage device storing numerical data of a sine wave waveform, and a digital/analog converter group. 17, and an attenuator group 18 are provided. Speech synthesis circuit 10
In the ROM group 14, each circuit element in the divider group 15, sine wave generator group 16, digital/analog converter group 17, and attenuator group 18 is provided correspondingly to each ROM in the ROM group 14. ing. The sine wave generator of each circuit element of the sine wave generator group 16 generates a sine wave from numerical data of a sine wave waveform. That is, each circuit element of the frequency divider group 15 is controlled by the code data of the frequency value code of the audio data, and the reading speed of numerical data of each sine wave waveform is controlled. As a result, the reading speed of each sine wave generator of the circuit element of the sine wave generator group l6 is individually controlled, and digital data of numerical data of a plurality of sine waves having different frequencies is output from each sine wave generator. Read out. Each read sine wave digital data is applied to an individual digital/analog converter of each circuit element of the digital/analog converter group 17 and converted into a sine wave analog signal. The individual analog signal sine waves are further applied to the attenuator of each circuit element of attenuator group 18. The attenuation degree of the attenuator of each circuit element of the attenuator group 18 is controlled by the code data of the amplitude value code of the audio data read from each ROM of the ROM group 14, and the gain amplified by the amplifier is variable. and output as a sine wave with a predetermined amplitude value. A plurality of sine waves having different frequencies and amplitudes output from the attenuators of each circuit element of the attenuator group 18 are synthesized by a synthesizer 19 and output as a synthesized audio output.

Further, the oscillator 11 here generates a basic timing CLKI for the speech synthesis circuit 10 that performs speech synthesis, and controls the entire circuit. Basic timing CLK from oscillator 11
I is supplied to a counter 12, which generates a pitch frequency timing CLK2 of the pitch period of the voice. counter 1
The pitch frequency timing CLK2 from 2 is supplied to the divider group 15 and the sine wave generator group 16 to control the phase of the pitch period of the synthesized speech. Further, the pitch frequency timing CLK2 is supplied to the address counter 13.

The count value of the address counter 13 provides a read address for the ROM group 14. Next, the individual circuit configurations of the elements of the above-mentioned speech synthesis device will be explained.

In order to generate individual sine waves of elemental component signals for synthesizing audio using the composite sine wave method, a frequency value code giving n frequency values and an amplitude value code giving n amplitude values are combined as audio data. The code data is set in advance. The code data (audio data) of this combination code is
The data is stored in advance as ROM data in the ROM group 14.

FIG. 2 is a diagram showing an example of code data obtained by converting audio data into frequency value code and amplitude value code and combining them. The code data in Fig. 2 is an example of data in which the frequency value and amplitude value of the sine wave of the audio component are coded and combined. This is an example in which audio data in units of time is stored chronologically as code data. In FIG. 2, frequency value code F0. ~F. Il is the aforementioned ROM
It is read out from the group 14 and provides the readout speed of numerical data in a sinusoidal waveform. Also, amplitude value code M0. ~M0 is
It is read from the aforementioned ROM group 14 and provides an attenuation value for controlling the gain of the attenuator group 18. In this way, the frequency value code F1J and the amplitude value code M. The code data FL, ·M, which is a combination of J and J, defines one sine wave.

FIG. 3 is a block circuit diagram showing an example of a speed control circuit that controls the read speed of a waveform storage device that stores a sine wave waveform as numerical data using a frequency value code F of audio data. In Figure 3, CLKI is the basic timing, CLK2 is the pitch frequency timing, D0~
D0 is bit data of the frequency value code FLJ.

This speed control circuit is composed of a group of flip-flops constituting a counter and a group of logic gates for control. For example, in the block diagram of FIG.
This circuit is included in the frequency divider of the 5th element circuit.

This speed control circuit uses, for example, bit data D. of the code value of the frequency value code FLJ. ~Dn to flip-flop CNT2°~CNT2'' with pitch frequency timing CL
This circuit is set by K2 or output signal CNTOUT and counts up by basic timing CLKI. This is a so-called brisset counter. The output cycle of the output signal CNTOUT changes depending on the values of the bit codes D0 to D0 of the frequency value code to be set.

FIG. 4 is a timing chart illustrating an example of the operation of the speed control circuit shown in FIG. This example shows a timing chart for the case where n=3. As shown in the figure, bit data D of the frequency value code. The input of -D is determined before the pitch frequency timing CLK2 occurs, is set in the flip-flop CNT2°-CNT23 at the pitch frequency timing CLK2, and is counted up at the basic timing CLKI. As shown in the figure, when (0001) is given as bit data D0 to D3 of the frequency value code, the period of the output signal CNTOUT is the basic timing C
It is output every 8 cycles of LKI. The output signal CNTOU is output according to the bit data value of the frequency value code that is set.
The period of T changes.

FIG. 5 is a block diagram showing the configuration of a main part of an address control circuit that provides a read address for reading digitized data from the waveform storage device. In FIG. 5, 51 is an address counter, and 52 is a ROM that stores numerical data of a sine wave waveform. An address counter 51 that generates an address to be given to the ROM 52 has n flip-flops 5.
It is composed of 1a to 51n. address counter 5
Address data A0 to A, generated from ROM 5
2, the numerical data of the sine wave waveform is sequentially read out. The n flip-flops 51a to 51n of the address counter 51 are reset by the pitch frequency timing CLK2, and the CNTOUT
The signal is used as a trigger to count up sequentially. ROM52 that stores numerical data of the sine wave waveform
stores the numerical data of the peak value of the sine wave at the phase angle in the address of the address code corresponding to the value of the phase angle of the sine wave, and the address counter 51 stores the value of the peak value of the sine wave at the phase angle. By sequentially increasing the read address of the ROM and performing read control, numerical data of the sinusoidal waveform of the contents of the ROM is sequentially read out as the phase angle progresses.

FIG. 6 is a diagram showing an example of ROM data storing sine wave waveform data converted into numerical data based on the correspondence between input addresses and read output data values. As shown in Figure 6, the RO which stores this sine wave waveform data
M associates the binary code values of input addresses 80 to A4 with the phase angle of the sine wave, and stores the wave height of the sine wave at the phase angle in the storage area of the address code corresponding to the phase angle of the sine wave.
Store the level value of the value as numerical data. As a result, when the address data of input addresses A0 to A4 are sequentially counted up and the numerical data is read from the ROM, the numerical data of the peak value corresponding to the progression of the phase angle of the sine wave is sequentially read out, and the numerical data is read out as the read data. , the waveform data of a sine waveform will be output. As described above, the circuits of each element of the speech synthesis circuit 10 (FIG. 1) that constitutes the main part of the speech synthesis device of this embodiment are as follows.
Since it is composed of a ROM readout circuit which is a simple digital circuit, the main part of the tone synthesis device can be made into a simple digital circuit, and it can be easily integrated into an integrated circuit. Furthermore, since speech synthesis is performed using the composite sine wave method, it is possible to provide a speech synthesis apparatus in which the speech synthesis output does not become unstable even if the quantization of speech data for speech synthesis is made coarse.

Next, another embodiment of the present invention will be described. In the embodiment described above, the waveform storage device that stores the numeric value of the sine wave waveform is included in each sine wave generator of the element circuit of the sine wave generator group 16. ROM group 1
The configuration may be such that it is held as shared data in 5.

FIG. 7 is a block diagram of the main parts of a speech synthesizer constructed from digital circuits according to another embodiment of the present invention. In FIG. 7, 10 is a speech synthesis circuit, 1.1 is an oscillator,
12 is a counter, 13 is an address counter, 14 is RO
M group, 15 is a splitter group, 16 is a sine wave generator group, 17 is a digital/analog converter group, 18 is an attenuator group, and 19 is a combiner. These are similar to those explained in Figure 1. Further, 71 is a RAM section, and 72 is an address selector. In this example. In order to provide control data to the ROM group 14, a RAM section 71 and this RAM are provided.
The configuration further includes an address selector for selecting an address provided by the section 71. In the RAM section 71,
When stored in the ROM group 14, the audio data is stored as code data that is a combination of a frequency value code and an amplitude value code in the same format as the audio data, and is used as some alternative data when changing the ROM data. . Also, this. It is used as selection data for selecting each ROM of the elements of the ROM group 14. Address selector 72 is R.
Select whether the address to be supplied to the AM section 71 is an external address or an address from the address counter 13. In this way, by adding the RAM section 71, which can also be used as a storage device for encoding and storing frequency values and amplitude values, and the address selector 72, which controls the address given to the RAM section 71, it is possible to use a wider area. It becomes a speech synthesis device that can be applied.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, the main part of the sound synthesis device can be configured with a simple digital circuit, and it can be easily integrated into an integrated circuit. Furthermore, since speech synthesis is performed using the composite sine wave method, it is possible to provide a speech synthesis apparatus that does not become unstable in its speech synthesis performance even if the quantization of speech data for speech synthesis is made coarse.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the main parts of a speech synthesis device configured with a digital circuit according to an embodiment of the present invention, and Fig. 2 is a code obtained by converting audio data into frequency value code and amplitude value code and combining them. A diagram showing an example of data. FIG. 3 shows a frequency value code F of audio data for controlling the read speed of a waveform storage device that stores a sine wave waveform as numerical data. FIG. 4 is a timing chart illustrating an example of the operation of the speed control circuit shown in FIG. 3. FIG. A block diagram showing the configuration of the main part of an address control circuit that provides an address. Figure 6 is an example of ROM data that stores sine wave waveform data converted into numerical data based on the correspondence between input addresses and read output data values. FIG. 7 is a block diagram of the main parts of a speech synthesis device configured with digital circuits according to another embodiment of the present invention. In the figure. 10... Speech synthesis circuit, 11... Oscillator,
12...Counter, 13...Address counter, 1
4...R. OM group, 15... Frequency divider group, 16...
...Sine wave generator group, 17...Digital/analog converter group, 18...Attenuator group, 19...Synthesizer, 71
...RA. M section, 72...address selector.

Claims (1)

[Claims] 1. Modeling the voice using a combination of a plurality of different sine waves,
The audio data storage device includes an audio data storage device that encodes and stores each modeled sine wave using a combination of a frequency value code and an amplitude value code, and a waveform storage device that digitizes and stores the waveform of the sine wave. The reading speed is determined by the output of the frequency value code read from the device, the numerical data of the sine wave waveform is read out from the waveform storage device, the read numerical data is converted into an analog signal, and the amplitude value code is read out from the audio data storage device. The analog signal is outputted through an amplifier whose gain is controlled by the output of the sine wave to generate sine waves having different frequencies and amplitudes, and the sound is synthesized by the sum of the plurality of generated sine waves. Synthesis method. 2. An audio data storage device that encodes and stores each sine wave of the audio component using a combination of a frequency value code and an amplitude value code, a waveform storage device that digitizes and stores the waveform of the sine wave, and an audio data storage device. a readout control means that determines the readout speed and controls the readout based on the output of the frequency value code read out from the device; a digital/analog converter that converts the readout output from the waveform storage device into an analog signal; and a digital/analog converter that converts the readout output from the waveform storage device into an analog signal; and a variable gain amplifier that controls gain by outputting an amplitude value code. 3. A waveform storage device that digitizes and stores the waveform of a sine wave stores numerical data of the peak value of the sine wave at the phase angle at the address of the address code corresponding to the value of the phase angle of the sine wave. The speech synthesis device according to claim 2, characterized in that: