JPH0223754U - - Google Patents
Info
- Publication number
- JPH0223754U JPH0223754U JP10153188U JP10153188U JPH0223754U JP H0223754 U JPH0223754 U JP H0223754U JP 10153188 U JP10153188 U JP 10153188U JP 10153188 U JP10153188 U JP 10153188U JP H0223754 U JPH0223754 U JP H0223754U
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- normal operation
- operating normally
- ram
- cpus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
- Multi Processors (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10153188U JPH0223754U (de) | 1988-07-30 | 1988-07-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10153188U JPH0223754U (de) | 1988-07-30 | 1988-07-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0223754U true JPH0223754U (de) | 1990-02-16 |
Family
ID=31330613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10153188U Pending JPH0223754U (de) | 1988-07-30 | 1988-07-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0223754U (de) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005081108A1 (ja) * | 2004-02-20 | 2005-09-01 | Naltec Inc. | プロセッシングユニットを用いた制御装置および制御方法 |
-
1988
- 1988-07-30 JP JP10153188U patent/JPH0223754U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005081108A1 (ja) * | 2004-02-20 | 2005-09-01 | Naltec Inc. | プロセッシングユニットを用いた制御装置および制御方法 |