JPH02236894A - Mos dram type semiconductor device with cell capacity measuring function - Google Patents

Abstract

PURPOSE:To obtain a large amount of cell capacity data automatically by adding a switching function to capacity to be measured and charging and discharging the capacitor, and measuring its charging and discharging currents and finding the cell capacity. CONSTITUTION:A changeover switch S is added to the chip of the capacity to be measured and has an N channel MOS transistor(TR) TRQN1 interposed between one-terminal sides of all bit lines BL and an input terminal (a) and a P channel MOSTRQP1 interposed between the other-terminal sides of all the bit lines BL and an earth terminal (d), and the gates of both the TRs QP1 and QN1 are connected to an input terminal (c) in common. When a driving signal 2 is held at H, the TRQN1 turns on to charge the bit lines BL with a current (i) and when at L, the TRQP1 turns on a discharge the bit lines. At this time, when a signal 1 is at H, a cell MC is also charged and discharged and the total capacity including the cell is the capacity to be measured. When the signal 1 is at L, on the other hand, only the bit lines BL are charged and discharged, so only the total capacity of the bit lines is the capacity to be measured.

Description

[Detailed Description of the Invention] [Summary of the Invention] An object of the present invention is to enable cell capacitance measurement of a MOS DRAM type semiconductor device with a cell capacitance measurement function using a memory measurement system for primary testing. Equipped with a power supply and switch circuit to charge and discharge the capacitance to be measured,
The configuration is such that the cell capacity can be calculated by measuring the charging/discharging current.

[Industrial application field]

The present invention relates to an 8GS DRAM type semiconductor device with a cell capacitance measurement function. The cell capacity of MOS dynamic RAM (MOS DRAM) is an important factor that influences the soft error rate due to alpha rays. In recent years, requirements regarding the error rate of soft errors due to alpha rays have become increasingly strict in DRAMs, and the cell capacity, which has a large influence on the soft error rate, has become an important factor to monitor. Therefore, it is necessary to develop a technology that can easily monitor cell capacity. [Prior art] Figure 6 is a schematic diagram of a conventional DRAM cell capacity measurement method.
MC is a memory cell arranged in a matrix, BL is a bit line, and WL is a word line. This is a monitor chip with only a memory cell, bit II, and word line laid out on a substrate for cell capacitance measurement, and was made for sampling inspection. In this monitor chip, one end of all word lines WL is commonly connected to the human power terminal a,
One end of all word lines WL is commonly connected to input terminal b.

Therefore, apply an H (high) level signal l to input terminal b to select all word lines WL, and in this state connect a capacitance measuring device (LCR meter), not shown, to input terminal a.
The capacitance seen from the terminal, that is, the sum of the capacitance ΣC of all bit lines and the capacitance ΣCM of all memory cells is measured. Also, apply an L (low) level signal l to input terminal b to deselect all word lines WL, and in this state, calculate the capacitance seen from input terminal a, in this case, the capacitance ΣC of all bit lines BL. Measure.
The difference between these two measurement results (ΣC.+ΣCM) - ΣC. =ΣC is divided by the number of cells N to obtain a capacity of 0.4 per cell.

N equipment is required, and a power source for each signal is also required. Furthermore, since the monitor chip is to be measured, a prober system is also required. Furthermore, when measuring a large amount, a large number of monitor chips are required, and when measuring these automatically, a measuring system controlled by a microcontroller is indispensable. Therefore, large-scale measurements are difficult in terms of cost, and there is a problem that there is little data to statistically manage cell capacity, which is an important parameter. The present invention has been made in view of the above points, and it is an object of the present invention to enable cell capacitance to be measured using a memory measurement system for primary testing of product chips.

That is, on the wafer on which the product chips are constructed,
The aim is to easily measure cell capacity without using a meter or the like.

[Problem to be solved by the invention]

However, in the measurement method shown in FIG. 6, the capacitance is measured [means for solving the problem]. S is the corresponding IC
A is the average current measuring device, and ■ is the charging power source. A switch S and a capacitor C are included in the chip, and an average current measuring device A and a charging power source V are included in the measurement system. The discharge power source of capacity C is earth G,
This is also supplied from the measurement system. A switching signal for the switch S is also supplied from the measurement system. This measurement system is a memory measurement system for primary testing such as a memory tester or wafer prober that measures product chips at the wafer stage.

[Effect]

When the switch S in Figure 1 is switched to the power supply V side and the ground G side, the capacitance C repeats charging and discharging, so the capacitance C can be calculated from the average current ■ measured by the measuring device A. In other words,
The total amount of charge Q stored in capacitor C at voltage V is Q-C-V (1)
The current is the time change of charge i=dq/dt...
・The integral value Sidt of this i, which is (2), is Q in equation (1), which is also the product of the average current ■ measured by measuring device A and the charging time T, so Q= S idt = I・T・・・・・・
-(3) holds true. Therefore, ■ is derived from equations (1) and (3), so if ■ = constant and T = constant, the capacity 1c can be found from the average current 1. switch S
When switching alternately to the power supply V side and the ground G side with a pulse in which the time ratio of high and low levels is 50%, the above T can be expressed by the period of this pulse.

〔Example〕

FIG. 2 is a block diagram showing an embodiment of the present invention, in which a charging/discharging switch S is added to the monitor chip shown in FIG. 6. This may not be a monitor chip, but may be a chip that can be used as an ordinary product, and only allows selection of all word lines and bit lines. This switch S is an N-channel MOS transistor QN. and all bit lines BL
A P-channel MOS transistor QP. and both transistors QPI . The gates of QNI are commonly connected to input terminal C.

All terminals a to d in this example are connected to the measurement system.
First, the first input terminal a is connected to the power source (2) through the average current measuring device A shown in FIG. Further, the second input terminal b is supplied with a signal l which can be switched between H level and L level as shown in FIG. H is the selection level of the word line WL, and L is the non-selection level of the word line WL. Furthermore, the third input terminal C has a period T, as shown in FIG.
Supply switch switching signal 2 that is inverted with a duty of 50%. Connect the remaining ground terminal d to earth. In this circuit, when drive signal 2 is set to H, transistor QN. turns on, bit lIiBL is charged with current i, and when set to L, transistor QP. Is it on? As a result, the bit line is discharged. At this time, if the signal l is at H level, the cell MC is also charged and discharged, and the total capacitance ΣCB+ΣCM including the cell becomes the capacitance C to be measured. On the other hand, if the signal 1 is at L level, only the bit line BL is being charged or discharged, so the total capacitance of the bit line ΣC. Only this becomes the capacitance C to be measured.

Therefore, the difference l between the average current Il of only the bit line BL and the average current 1■ including the cell. is the total capacity ΣCl of only cell MC
4, so if the number of cells is N, then the capacity per cell is C. can be calculated. (2) FIG. 4 shows another example of the configuration of the switch S of the present invention. In this example, the P-channel MOS transistor QPr in FIG. 2 is replaced with an N-channel MOS transistor QN1, and two input terminals c. ,c. Switch switching signal 21 with opposite phase from
．． 22 (see FIG. 5) are two N-channel MOS transistors connected in series (see FIG. 5). This is given to the gate of QN+. In this case, the first input terminal a to which the average current measuring device A is connected, the grounding terminal d to be connected to earth, and the second input terminal C to be connected to the word line WL are omitted in the drawing. Transistor QN+. QN! The relationship between the capacitors C and C is switched such that one is on and the other is off every half cycle T/2, so the capacitor C repeats charging and discharging in the same manner as in FIG.

Although the above example uses a MOS transistor, it can also be applied to a bibolar transistor. [Effects of the Invention] As described above, according to the present invention, DRAM cell capacitance measurement, which has been performed using a capacitance measuring device, can be performed by adding a switching function to the capacitance to be measured to enable charging and discharging. , the capacity can be calculated indirectly by measuring the charging and discharging current,
Wafer prober used in DRAM primary testing, etc.
Cell capacitance can be measured using a measurement system that includes a memory tester, etc., and has the advantage of automatically obtaining large amounts of cell capacitance data at low cost.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the principle of the present invention, Fig. 2 is a configuration diagram showing an embodiment of the present invention, and Fig. 3 is a diagram showing the principle of the present invention.
FIG. 4 is a configuration diagram showing another example of the switch of the present invention; FIG. 5 is a signal waveform diagram of FIG. 4;

Claims (1)

[Claims] 1. A power supply (V) and a switch circuit (S) for charging and discharging the capacitance to be measured are provided, and the cell capacitance can be calculated by measuring the charging and discharging current. A featured MOSDRAM type semiconductor device with a cell capacitance measurement function.