JPH02235440A - Digital audio signal processor - Google Patents

Abstract

PURPOSE:To attain the effective utilization of a D/A converter by outputting a digital audio signal selectively among a signal subjected to the demodulation processing of a transmission signal and a signal supplied to an input terminal. CONSTITUTION:When it is decided that the processing of a signal supplied from an external equipment is commanded, a processor outputs selectively the output of a clock extraction and data demultiplex circuit 21 from a changeover switch 20. Then a digital audio signal demultiplexed from a biphase mark signal supplied to an input terminal IN from an external equipment is supplied to a D/A converter circuit 23 where the signal is converted into an analog audio signal. On the other hand, when the processing of the signal supplied from the external equipment is not commanded, the digital audio signal obtained by applying demodulation processing 9 to an EFM signal read from a disk 1 is supplied to the circuit 23 where the signal is converted into an analog audio signal. Thus, the circuit 23 and LPFs 24, 25 are effectively utilized.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a digital audio signal processing apparatus.

Digital audio signal processing devices, such as digital audio disc players called CD players, digital audio table recorders called DAT, and BS (i4 foot broadcasting) tuners, use transmission signals obtained from recording media or It is purchased to demodulate the transmission signal supplied from the BS antenna to obtain a digital audio signal and then supply it to a digital-to-analog converter to obtain an analog audio fa signal.

In such a conventional digital audio signal processing device, it was not possible to input a digital audio signal output from an external device to a digital to analog converter and perform conversion processing. For this reason, in conventional digital audio signal processing equipment, even if a high-precision digital-to-analog converter is installed, the digital-to-analog converter is used only when playing a digital audio disc, for example, and when receiving satellite broadcasts. It has the disadvantage that it cannot be used in other cases such as time, and cannot be used effectively.

Summary of the Invention The present invention has been made in view of the above points, and includes:
It is an object of the present invention to provide a digital audio signal processing device that can effectively utilize a digital-to-analog converter. - In the digital audio signal processing device according to the present invention, a digital audio input terminal, an output of a demodulating means for demodulating a transmission signal carrying a digital audio signal to obtain a digital audio signal, and a digital audio input terminal. A signal selection means for selectively outputting one of the signals supplied to the terminal according to a command is provided, and the output of the signal selection means is supplied to the digital-to-analog conversion means.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, a disk 1 is rotationally driven by a spindle motor 2. As shown in FIG. As the disk 1 rotates, signals recorded on the disk 1 are read by a pickup 3. The pickup 3 is carried by a carriage (not shown) that is moved in the radial direction of the disk 1 by a carriage motor 4, and the information reading point (information reading light spot) of the pickup 3 is freely positioned in the radial direction of the disk 1. Ru. Further, various servo systems such as a focus servo system, a tracking servo system, and a carriage servo system are provided, but they are not shown because they are already well known.

The spindle motor 2 and the carriage motor 4 are connected to a spindle servo system, a carriage servo system, or a performance section control circuit 5.
driven by. The performance section control circuit 5 is a horizontal sphere that drives the spindle motor 2 and the carriage motor 4, performs on/off control of various servo systems (not shown), jump control, etc. in accordance with commands from the system controller 7.

A so-called RF (high frequency) signal, which is a read signal output from the pickup 3, is amplified by an RF amplifier 81 and then supplied to an EFM demodulation circuit 9. The EFM demodulation circuit 9 is configured to perform EFM demodulation processing on a pulse signal obtained by slicing an RF signal to obtain digital data and subcodes including time-division multiplexed audio information of both left and right channels. Digital data including audio information output from the EFM demodulation circuit 9 is fed to a deinterleaving/interpolation circuit 10.

The deinterleaving/interpolation circuit 10 works with the RAMII using the clock pulses output from the frequency dividing circuit 15 to restore the digital data whose order has been rearranged by the interleaving performed during recording, and returns it to the error correction circuit 12. When the error correction circuit 12 outputs a signal indicating that correction is impossible, the error data in the output data of the error correction circuit 12 is interpolated by an average value interpolation method or the like. Further, the error correction circuit 12
C I R C (Cross Interleave
Deinterleaves digital data by correcting errors using Reed Soloson Code
It is configured to supply the signal to the interpolation circuit 10 and output a signal indicating that the correction is impossible when the correction is impossible.

The dividing circuit 15 outputs the outputs of the clock generation circuits 17 and 18 selectively by the changeover switch 16 to 1/N.
The configuration is such that the frequency is divided into The frequency dividing circuit 15 is configured to generate a frequency divided output synchronized with the timing signal t when a timing signal output from a clock extraction/data separation circuit 21, which will be described later, is supplied.

The changeover switch 16 switches the clock generation circuit 1 in response to a changeover command signal SA supplied from the system controller 17.
It is configured to selectively output one of the outputs 7 and 18. The clock generation circuits 17 and 18 are
It consists of a crystal oscillator, etc., and is configured to generate clock pulses with a frequency N times 44.1 KHz and clock pulses with a frequency N times 48 KHz, respectively.

The output data of the deinterleaving/interpolation circuit 10 is one input of the changeover switch 20. Changeover switch 20
The data output from the clock extraction/data separation circuit 21 is supplied as another input. Changeover switch 2
0 is configured to selectively output the output data of one of the deinterleaving/interpolation circuit 10 and the clock extraction/data separation circuit 21 in response to a switching command signal S8 supplied from the system controller 7. .

The clock extraction/data separation circuit 21 is supplied with a bi-phase mark signal obtained by modulating a digital audio signal using, for example, a bi-phase mark modulation method from an external device via an input terminal IN.

The clock extraction/data separation circuit 21 extracts and outputs a clock signal C from the input biphase mark signal, and uses this clock signal C to extract left and right channel audio information time-division multiplexed from the biphase mark signal. , and outputs a timing signal t synchronized with one of the left and right channel audio information. This clock extraction/data separation circuit 21
The clock signal C output from the system controller 7 is supplied to the system controller 7, the digital audio signal is supplied to the changeover switch 20, and the timing signal t is supplied to the frequency divider circuit 1.
5.

The output of the changeover switch 20 is supplied to a D/A (digital-to-analog) conversion circuit 23. D/A conversion circuit 2
3 is configured to separate digital data including left and right channel audio information time-division multiplexed by the output of the frequency dividing circuit 15 for each channel, convert it into an analog signal, and output audio signals for both left and right channels. It has become. The reproduced audio signals of both the left and right channels output from this D/A conversion circuit 23 are processed through an LPF (
After unnecessary components are removed by low-pass filters 24 and 25, the audio output terminals OUTl. OUT2
is supplied to

On the other hand, the subcode output from the EFM demodulation circuit 9 is
The signal is supplied to a subcode error correction circuit 27 and error correction is performed thereon. The P and Q channel bits of the subcode are supplied to the system controller 7.

The system controller 7 includes, for example, a processor, a ROM
, RAM, timer, etc., and performs arithmetic operations based on data or programs stored in ROM, RAM, etc. in response to commands supplied from the operation unit 28 in response to key operations. Various command signals are sent to the performance section control circuit 5 and changeover switches 16 and 20.

The operation of the processor in the system controller 7 in the above configuration will be explained with reference to the flowchart shown in FIG.

During execution of a main routine or the like, an interrupt from a timer or the like causes the processor to proceed to step S1 and determine whether processing of a signal supplied from an external device has been instructed. When it is determined in step S1 that processing of the signal supplied from the external device is not instructed, the processor does not send out the switching command signal sB, and the output of the deinterleaving/interpolating circuit 10 is changed from the changeover switch 20 to The changeover command signal SA is selectively output (step S2), and the changeover command signal SA is not sent.
44.1KHz which is the output of the clock generation circuit 17 from
After selectively outputting clock pulses having the same wave number N times (step S3), execution of the routine that was being executed immediately before proceeding to step S1 is resumed.

When it is determined in step S1 that processing of a signal supplied from an external device is commanded, the processor sends a switching command signal sB, and the output of the clock extraction/data separation circuit 21 is selected from the changeover switch 20. (step S4), and determines whether the sampling frequency of the signal supplied from the outside is 44.1 KHz based on the cycle of the demodulation clock signal output from the clock extraction/data separation circuit 21. Determination is made (step S5).

When it is determined in step S5 that the sampling frequency of the signal supplied from the outside is 44.1 KHz, the processor does not send out the switching command signal SA, and the output of the clock generation circuit 17 from the changeover switch 16 is 44.1 KHz. A clock pulse having a frequency N times .1 KHz is selectively outputted (step S6), and execution of the routine that was being executed immediately before proceeding to step S1 is restarted. When it is determined in step S5 that the sampling frequency of the signal supplied from the outside is not 44.1 KHz, the processor sends a switching command signal SA to cause the changeover switch 16 to output the 44.1 KHz signal from the clock generation circuit 17. A clock pulse with a frequency N times higher is selectively outputted (step S7), and execution of the routine that was being executed immediately before proceeding to step S1 is resumed.

If the processing of the signal supplied from the external device is not instructed in steps 81 to S3 in the above operation, the digital audio signal obtained by demodulating the EFM signal read from the disc l is The signal is supplied to the A conversion circuit 23 and converted into an analog audio signal. In addition, if processing of a signal supplied from an external device is instructed in steps S4 to S7, a digital audio signal separated from the biphase mark t= signal supplied from the external device is input to the input terminal IN. is supplied to the D/A conversion circuit 23 and converted into an analog audio signal.

Therefore, if high-precision circuits are used as the D/A conversion circuit 23 and LPFs 24 and 25, a high-quality analog audio signal can be extracted from the digital audio signal output from other equipment, and the D/A Exchange W23, LPF
This means that it can be used for the 24,25'frH effect. Furthermore, the D/A conversion circuit and LPF of the BS tuner can be removed, resulting in an inexpensive device. Also, DAT
When the number of bits of the D/A conversion circuit is set to about 8 to 12, LA
Since only the sound condition can be checked, manufacturing costs can be reduced by a day. Further, since the digital circuit section and the analog circuit section are separated, it is possible to reduce noise.

Although the case of a digital audio disc player has been described above, the present invention can also be applied to other digital audio signal processing devices such as a DAT or BS tuner.

Effects of the Invention As detailed above, in the digital audio signal processing device according to the present invention, the digital audio input terminal and the output of the demodulating means for demodulating the transmission signal carrying the digital audio signal to obtain the digital audio signal. and signal selection means for selectively outputting one of the signals supplied to the digital audio input terminal in accordance with a command, and the output of the signal selection means is supplied to the digital/analog conversion means. There is.

Therefore, in the digital audio signal processing device according to the present invention, the digital audio signal output from the external device can be fed to the digital/analog converting means, and the digital/analog converting means is a highly accurate circuit. When this is used, an analog audio signal with good characteristics is provided, and the digital-to-analog conversion means can be used to high effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a flowchart showing the operation of a processor in the device shown in FIG. Explanation of symbols of main parts 7... System controller 16.20... Changeover switch 21... Clock extraction data separation circuit 23...
...D/A switching circuit applicant Pioneer Corporation

Claims (1)

[Claims] a demodulating means for demodulating a transmission signal carrying a digital audio signal to obtain a digital audio signal; a digital audio input terminal; and an output of the demodulating means and a signal supplied to the digital audio input terminal. A digital audio signal processing device comprising: signal selection means for selectively outputting one of the signals according to a command; and digital-to-analog conversion means for converting the output of the signal selection means into an analog audio signal.