JPH02235296A - Mos type output buffer circuit - Google Patents

Abstract

PURPOSE:To set up an output voltage to an intermediate potential level, to execute rapid operation and to reduce power supply noise by turning on and off an output PMOS and an output NMOS to be controlled by a prescribed voltage. CONSTITUTION:The MOS type output buffer circuit is provided with the NMOS 48 connected between the gate of an output PMOS 50 and an output terminal 52 and controlled so as to be turned on and off by voltage (Vr+Vtn) (provided that the Vr is the intermediate voltage between the 1st and 2nd power supply voltages and the Vtn is the threshold voltage of the NMOS) and the PMOS 49 connected between an output terminal 52 and the gate of an output NMOS 51 and controlled so as to be turned on and off by voltage (Vr-Vtp) (provided that the Vtp is the threshold voltage of the PMOS). In addition, the 1st MOS transistor (TR) 46 and the 2nd MOS TR 47 respectively connected between the power supply voltage and the gate of the output PMOS 50 and between the gate of the output NMOS 51 and the 2nd power supply voltage are provided. Thereby, by complementary turning on and off the output PMOS 50 and the output NMOS 51, the output terminal 52 can be set up to the intermediate potential. Consequently, the generation of power supply noise can be prevented while maintaining high rapidly.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a MOS output buffer circuit provided on the output side of a semiconductor memory such as a ROM (read only memory), a microcomputer, a semiconductor device, etc. It is.

(Prior art) Conventionally, as a technology in this field, Japanese Patent Application Laid-Open No. 56-5
There was one described in Publication No. 8190. The configuration will be explained below using figures.

FIG. 2 is a block diagram showing a main part of a conventional MOS type output buffer circuit.

This MOS type output buffer circuit is provided on the output side of the semiconductor memory, and includes an inverter 1.2 for inverting data read from a memory cell array (not shown).
A final output stage P-channel MOS transistor (hereinafter referred to as PMOS) 3 is connected to the output side of the inverters 1 and 2.
and N-channel type MOS transistor (hereinafter referred to as PMOS
4 gates are connected to each other. PM
The OS3 and the NMOS4 are connected in series between the power supply voltage Vdd, which is the first power supply voltage, and the ground potential Vss, which is the second power supply voltage, and the connection point between the PMOS3 and the NMOS4 is connected to the output terminal 5. There is. A load capacitor CO is connected to this output terminal 5.

Further, a precharge circuit is connected to the output side of the inverter 1.2 for setting the output terminal 5 to an intermediate potential (eg, Vdd/2>) in advance.

This precharge circuit is composed of an inverter 6 that inverts the predicted pulse Si generated when an address changes, an NMOS 7 that turns on and off depending on the output of the inverter 6, and a PMOS 8 that turns on and off depending on the predicted pulse Si. ing.

Next, the operation will be explained.

When reading data from a memory cell array (not shown),
A decoder (not shown) decodes the address to select a memory cell, and data stored in the selected memory cell is amplified by a sense amplifier (not shown).

Here, while the inside of the memory is operating, such as the time for decoding and the time for amplifying data by a sense amplifier, a detection circuit (not shown) uses a signal that detects a change in the address to generate a predicted pulse. Generates Si. Then, with this predicted pulse Si, N
MOS7 and PMOS8 turn on, thereby PMO
S3 and NMOS4 are turned on simultaneously, and the output terminal 5 is set to the intermediate potential Vss/2.

After that, when the read data amplified by a sense amplifier (not shown) is supplied to the circuit shown in FIG.
MOS8 turns off, then PM via inverter 1.2
Either OS3 or NIVIOS4 is turned on,
By turning off the other side, the high level (hereinafter referred to as 11 }
1 ++) is the Vdd level, and the low level (hereinafter referred to as ''
Continuous data whose output (referred to as "L") is at the Vss level is output from the output terminal 5, and the load capacitance CO is charged and discharged.

In this type of MOS type output buffer circuit, when outputting read data from the output terminal 5, the output terminal 5 is precharged to an intermediate potential Vdd/2 by a prediction pulse Si, and then the output terminal 5 is output from the output terminal 5 to the Vdd level. and V
Since the 1-off data at the ss level is output, the output operation time is approximately 1/2 that of inverting the read data from the Vdd level or VsS level state.
High-speed operation becomes possible.

(Problems to be Solved by the Invention) However, the circuit with the above configuration has the following problems.

As the degree of integration of semiconductor integrated circuits improves, MOS
The gate length of transistors is becoming shorter and the conductance is becoming larger. Although it has become possible to simply increase the drive capacity of the transistor in the MOS output buffer circuit and increase the speed, the current required when rapidly charging or discharging the load capacitance Co connected to the output terminal 5 As a result, the generation of noise at the Vdd level and Vss level, which is the power supply inside semiconductor memory, has become a problem.In particular, in large capacity semiconductor memory, there are many output terminals 5, and these output terminals If signals are simultaneously output from 5, large power supply noise will occur.

In the conventional MOS type output buffer circuit, the output terminal 5 is precharged to an intermediate potential Vdd/2 and the signal is output from the output terminal 5, so that the signal propagation speed can be increased. .

However, when setting the output terminal 5 to the intermediate potential Vdd/2, both PMOS3 and NMOS4 are turned on momentarily, so during this time, the power supply voltage Vdd is changed to PMOS3.
A large through current flows to the ground potential Vss through the NMOS 4 and the NMOS 4, and power supply noise is generated. For this reason, semiconductor memory, etc., where power supply noise as mentioned above is a problem,
If the circuit shown in FIG. 2 was provided, there was a risk that the device would malfunction due to large power supply noise.

The present invention provides a MOS type output buffer circuit that solves the problem of the prior art, which is that it is difficult to prevent power supply noise while maintaining high speed.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides an output PMOS connected between a first power supply voltage and an output terminal and controlled on and off by a gate voltage; In the MOS type output buffer circuit, the output NMOS is connected between two power supply voltages and is controlled on and off by a gate voltage, and the output NMOS is connected between the gate of the output PMOS and the output terminal, and has a voltage (Vr+Vtn). (However, Vr is the intermediate voltage between the first and second power supply voltages, and Vtn is the threshold voltage of the NMOS.) between the NMOS, which is controlled on and off, and the output terminal and the gate of the output NMOS. connected to the voltage (Vr-Vtp) (where vLp is PMO
(Threshold voltage of S). PMO controlled off
S, a first MOS transistor connected between the first power supply voltage and the gate of the output PMOS, and a second MOS transistor connected between the gate of the output NMOS and the second power supply voltage. MOS transistors are provided.

(Function) According to the present invention, since the MOS type output buffer circuit is configured as described above, the NMOS and PMOS are connected to the output PM.
By turning on and off the OS and the output NMOS in a complementary manner, the output terminal is set to an intermediate potential. After that, N
The MOS and PMOS are turned off, and the output voltage is output from the output terminal by the on/off operations of the output PMOS and output NMOS. Therefore, the above problem can be solved.

(Embodiment) Fig. 1 is a circuit diagram of a MOS type output buffer circuit showing an embodiment of the present invention, Fig. 3 is a schematic configuration diagram of a semiconductor memory incorporating the circuit of Fig. 1, and Fig. 4 is a diagram of a semiconductor memory incorporating the circuit of Fig. 3. FIG.

First, to explain the semiconductor memory shown in FIG. 3, this semiconductor memory includes an address buffer 10 for inputting an address AD, and the address buffer 10 includes a row decoder 11 and a column decoder 12 for decoding the address, and a row decoder 11 and a column decoder 12 for decoding addresses. An address change detection circuit 13 that generates a predicted pulse 813 is connected. The address change detection circuit 13 has an output enable signal OE activated by the negative phase output enable signal στ and based on the prediction pulse SL3, etc.
and an output control circuit 1 that outputs control signals A, B, C, and D.
4 are connected.

A memory cell matrix 15 in which a large number of memory cells are arranged in a matrix is connected to the row decoder 11, and a MOS type output buffer circuit 18 is connected to the memory cell matrix 15 via a multiplexer 16 and a sense amplifier 17. ing. The multiplexer 16 is a circuit that performs signal selection operation based on the output of the column decoder 12, and the sense amplifier 17 selects the signal from the multiplexer 15 using the predicted pulse 813.
This is a circuit that amplifies the output of and outputs read data DAI. Further, the MOS type output buffer circuit 18 is activated by the output enable signal OE, and the control signals A, B,
This circuit drives read data DA1 based on C and D and outputs it in the form of data DA2.

In this semiconductor memory, when address AD is input,
An address on the memory cell matrix 15 is selected by the address buffer 10, row decoder 11, and column decoder 12. The memory cell data of the selected address is read by the sense amplifier 17 via the multiplexer 16, and the read data DAI is driven by the MOS type output buffer circuit 18 and outputted to the outside in the form of data DA2.

As shown in FIG. 4, in the output control circuit 14 in this semiconductor memory, a PMOS 20 for a minute current source to which a control signal E is applied to the gate is connected to a power supply voltage Vdd, which is a first power supply voltage, and a node N1. connected between. The node N1 is connected to the node N2 via NMOS21 and 22 whose gates and drains are commonly connected and diode-coupled.
It is connected to the. The intermediate potential Vr on the node N2 is connected to the ground potential Vss, which is the second power supply voltage, through PMOSs 23 and 24 whose gates and trains are commonly connected and diode-coupled. Between the power supply voltage Vdd and the node N3 for outputting the control signal A, there is a PMOS 25 whose gate is connected to the control signal E, and a PMOS 25 whose gate is connected to the node N1.
The NM0826 connected to the NM0826 is connected in series.

The PMOS 25 and the NMOS 26 constitute a drive circuit on the II H II side of the control signal A.

An NMOS 27 whose gate is connected to the control signal E is connected between the node N3 and the ground potential Vss, and its PM
The gate of OS27 is connected to PMOS via inverter 28.
29 and the gate of NMOS31. NMOS27 is a transistor that drives node N3 to ground potential Vss. PMOS29 is connected between power supply voltage Vdd and node N4 for outputting control signal B, and node N4 is connected to ground potential Vss via PMOS30 and NMOS31. PMOS29
is a transistor that drives node N4 to power supply voltage Vdd. The PMOS 30 and the NMOS 31 constitute a drive circuit on the II LIT side of the control signal B.

Furthermore, constant current sources 32 and 33 for stabilizing the levels of control signals A and B are connected to nodes N3 and N4, respectively.

Although not shown in FIG. 4, the output control circuit 14 in FIG. 3 is also provided with a circuit for generating control signals C, D, and E.

The MOS output buffer circuit 18 controlled by the output control circuit 14 includes a tri-state inverter 40, as shown in FIG. The tri-state inverter 40 converts the data DAI output from the sense amplifier 17 when the output enable signal OE is "H'°".
This circuit inverts and outputs the signal, and when the output enable signal OE is "LIT", the output becomes a high impedance state, and is composed of a two-man power NAND gate 41, an inverter 42, and a two-man power NOR gate 43. The output side of the NAND gate 41 is turned on by control signals C and D. The output side of the NOR gate 43 is connected to the node Nil via the CMOS type transfer gate 44 which is turned off, and the output side of the NOR gate 43 is turned on and off by the control signals C and D. CMOS operating off
It is connected to node N12 via a type transfer gate 45. The node Nil is connected to the power supply voltage Vdd via a PMOS 46 for a micro current source, which is a first MOS transistor whose gate is connected to the control signal B, and the node N12 is connected to the control signal A at its gate. NMO for minute current source which is the second MOS transistor
It is connected to the ground potential Vss via S47.

An NMOS 48 whose gate is connected to the control signal A is connected between the node Nil and the output terminal 52, and a PMOS 49 whose gate is connected to the control signal B is connected between the output terminal 52 and the node N12. has been done. The output PMOS50 and the output NMO are connected to the nodes Nil and N12.
Each gate of S51 is connected respectively, and its output PMO
S50 and output N. IVIOS 51 is connected in series between power supply voltage Vdd and ground potential Vss. Output P
The MOS 50 is a drive transistor on the "H" side of the output terminal 52, and the output NMOS 51 is a drive 1 transistor on the "Lll" side of the output terminal 52. A load capacitor Co is connected to the output terminal 52.

Next, the operations shown in FIGS. 1 and 4 will be explained.

The following table is a mode table for explaining the circuit operations of FIGS. 1 and 4.

Mode table (1) High impedance mode In the semiconductor memory shown in Fig. 3, when the read operation is prohibited, the negative phase output enable signal becomes “H゛゜”.
Output enable signal O output from the output control circuit 14
Of E and control signals A, B, and CD, OE is “H”, A
．． C becomes the Vss level, and B and D become the Vdd level. That is, in FIG. 4, when the control signal E becomes ll H I1, the NMOS 27 is turned on and the control signal A becomes the Vss level, and the PMOS 29 is turned on through the inverter 28, so that the control signal B becomes the Vdd level. Signal O
When signals E, A, and C reach the Vss level and signals B and D reach the Vdd level, the output of the tristate buffer 40 in FIG.
4.45 is on, NMOS48, 51 and PMOS4
9.50 becomes the off state and enters the high impedance mode.

(2) Vr output mode When performing a read operation in the semiconductor memory shown in FIG. M via the control circuit 14
The OS type output buffer circuit 18 enters the Vr output mode.

In this Vr output mode, the output terminal 52 in FIG.
An intermediate potential V that is an intermediate level between the d level and the Vss level
This is the mode for setting to r.

In this Vr output mode, in the output control circuit 14 of FIG. 3, the control signal C is at the Vdd level, and the control signals E and D are at the Vss level. When the control signal E reaches the Vss level, the output control circuit 14 of FIG. 4 sets the NMOS threshold value to Vtn. When the threshold value of the PMOS is Vtp, the control signal A is at the (Vr+Vtn) level, and the control signal B is at the (Vr-vtp) level. That is, if the current flowing through the PMOS 20 is set sufficiently small, the intermediate potential Vr can be reduced to N
When the potential of the node N2 between MOS22 and PMOS23 is taken as the value of the intermediate potential Vr, as shown in the following equation, the value of the PMOS
This is the value obtained by adding the threshold value Vpt of S23.24.

Vr=2Vtp Furthermore, the voltage ■ at the gate side node N1 of the NMOS21.

1 becomes V nl ” V r + 2 V t n.N
A voltage V is applied to the gate of MOS26. 1 is applied, so
The voltage of the control signal A is Vnl-vtn=Vr+Vtn. Furthermore, the gate of the PMOS 30 has a ground potential Vs.
s is connected, the voltage of the control signal B becomes Vtp=Vr-Vtp.

Control signals C (=Vdd), D (=Vss)
, A (=Vr+Vtn), B (=Vr-Vtp) are supplied to the IVIOs type output buffer circuit 18 in FIG. works like this:

For example, if the power supply voltage Vdd is set to 5V and the output terminal 52
PM when changing the output voltage of 0 from OV to 5V
OS50 and N] VIOS51 gate voltage Vp, Vn and current Ip flowing between the source and drain,
In is shown in FIG. 5 and FIG. 6, respectively.

5 and 6, the output voltage Vo is the intermediate potential V
When lower than r, NMOS48 is on, PMOS4
9 is in the off state, Vp-:Vo, Vn:OV, and a current Ip that attempts to raise the output voltage 0 to the intermediate potential Vr flows through the PMOS 50. When the output voltage ■0 is higher than the intermediate potential Vr, PMOS49 is in the on state, N
Since the MOS 48 is turned off, Vn:Vo, Vp::Vdd, and a current In that attempts to lower the output voltage VO to the intermediate potential Vr flows through the NMOS 51. Then, it becomes stable when Vo=Vr, and PMOS50 and NIVI
Both OSs 51 are turned off. In this way, the predicted pulse 813 causes the output voltage Vo of the output terminal 52 to rise to Vdd.
It is set to an intermediate potential Vr between the level and the Vss level.

(3) ″゜H′゜Output, IIL″゜Output mode After the Vr output mode has passed, the output enable signal OE output from the output control circuit 14 is at the Vdd level, and the control signals B and D are at the Vdd level.
dd level and the control signals A and C reach the Vss level, in the MOS type output buffer circuit of FIG.
Then, NMOS 47 and 48 are turned off. Then, successive data DAI output from the sense amplifier 17 is Vd
For d level, it is tri-state inverter 4
0 and its output causes the transfer gate 44
．． 45, the nodes N11 and N12 go to the Vss level, the PMOS 50 is turned on and the NMOS 51 is turned off, and the output terminal 52 outputs the output voltage Vo at the Vdd level, that is, the read data DA2. Further, when the read data DA1 is at the Vss level, the read data DA2 at the same phase level is outputted from the output terminal 52. In this way, in the "H" output mode and "L" output mode, the one-off data DA2 having the same phase level as the read data DAI is output from the output terminal 52.

This embodiment has the following advantages.

Conventionally, in a semiconductor memory, for example, when the number of output terminals 52 increases and high speed is required, when a large number of output terminals 52 output data DA2 at the same time, all the output terminals connected to the output terminals 52 The transient large current for charging or discharging the load capacitance CO generates power supply noise, which may cause the semiconductor memory to malfunction.

However, in this embodiment, the PMOS 50 and the NMOS 51 are set in advance by the prediction pulse 313 before data output.
By turning on one and turning off the other without turning both on, the output terminal 52 can be set to the Vdd level and Vs.
It is set to the intermediate potential Vr of the s level. At this time, P]
Since VIOS50 and NMO851 are not turned on at the same time, the power supply voltage Vdd and ground potential Vss are connected through them.
No through current flows between the two and the generation of power supply noise is suppressed. After setting the output terminal 52 to the intermediate potential Vr, the promotional data DAI from the sense amplifier 17 is driven by the tri-state buffer 40, PMOS 50, and NMOS 51 to charge and discharge the load capacitor i1co, so that the amount of charging and discharging current is reduced to 1/1. 2, suppressing the generation of power supply noise,
Enables high-speed access.

Note that the present invention is not limited to the above embodiments, and various modifications are possible. Examples of such modifications include the following.

(a) In FIG. 4, the intermediate potential Vr on the node N2 is 2Vtp, but this value can be set arbitrarily between the Vdd level and the Vss level.

An example of setting Vr>2VtP is shown in FIG.

FIG. 7 is a diagram showing a modification of FIG. 4. In this circuit, a node N4 is connected between the PMOS 30 and the NMOS 31, and an NMOS 34 for a minute current source is added between the PMOS 24 and the ground potential Vss. Furthermore, the reference potential V
r is applied to the node N2 via the differential amplifier 35. In this way, a reference potential Vr larger than 2Vp can be applied to the node N2, and as in FIG.
Control signal A (=Vr+Vtn) in r output mode
．． B (=Vr-Vtn) can be output.

(b) The tri-state inverter 40 in FIG.
It is possible to replace the PMOS 46 and N]VIOS 47 for a small current power supply with a tri-state buffer, or replace the PMOS 46 and VIOS 47 for a small current power supply with another first MOS such as a load MOS. It is also possible to replace it with a second MOS transistor. Furthermore, the power supply voltage Vdd and the ground potential V
ss may be replaced with other first and second power supply voltages.

(C) The present invention can also be applied to output circuits of semiconductor integrated circuits other than semiconductor memories.

(Effects of the Invention) As explained in detail above, according to the present invention, the voltage (V
r+Vtn), and the voltage (V
Since the output PMOS and output NMOS are turned on and off by a PMOS etc. controlled by r-Vtp, the output voltage is kept at an intermediate potential without turning on both the output PMOS and the output NMOS at the same time. Vr can be set, allowing high-speed operation and reducing power supply noise.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a MOS type output buffer circuit showing an embodiment of the present invention, Figure 2 is a circuit diagram of a conventional MOS type output buffer circuit, and Figure 3 is a circuit diagram of a semiconductor memory incorporating the circuit of Figure 1. 4 is a partial circuit diagram of the output control circuit in FIG. 3, FIGS. 5 and 6 are voltage and current characteristic diagrams in FIG. 1,
FIG. 7 is a circuit diagram showing a modification of FIG. 4. 14... Output control circuit, 18... MO
S-type output buffer circuit, 40... tri-state inverter, 44.45... transfer gate, 46, 49.50... PMOS, 47,
48.51...NMOS, A, B, C, D. E
...Control signal, 0E...Output enable signal, 813...Predicted pulse, Vo output voltage, Vdd...Power supply voltage, Vss...・Ground potential.

Claims (1)

[Scope of Claims] An output P-channel MOS transistor connected between a first power supply voltage and an output terminal and controlled on and off by a gate voltage, and an output P-channel MOS transistor connected between the output terminal and a second power supply voltage and controlled to turn on and off by a gate voltage In the MOS type output buffer circuit, the output N-channel type MOS transistor is connected between the gate of the output P-channel type MOS transistor and the output terminal, and the voltage (V
r+Vtn) (where Vr is an intermediate voltage between the first and second power supply voltages, and Vtn is a threshold voltage of the N-channel MOS transistor); It is connected between the terminal and the gate of the output N-channel type MOS transistor, and has a voltage (Vr-Vtp) (
However, Vtp is a P-channel MOS transistor whose on/off is controlled by the threshold voltage of the P-channel MOS transistor.
an OS transistor; a first MOS transistor connected between the first power supply voltage and the gate of the output P-channel MOS transistor; and a gate of the output N-channel MOS transistor and the second power supply voltage. A MOS type output buffer circuit comprising: a second MOS transistor connected between the MOS transistor and the second MOS transistor;