JPH0223393A - Matrix display device - Google Patents

Abstract

PURPOSE:To reduce the driving electric power by providing an 1H (one horizontal line) memory circuit for storing a transfer data signal, a comparing circuit which compares the transfer data signal with the output signal of the 1H memory circuit, and a 1H latch circuit which latches the output of the comparing circuit. CONSTITUTION:The comparing circuit compares an original data signal with a data signal which is 1H delayed by the memory circuit 14 to detect the inversion of the data signal of each 1H. The detection signal is led to the 1H latch circuit 17 composed of a D latch circuit and the output of the 1H latch circuit 17 is used as a control signal to control the logic signal of a data-side driver 5, thereby placing an output transistor (TR) in a push state. At the same time, modulation pulses are made into a direct current to minimize the discharge of a charged display element in a display panel 1. Consequently, the driving electric power is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a matrix display device of capacitive elements such as ELP (electro-μ-minescent spring) and FDP (plasma display).

Conventional technology An EL panel will be described as an example of a matrix display device using capacitive elements. FIG. 8 is a block diagram showing a conventional drive device for a thin film EL panel, FIG. 9 is an operating waveform diagram of the same drive device, and FIG. 10 is a conventional modulation drive power distribution diagram. In FIG. 8, a block diagram of a simultaneous inversion refresh driving method will be explained. The thin film EL panel 1 has data electrodes, ~
DM and scanning electrodes 81 to SN are orthogonal to each other in a matrix configuration, and a capacitive EL element CEL is interposed between both electrodes. This thin film EL panel 1 controls a data side driver 5 that supplies a modulation pulse VM to the data electrodes ~DM, and a scan side driver 8 that supplies a write pulse vw or a refresh pulse vR to the scan electrodes S and ~SN. The data is displayed.

The data side driver 6 includes a logic circuit 6 consisting of a shift register circuit, a latch circuit, a gate circuit, etc.
Similarly, the scanning side driver 8 is composed of a logic circuit 9 and a pull type transistor 10. Further, since the writing pulse VW and the refresh pulse vR are applied to the ground of the scanning side driver 8, it is necessary to keep the ground in a floating state. Therefore, a control signal to the logic circuit 9 is supplied via the photocoupler 4. The light emitting operation is performed as follows. During the line sequential scanning period, the scanning electrodes S, →SN are selected by the scanning side driver 8 in the order of every scanning period (hereinafter referred to as 1H), and a write pulse vw of negative polarity is supplied. On the other hand, in the data side driver 6, Data
The signal is taken in and all push-pull type output transistors 7
At the same time, a Data signal is sent to the data electrodes, and a modulation pulse VM is supplied to the data electrodes -DM in accordance with the Data signal.

For example, if the relationship between input and output in the data side driver 5 is set as shown in the following table, when the Data signal is H, the output will be vM, and when it is L, the output will be zero.

Therefore, the selected light emitting pixel voltage vEL1 is vEL,=”M+
vw-ii selection non-light emitting pixel voltage vEL2 is vEL2=■w
and gives a potential difference of vM between the two, which causes light emission,
Causes non-emission. After completing such line sequential scanning,
Refresh pulse vR (with opposite polarity to write pulse vw)
vR':2vw) is simultaneously applied to all the EL elements via the clamp diode of the pull-type transistor 10 of the scanning side driver 8, causing the light emitting pixels during line sequential scanning to emit light again and completing one frame.

The driving power in such a driving method will be explained with reference to the operating voltage waveform diagram in FIG. 9 and the modulated driving power distribution diagram in FIG. 10. Since the modulated drive power has the largest proportion of the total drive power, the modulated drive power will be described here. Let the number of data electrodes be M and the number of scan electrodes be N. When the number of selected picture elements (emitting light) in the selected scanning electrode line is m, the modulation voltage V charged to the EL element CEL on the data electrode line is
- is an EL element on the light-emitting pixel data electrode.

= (M-m)・VM, EL on non-light-emitting pixel data electrode
The element is 7m2"-yl" vM. Since the driving power P of the capacitive load is P cc CV2, the total modulation driving power P0 in this case is P. tx-m-1--C0vM.

However, C0 is the capacitance of one display element. Therefore, the modulation drive power distribution with respect to the number of light-emitting pixels becomes a bilaterally symmetrical convex distribution in which the maximum drive power is reached when the light emission rate is 50%, as shown in FIG. FIG. 9 shows the control signal of the data side driver 6 and the modulation pulse applied to the display panel when the luminous efficiency is 6 degrees. Display element voltage vm1 on the selected data electrode line. Display element voltage vm on non-selected data electrode line
2 changes depending on the luminous rate a, -vrnl as clothing cost
``-''vMevm2=-avM. Problems to be Solved by the Transfer Invention However, in the above drive circuit configuration, the Data signal to the push-pull transistor 7 is controlled by the ENB signal, and a portion of 1H In order to discharge the write pulse (hatched), an L period is provided to cause forced discharge. Therefore, regardless of whether the display element emits light or not, the charge charged in the display element is always discharged within 1H, resulting in a problem in that a large amount of wasted driving power is consumed.

In view of this point, it is an object of the present invention to provide a matrix display device with low driving power.

Means for Solving the Problems The present invention provides a 1H memory circuit that stores a transfer data signal, a comparison circuit that compares the transfer data signal and the 1H memory circuit output signal, and a 1H latch that latches the output of the comparison circuit. This is a matrix display device characterized by having 1,000 circuits.

The comparison circuit compares the original data signal and the data signal delayed by 1H in the memory circuit, and detects the inversion of the data signal every 1H. The detection signal is guided to a 1H latch circuit using a D latch circuit, and the output of the 1H latch circuit is used as a control signal to control the logic signal of the data side driver to put the output transistor in a bush state and convert the modulation pulse to DC. , driving power is reduced by suppressing the discharge of charges stored in display elements in the display panel to the necessary minimum.

Embodiment FIG. 1 shows a control system diagram of a matrix display device in an embodiment of the present invention.

In FIG. 1, 14 is a 1H memory circuit that stores 1H of the transferred data signal, 16 is a comparison circuit that synchronously compares the original Data signal and the output signal of the 1H memory circuit 14, and 16 is the comparison circuit. A weighting circuit 17 weights the output signal of 1, and 17 holds the comparison output for 1H.
The H circuit 18 is a driver control circuit that ultimately controls the data side driver 8. The operation of this embodiment configured as above will be described below. Note that the role of the weighting circuit 16 will be described later. First 1H
Data electrode for 1H in memory circuit 14.

The input and output signals of the 1H memory circuit 14 are synchronized by writing and reading M transfer ata signals corresponding to ~DM using the same address signal (not shown). Therefore, the output signal becomes a Data signal delayed by 1H with respect to the original Data signal. The comparator circuit 16 compares this delayed Data signal with the original signal, and determines, for example, if they have the same polarity (display data content is 1H).
When the polarity is reversed (the display data contents are inverted within 1H), the output is set to H. The comparison output is a signal held in the 1H Cucci circuit 17 for 1H, and is supplied to the driver system control circuit 18, and the data side driver 6
The logic system control signals and modulated pulse voltage generation circuit (not shown) are controlled.

A time delay between 1H occurs in the signal processing from this 1H memory circuit 14 to the driver system control circuit 18.
Since the logic circuit system of the data side driver 5 has a built-in 1H latch circuit to hold the Data signal, the response to the push-pull transistor similarly operates with a delay of 1H. Therefore, it is basically synchronized with the control signal of the driver system control circuit 18.

The control signal from the driver control circuit 18 is controlled by the display spring /L during the scanning period when the Data signal is inverted for 1H.
'1 data side driver 6
so that the Data signal is discharged every H,
When it is continuous, it becomes L, so by controlling the data side driver 6 and the modulation pulse voltage generation circuit so as to eliminate the discharge loop, unnecessary discharge of the charge charged in the display element is suppressed. This reduces driving power.

Note that the 1H memory circuit 14 may be replaced by a 1H delay circuit if synchronization can be achieved.

By the way, regarding the operation of the 1H memory circuit 14, there is no problem with the original Data signal, which is the input signal to the comparator circuit 160, as processing information of the Data signal during the first line sequential scanning of the scanning electrodes. As for the output signal, a Data signal from the last scan of one frame before or an undefined signal is sent. This signal is basically the original D
Since this signal has no correlation with the ata signal, in this state, the comparator circuit 16 assumes that most of the ata signals transferred during this period are inverted and outputs a false signal. In order to prevent this, the operation of the comparison circuit 16 during the first line sequential scanning is forcibly stopped by using the horizontal synchronization signal I'(,D) of which the timing is shifted for the comparison circuit 16 as an inhibit signal.

FIG. 2 shows a specific example A, and FIG. 3 shows its operating voltage waveform diagram. Modulation pulse V. 1, a DC voltage vM is applied. The comparison circuit 16 is composed of an EXC and OR circuit 19, and appears as an H output only when the Data signal is inverted within 1H. This output is made into a signal held for 1H by the 1H latch circuit 17, and the Q signal is added to the ENB signal, which is the logic signal of the data side driver 6, by the OR circuit 21. EXC while the Data signal continues every H.

Since the output of the OR circuit 19 is L, the 1H latch circuit 17
The Q output of is H and the ENB signal is always H.
NB' times the signal.

As mentioned above, the push-pull transistor 70ENB
The operation for the signal is determined by the Data signal when it is H, and the D
When the ata signal is H, the bush stage is turned on, when the Data signal is L, the pull stage is turned on, and when the ENB signal is L, the pull stage is forcibly turned on.
When the signal is continuous, the bushing stage is always on, so a DC voltage vM is applied to the data electrode as a modulation pulse voltage. As a result, as shown in FIG.
n2 vM) is the modulation voltage V applied to the selected data electrode.
M is balanced, the discharge loop of the charge of the display element is blocked, and the charge is preserved. By such an operation, as long as the Data signal is continuous, charging and discharging are not performed, so the driving power can be reduced significantly.

FIG. 6 shows a specific embodiment B, and the difference from FIG. 3 is that the control signal from the 1H reset circuit 17 is controlled by the modulated puffless voltage generation circuit 29. Data side Dohino <6 E
The NB signal is always H, and the push-pull transistor 7
The operation is turned on and off only by the Data signal. The modulated pulse voltage generation circuit 29 includes a DC power supply vM, a modulated pulse transistor 23, a capacitor 24, a diode 26, a transistor 26, and a vrn control circuit 22.

Normally, the modulation pulse transistor 23 generates a modulation pulse (2) synchronized with the ENB signal in the conventional example. The modulation pulse is grounded by the capacitor 24 and the diode 26, but since the diode 24 only charges the capacitor 24, the modulation pulse vm remains in a pulse form and is not converted into a direct current.

On the other hand, when the Da ta signal is continuous for every H, the output of the KXC and OR circuit 19 of the comparator circuit becomes L, so the Q output of the 1H latch circuit 17 becomes H, and the Q output is v!
! 1 control circuit 22 and turns on transistor 26. By using a PNP type transistor 26, it works to flow the discharge current of the capacitor 24 from the ground to the capacitor 24, so the capacitor 24 is basically grounded, and the modulation pulse vm is smoothed and becomes a direct current. A voltage of 7M is applied to the data side driver, and the same operation as in the embodiment of FIG. 2 is performed. Also, when the Data signal is inverted, the normal modulation noise v! n is applied, and the charge of the display element is modulated AIVsV.

During the zero level period, a discharge loop is created between the ground and the modulated pulse voltage generation circuit 29 via the clamp diode 2 constituted by the push-pull transistor 7, and discharge occurs. With such a driving method, Da
When the ta signal is inverted for 1H, the conventional drive mode is operated, and when the Data signal is continuous for 1H or more, the low power drive mode is operated. Figure 6 shows the luminescence rate a on one line.
Alternatively, it is a modulation drive power distribution diagram with respect to the Data signal inversion rate ρ during 1H. Here, Po is the conventional driving method, PN1 to P
N3 indicates the driving power in the new driving method.

Here p. oc a (1-a) VM, PNI
oc sliding ρ(1-ρ)7M2. However, PN1 is when the Data signal is inverted every 1H. PN2 is when the D signal is inverted every 2H.
In the case of ata signal inversion (PN2=PN, /2), PN3
is when the Data signal is inverted every 3H (PN3=PN, /
3), and the driving power decreases in inverse proportion to the inversion period of the Data signal. In this embodiment, when the Data signal is inverted every 1H, the conventional drive mode is entered, so the PN1 state is not entered.

With this drive mode, low drive power of P0 to PNn (Po>PNn, PNn=PN1/n, where n≧2, n: Data signal inversion period) can be realized depending on the inversion period of the Data signal. By the way, when considering the drive power for every 1H, for example, when the first line is in the maximum drive power state of 60% light emission, and the Data signal on the second line changes only at one point, the light emission rate a at this time is ≦60%),
During this period, the operation mode is the conventional driving method, so P. The driving power is (50). However, even if 1H
Even if there is an inversion of the Data signal every time, if the inversion rate ρ of the Data signal is low, it is possible to satisfy PN, ≦P0 (6°). In Figure 6, the Data signal inversion rate ρ
When the drive power PN1 (1)) in the new drive method during engineering is the maximum drive power in the conventional drive method, the luminous rate a = 5
The Data data signal inversion rate ρ is 26 degrees, which is the same as Po (5 degrees) of 0 degrees. From this, even if there is an inversion of the Data signal every 1H, at least as long as the inversion rate ρ is approximately 215% or less, it is possible to drive with lower power by assuming that the Data signal is continuous. . The weighting circuit 16 shown in FIG. 1 detects the inversion rate ρ.

This weighting circuit 16 is connected between the comparison circuit 15 and the 1H clutch path 17, and even if an output signal of a Data signal change is sent from the comparison circuit 15, the reversal rate ρ is about 25%.
The output of the weighting circuit 16 remains at L unless the value exceeds 1, and the output of the weighting circuit 16 is operated in the low power drive mode described above as if a continuous Data signal were being sent.

This weighting circuit 16 is realized by a counter circuit, an AND gate circuit, or the like.

FIGS. 7(a) and 7(b) show examples of the weighting circuit 16 for high-speed transfer of ata signals. First, (a) will be explained. The data signal transferred at high speed is separated into n bits by the serial/parallel conversion circuit 27, and the transfer period is reduced to 1.
to reduce the transfer speed.

1H memory circuit 14 for each bit. The processing circuit of the comparison circuit 16 detects the inversion of the Data signal during 1H with respect to the n-bit transferred ata signal. Thereafter, the n-bit information is returned to the original high-speed transfer cycle via the parallel-to-serial conversion circuit 28. Therefore, the parallel-to-serial conversion circuit 28 sequentially outputs only the signal components inverted during 1H in the original data signal transferred at high speed. By guiding this output signal to the counter circuit 16A and setting the output of the counter circuit 16A to a count number such that the inversion rate is approximately 26,
Weighting can be applied to the inversion of the Data signal.

Similarly, (b) shows A for the n-bit output of the comparison circuit 15.
It is weighted by receiving it in a multiplication circuit such as an ND gate circuit 1eB, and if it is an n-bit gate input, the inversion rate ρ of the Data signal is weighted at 1×10%. In this way, arbitrary weighting can be performed depending on the count number of the counter circuit and the number of input gates of the multiplication circuit.

In this embodiment, a simultaneous inversion refresh driving method using a thin film EL (fabric panel) was described as an example, but a simple frame inversion driving method in which positive or negative polarity writing is performed for each frame (line sequential scanning is performed with a pulse) can also be used. In addition, regarding the so-called PN frame inversion driving method in which the polarity of the write pulse is inverted every 1H in line sequential scanning and is also inverted every frame, the data side driver's Data Since the input signal must also be inverted, the comparison circuit 16 uses the original data shown in the embodiment.
A similar effect can be obtained by detecting the continuity of the original data signal and using it as a control signal instead of detecting the inversion of the signal. Furthermore, although the present embodiment has been described using a thin film EL display device as an example, the present invention is not limited to this, and it goes without saying that the present invention is effective for any matrix display device using PoP equivalent capacitive display elements.

As described in detail, according to the present invention, the continuity of the original data signal processed by the 1H memory circuit and the comparator circuit is detected, and the data-side driver system is controlled using the weighted control signal. This makes it possible to control the discharge loop by making the charge stored in the display element correspond to changes in the data signal, thereby reducing driving power.

[Brief explanation of the drawing]

Fig. 1 is a control system block diagram of a matrix display device according to an embodiment of the present invention, Fig. 2 is a first specific circuit diagram of the same embodiment, Fig. 3 is its operating voltage waveform diagram, and Fig. 4 is a continuous Relationship diagram between modulation voltage and display element voltage during data signal, No. 6
The figure is a second specific circuit diagram of the same embodiment, FIG. 6 is a modulation drive power distribution diagram in the same embodiment, and FIGS. 7(a) and (b)
) is a block diagram of a different embodiment of the weighting circuit in the same embodiment, FIG. 8 is a drive system block diagram of a conventional thin film EL display device, FIG. 9 is an operating voltage waveform diagram thereof, and FIG. 10 is a diagram of a conventional thin film EL display device. FIG. 3 is a modulation drive power distribution diagram. 1... Display spring ~, 6... Data side driver, 14... 1H memory circuit, 16...
... Comparison circuit, 16 ... Weighting circuit, 1
7...1H clutch path, 18...Driver system control circuit. Name of agent: Patent attorney Shigetaka Awano and 1 other person Figure / IH Yami no Ki IA reversal with Rai 5? Figure Figure Figure 1 Figure 1 Light-emitting rod a on the line

Claims (4)

[Claims] (1) When driving a display panel in which data electrodes and scanning electrodes are arranged orthogonally and a capacitive display element is interposed between both electrodes, a memory circuit that stores and holds data signals for one scanning period, and a memory circuit that stores and holds data signals for one scanning period; A comparison circuit that compares the output of the memory circuit delayed by one scanning period, and a latch circuit that stores and holds the output of the comparison circuit that detects a change in the data signal between before and after one scanning period for the scanning period. A matrix display device characterized in that a data-side driver system is controlled by a control signal processed by a processing circuit to discharge accumulated charges charged in the display element or interrupt a discharge loop for each scanning period. . (2) If the number of data signals for one scanning period is M, and the number of data signal inversions before and after one scanning period is m, then the data signal inversion rate ρ_m (ρ_m=(m/M)×100%) is p_m≦ 2. The matrix display device according to claim 1, further comprising a weighting circuit having a weighting coefficient of 25% connected between said comparison circuit and said latch circuit. (3) The matrix display device according to claim 2, wherein the weighting circuit is constituted by a counter circuit. (4) The matrix display device according to claim 2, wherein the weighting circuit is constituted by a multiplication circuit having a rubit input gate.