JPH022336B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an encoding device that compresses and encodes a sampled multi-level time series signal whose frequency of occurrence is biased.

Multi-value time-series signals obtained by sampling image signals and audio signals generally have a bias in the frequency of occurrence of each multi-value signal. Analog image and audio signals
In the PCM (pulse code modulation) signal obtained by D conversion, the deviation in the frequency of occurrence is not so large, but for example, the multilevel signal obtained by converting the PCM signal to the DPCM (differential pulse code modulation) signal is ,
In general, it shows a frequency distribution of zero concentration type. That is, signals with a difference value close to 0 occur frequently, and signals with a large difference value occur less frequently. Signals with uneven occurrence frequency can be compressed and encoded by unequal length coding in which short codes are given to signals with high occurrence frequency and long codes are given to signals with low occurrence frequency. This type of unequal length encoding is performed on a sampled multi-level difference (sample value sequence) time series signal by applying predetermined unequal lengths at each sampling time according to the difference signal at that time. This is a method of giving a sign.

In this case, a code of at least 1 bit is required even for the most frequently occurring difference value. However, between frames for image signals such as television, etc.
In DPCM encoding, etc., the probability of occurrence of a signal with a difference value of 0 is usually 90% or more, and it is inefficient to give a 1-bit code to a signal with a difference of 0. Therefore, for signals with large deviations in frequency of occurrence, the time-series signal is grouped into blocks of, for example, 8 sample values, and all 8 code values included in each block are the signals with the highest frequency of occurrence. (hereinafter referred to as the most frequently occurring signal value), attempts have been made to improve compression efficiency by providing a special block code to indicate this value, but the complexity of the device configuration However, the disadvantage is that the compression efficiency does not improve.

Another problem with compression encoding is that the circuit configuration for realizing unequal length encoding and unequal length decoding becomes complicated. In particular, when the sampling frequency of a sampled multilevel time series signal is as high as 10KHz, such as a television signal, there is a limit to the operation of code conversion for unequal length encoding, so serial arithmetic processing is applied. This makes the circuit even more complex.

An object of the present invention is to provide an encoding device that efficiently compresses and encodes a multivalued time-series signal with a large deviation in frequency of occurrence as described above with a simple circuit configuration.

The encoding device of the present invention divides at least one multilevel time series signal into blocks in time series and compresses and encodes each block, comprising means for generating a synchronization code indicating the division of the blocks; means for generating a first code representing the duration of a predetermined signal value in the multilevel time series signal;
a second signal representing each value of the multivalued time series signal;
means for time-division multiplexing the synchronization code and the first and second codes onto a parallel m (m≧2) bit data line; and a valid (invalid) code on the parallel data line. means for generating a display signal representing the number of bits of the parallel m-bit data line; and a means for generating a parallel l(1 It is characterized by comprising means for outputting the above-mentioned arbitrary integer) bits onto the data line.

The first feature of the present invention is that among multi-level time series signals, the most frequently occurring signal value is encoded with unequal length encoding, so the number of codes per sample value can be reduced to 1 bit or less. , two types of codes R and V are defined to indicate transitions, so even if the most frequently occurring signal value and other signal values are mixed in the time series, they can be easily distinguished. It is possible. This feature makes it possible to realize encoding with high compression efficiency. The second feature is that R and V codes to which synchronization codes and unequal-length codes are assigned, as well as other codes (for example, mode codes, voice codes), are added to parallel m-bit data lines, including invalid codes, as necessary. The two methods are time-division multiplexed, and a common array conversion circuit is used to remove invalid codes from assigned codes. Generally, in unequal length encoding, it is easy to assign codes, but it is not easy to realize high-speed array conversion to remove invalid codes. The present invention takes advantage of the following characteristics: (1) R code and V code do not occur simultaneously in time, and (2) empty time occurs in code generation due to encoding of the duration of the most frequently occurring signal value. This facilitates time division multiplexing of multiple time series signals. In other words, the encoding logic and the features of the circuit configuration for realizing this are skillfully combined to realize an unequal-length encoding device that has high compression efficiency as a whole and has a simple circuit configuration.

Next, the present invention will be explained in detail with reference to the drawings.

FIGS. 1 and 2 are a block diagram and timing chart showing an embodiment of the encoding device of the present invention. Although the device of the present invention can be applied to sampled time-series signals such as image signals and audio signals, a television signal will be explained here as an example.

First, the television signal supplied to the input terminal 1 is converted into a multilevel time series signal (S4 in FIG. 2) with a biased frequency of occurrence suitable for the conversion device of the present invention.
It is converted in the DPCM encoder 2 and sent to the signal line 10.
Output to 0. At this time, a synchronization timing signal (S3 in FIG. 2) and a sampling clock pulse (S1 in FIG. 2) are simultaneously output to signal lines 103 and 102. This synchronization timing signal S3
is used as information representing the division of blocks to compress and encode time series data by dividing them into blocks of a certain length.

Now, the encoding device of the present invention shown in FIG. a second code generator 4 that generates the first and second codes; a multiplexer 6 that integrates the first and second codes; It is composed of a code array conversion circuit 7. Note that reference numeral 8 is a memory that stores data converted by this encoding device. When using the device of the present invention by incorporating it into a communication device through a line,
The memory 8 is used as a buffer memory for speed smoothing, and when the device of the present invention is used as a part of input means for a data file included in a computer device, the memory 8 is used as a memory of the computer or as an interface. Used as memory. Here, the first code R is a code representing the run length of the most frequently occurring value in time series, and the second code V is a code representing the value (level) of the multilevel signal. Also, R code and V
Each code includes at least one transition code. These are respectively referred to as the first transition code (hereinafter referred to as R ^* code) and the second transition code (hereinafter referred to as R* code).
V ^* code). The R ^* code is a code that indicates a transition from the R code to the V code, and the V code is sent out after the R ^* code in time series.

Further, the V ^* code is a code indicating a transition from the V code to the R code, and the R code is sent out after the V ^* code.
For codes other than transition codes, the R code is followed by the R code, then V
The next code shall be the V code.

FIG. 3 shows an example of the code V for signal levels 0 to 5 of the multilevel signal. For signal level 0, that is, the most frequently occurring value, a code V ₀ that does not transition is given in addition to the transition code V ^* ₀ . The V code is assumed to be an unequal length code with a code length of 2 to 4 as shown in the figure. An unequal length code is a code that has the characteristic that if the beginning of the code is known, the length of the code or the end of the code can be determined from the time series of the code.
In Figure 3, for example, the codes that start with 1 are ``11'' of code V <sup>*</sup> <sub>0</sub> and ``10'' of code V ₁ .
There are only two code lengths, both of which have a code length of 2. Also,
The _only code that follows "011" is code V2 with a code length of 3. When the code becomes "00..." or "010...", the code length becomes 4.

FIG. 4 shows an example of the R code for the run length of the most frequently occurring signal value. Here, the R code is also assigned an unequal length code with a code length of 2 to 4. The codes representing run lengths from 0 to 7 are respectively
R ^* ₀ to R ^* ₇ and these are transition codes. The code _R3 whose run length represents 8 is not a transition code.
In the present invention, it is also possible to define all run-length codes as transition codes, but generally, as the run length increases, the number of types of codes that represent it increases, and the code generation circuit becomes complex. Therefore, in the present invention, as shown in FIG. 4, a non-transition code and a transition code are used to encode a large run length. For example, using a non-transition code R ₈ , the run length 8 is R ₈ + R ^* ₀ ,
Run length 10 can be expressed as R ₈ +R ^* ₂ , and in the example of FIG. 4, run lengths from 0 to 15 can be expressed by nine types of codes.

Note that a larger run length can be expressed by increasing the number of non-transition codes as necessary.

The method of determining unequal length codes as shown in FIGS. 3 and 4 is actually to obtain statistics of the frequency of occurrence of each signal level and each run length for the target image signal, For example, Huffman codes are assigned to these probability distributions. This results in
The overall compression code amount can be minimized.

Next, the configuration and operation of each part 3 to 7 of the present invention will be explained in order. To make the explanation easier, the input multi-value time series signal 100 will be 6 from 0 to 5.
The most frequently occurring signal value is assumed to be 0 level. That is, the signal line 100 has 3
It is assumed that the data line is composed of parallel bit data lines, and the signal levels from 0 to 5 are expressed as binary numbers 000, 001, etc., respectively.

FIG. 5 is a diagram showing a specific circuit of the timing control circuit 3. In the figure, an OR circuit 31 determines whether or not the level of a multilevel time series signal having levels from 0 to 5 is 0, which is input through a signal line 100, and a delay adjustment register 34 performs delay adjustment to signal the signal. It is output as the most frequently occurring signal to line 101 (S5 in FIG. 2). (In Figure 2, for simplicity, it is assumed that there is no input signal to be encoded at times t ₀ and t ₁₄ , which have synchronization timing. (In the blanking period of television signals, it is often the case that such encoding is not performed. (Yes) At this time, the most frequently occurring signal is set to 1 (high level)) OR gate 3
The output of 1 is delayed by 1 clock by register 32 for 1 clock delay and applied to OR gate 35. The OR gate 35 performs an OR operation on this signal and the undelayed original signal (S6 in FIG. 2), and supplies this signal through a signal line 203 to a timing pulse generator 33 composed of a register and a gate. The timing pulse generator 33 uses the signal on the signal line 203 and the clock pulse to generate a timing pulse for generating a V code (S6 in FIG. 2), a timing pulse for generating a transition code V ^* (S7 in FIG. 2), and a timing pulse for generating an R code. timing pulse (S8 in Figure 2) and transition code R ^* generation timing pulse (S8 in Figure 2)
9) is generated on signal lines 104-107. Furthermore, the multilevel time series signal S4 and the synchronized timing signal S3 are also delayed and adjusted by the delay adjustment register 34, and outputted to the signal lines 110 and 113, respectively. The delay adjustment register 34 is used to compensate for delays caused by waveform processing in the timing pulse generation circuit 33. In addition, the timing pulses S6, S7, S8 in FIG.
and S9 indicate the state after delay adjustment, and the relative time relationships of the signals S1 to S9 are described so as to be correct when viewed from the output of the timing control circuit 3. That is, S3, S4,
The waveforms of S5 are the waveforms of signal lines 113, 110, and 101, respectively. Timing control circuit 3
The multilevel time series signal 100, the V code generation timing pulse S6, and the transition code V ^* generation timing pulse S7 generated in the above are supplied to the second code generator 4 in FIG. The second code generator 4 generates a V code on its output signal line 120 in response to the timing pulse, and generates a binary code on a signal line 121 indicating the code length of the V code. Furthermore, the most frequently occurring signal S5, R code generation timing pulse S8, and transition code R ^* generation timing pulse S9 from the timing control circuit 3 are supplied to the first code generator 5.
The first code generator counts the number of consecutive 0's in the most frequently occurring signal S5, generates an R code on its output signal line 130 in response to a timing pulse, and outputs the code length of the R code on a signal line 131. Generates a binary code indicating . Timing pulses S6 and S8 are used so that the V code and R code do not occur at the same time.
is controlled by.

The V code and R code generated on the signal line 120 and the signal line 130 are time-division multiplexed by the multiplexer 6. Similarly, binary codes indicating the code length generated on the signal line 121 and the signal line 131 are also time-division multiplexed by the multiplexer 6. The multiplexer 6 further generates an unequal length code M (S10 in FIG. 2) in which the synchronization code S is time-division multiplexed into R and V codes in accordance with the synchronization timing pulse supplied through the signal line 113.
is output to the signal line 140. Similarly, for the binary code indicating the code length, a code length signal N is obtained by time-division multiplexing each code length of the R and V codes and the synchronization code S.
(S11 in FIG. 2) is output to the signal line 141.

In S10 of FIG. 2, the symbol x indicates an arbitrary code, and the fact that the number of effective codes in S11 of FIG. 2 is 0 indicates that there is no meaningful unequal length code at that time.

Here, the combination of the V code and the R code in S10 in FIG. 2 will be explained. This example works according to the following rules:

(1) Give a code Vk (k=1 to 5) that does not transition if the multilevel time series signal has a value other than the most frequently occurring value.

(2) For the first most frequent value where the multi-level time series signal changes from a value other than the most frequent value to the most frequent value, (a) when the second signal is the most frequent value, the transition code V ^* ₀ is set. give,
(b) Give a code V ₀ that does not transition when the second signal is not the most frequently occurring value.

(3) For two or more consecutive most frequently appearing values, the run length excluding the first most frequently appearing value is expressed by an R code.

(4) R code is R ^* ₁ when the run length is 1 to 7.
It is represented only by the transition code ~R ^* ₇ , and when the run length is 8 to 15, it is represented by a combination of the non-transition code _R8 and the transition code R ^* ₀ ~ ^R* ₇ .

(5) The beginning of the block shall be a V code.

This rule is called Rule 1.

In FIG. 2, at times t ₁ , t ₂ , t ₃ , t ₈ and t ₁₀
Since the value is other than the most frequent value, Rule 1
(1) gives the V _k code as shown in S10 of FIG. At times t ₄ and t ₁₁ , the transition code V ^* ₀ is given by rule 1 (2) (a), and the time
At t ₉ , non-transition code V ₀ is given by (b) of (2). According to (3) and (4) of Rule 1, the most frequently appearing signal from time t ₅ to t ₇ is represented by an R ^* ₃ code representing a run length of 3, and this code is used as a time signal as shown in FIG. 2 S10. Output at t ₇ . The same applies to times _t12 to _t13 . Although not shown in this figure, when the run length is 8 or more, a transition code is output at the time of the last most frequently occurring value signal, and a non-transition code is output one clock before that. Times t ₁ and t ₁₅ correspond to the beginning of the block, and according to Rule 1 (5), they are given a V code. At this time, when the beginning of the block is the most frequently occurring value, as at time _t15 , if time _t16 is the most frequently occurring value, a V ^* ₀ code is given, and if it is not the most frequently occurring value, a _V0 code is given.

FIG. 6 is a diagram showing a specific circuit of the second code generator. In the figure, the multilevel time series signal S4 is passed through the signal line 110 to address input terminals _A2 to read-only memories (ROM) 41 and 42.
A ₀ is supplied. Furthermore, the transition code generation timing pulse S7 is sent to the ROM 41 via the signal line 105.
and 42 address input terminal _A3 .

The timing pulse passes through the signal line 104,
It is supplied to the output control terminals (for example, chip selection terminals) of the ROMs 41 and 42. Here, ROM41
When the output control terminal is turned off, all outputs of 42 and 42 become 0, and only when the timing pulse is on, the content specified by the address line is output to the output signal line 120.
and output to 121. ROM41 and 4
The contents of 2 can be easily created from FIG. That is, if A ₀ is an address line represented by 2 ⁰ and A ₁ is an address line represented by 2 ¹ . . . , code patterns corresponding to codes V ₀ to V ₅ are written in addresses 0 to 5 of the ROM 41,
The corresponding code length is expressed in binary and written in the ROM 42. Also, ROM41 and 42
At address 8, there are binary codes representing a V ^* ₀ code pattern and a code length of 2, that is, output terminals O ₃ ,
Write 0, 1, 0 in the order of O ₂ and O ₁ . Note that the code pattern is written so that the output terminal of the ROM 41, for example, the terminal _O4 side, always has the first bit code. For example, if the number of codes is 2 bits, the remaining 2 bits may be 0 or 1. This is the symbol ×
For example, the V ^* ₀ code pattern written at address 8 is "11××" in the order of output terminals O ₄ to O ₁ .
is output.

FIG. 7 is a diagram showing a specific circuit of the first code generator. The most frequently occurring signal supplied through the signal line 101 is applied to the clear terminal of the counter 51. The clock pulses supplied through signal line 102 are applied to the clock input terminal of counter 51, and the number of clock pulses during the period in which the most frequently occurring signal is 0 is counted. When the most frequently occurring signal becomes 1, the counter is cleared. The output of the counter 51 is
Address input terminals _A3 to _A0 of ROM51 and 52
supplied to

As in the case of the second code generator, the transition code output timing pulse is sent from the signal line 107 to the ROM5.
The R code output timing pulse is applied to _the output control terminals of the ROMs 51 and 52 through the signal line 106. Each of the ROMs 51 and 52 outputs an R code corresponding to the run length and its code length when the output control terminal is on, and all outputs are 0 when the output control terminal is off. ROM
The contents of 51 and 52 can be determined from FIG. 4 in the same way as the second code generator, so their explanation will be omitted.

FIG. 8 shows an example of the configuration of the multiplexing circuit 6. The V code and R code supplied through signal lines 120 and 121 are time-division multiplexed by an OR gate 61, and a synchronization code S is further multiplexed by a multiplexer 63 to output an unequal length code M to an output terminal 140. The code generator 65 generates a synchronization code S, and in this example, the synchronization code S is a 5-bit code represented by "00001". That is, since the synchronization code S is a code to indicate the start of a block, it is necessary to set it to a code pattern that does not occur from the combination of the V code and R code shown in FIGS. 3 and 4. In this embodiment, the code "00001" is a pattern that does not occur as long as the above-mentioned V code and R code are switched and used. The multiplexer 63 switches between two input signals in response to a synchronization timing pulse supplied via a signal line 113, and outputs a synchronization code S when the synchronization timing pulse is zero. Similar multiplexing is performed on a code length signal indicating the code length. That is, reference numeral 62 is an OR gate, reference numeral 64 is a multiplexer, and a time-division multiplexed code length signal N is output to the signal line 141. Since the code length of the synchronization code 7 is 5, the pattern generator 66 generates a code pattern of "101".

Next, the unequal length code array conversion circuit 7 will be explained. The unequal-length code array conversion circuit 7 is a circuit that extracts a valid unequal-length code designated by n from unequal-length codes including invalid codes and performs array conversion.

FIG. 9 shows a specific circuit diagram of the unequal length code array conversion circuit, and FIG. 10 shows waveforms of each part thereof. The input signal to the conversion circuit 7 includes a 5-bit signal line 1.
unequal length code M (10th
S13) in the figure, a code length signal N indicating the length of the unequal length code supplied via the 3-bit signal line 141 (S14 in FIG. 10), and a sampling signal supplied via the signal line 102. There is a clock pulse. As is clear from FIGS. 3 and 4, the code lengths of the unequal length codes are 2, 3, 4, and 5. Furthermore, if there is no significant unequal length code, the code length is given as 0. Therefore, the 5-bit code provided on signal line 140 includes a mixture of valid and invalid codes. For example, in an unequal-length code given with a code length of 2, only the upper 2 bits of the code on the signal line 140 are valid, and the remaining 3 bits are invalid. Therefore, it is sufficient to remove the invalid code x from the unequal length code M and extract the valid unequal length code. When the operating sampling frequency is as low as several 10 to several 100 KHz, such array conversion of unequal length codes should be performed after parallel/serial conversion of the unequal length code to convert it into a 1-bit signal sequence. is convenient, but when the sampling frequency is as high as 10MHz, the operating speed of serial operations becomes
This will be difficult as it will be around 100MHz. The unequal length code array conversion circuit shown in FIG. 9 is a parallel operation type circuit that overcomes these drawbacks and operates at high speed.
That is, this circuit removes invalid codes from an unequal-length code M that includes invalid codes, repacks the bits, and then outputs the data to the output line 150 as parallel 4-bit data.
Output to. If we call this circuit a parallel operation unequal-length code array conversion circuit, the parallel operation unequal-length code array conversion circuit generally converts invalid codes from unequal-length codes containing invalid codes given by m-bit parallel signal lines. It can be expanded to a circuit that removes the sign and converts it to 1-bit parallel data.

Next, the operation of the circuit shown in FIG. 9 will be explained. Note that this circuit is an example in which m and l in the above description are set to m=5 and l=4, respectively.

The 5-bit unequal length code provided on signal line 140 is applied to shifter 71 and second shifter 72. A sictor is a type of multiplexer that switches input lines and output lines.
A circuit element such as Am25S10 manufactured by Device) is used. The input terminals of the first shifter 71 are I ₁ to _{I 8} ,
Assuming that the output terminals are _O1 to _O3 , the connections of the input and output terminals are determined by the number of shifts as follows (signals determining the number of shifts are given by signal lines 141a to 141c). When the shift number is 0, I ₁ and O ₁ , I ₂
and O ₂ , I ₃ and O ₃ are connected, and when the shift number is 1, I ₂ and O ₁ , I ₃ and O ₂ , I ₄ and O ₃ are connected, and generally when the shift number is n, I _{1 +o} and O ₁ , I _2+o and O ₂ , I _3+o and O ₃
is connected. The second shifter 72 has 4 output terminals
It has O ₁ to O ₄ , but the input/output connection operation is done by shifter 7.
It is the same as 1. Output terminal of first shifter 71
O ₁ to _{O 3} are connected to the input terminals of the register 74,
The output of the register 74 is connected to input terminals I ₁ -I ₃ of the first shifter 71 and input terminals I ₇ -I ₅ of the second shifter.

A 4-bit parallel code from which invalid codes have been removed is output to the output terminals O ₄ to O ₁ of the second shifter 72, but the remainder code generated when dividing the unequal length code into 4-bit units is output to the register 74. is temporarily stored. The number of remainder signs is calculated by modulo arithmetic circuit 73 and register 75. The modulo arithmetic circuit receives binary data indicating the code length of the unequal length code given by the signal lines 141a to 141c and the signal line 175.
Binary data indicating the remainder given by a and 175b are added, and the remainder obtained by dividing this by l is supplied to the register 75 via signal lines 173b and 173c, and when the addition result is l or more, The carry signal is applied to the AND gate 76 via the signal line 173a. In this example, since l=4, a normal binary adder can be used as the modulo arithmetic circuit. AND gate 76 creates a write pulse for writing output data into memory when the carry signal is output.

The operation of the conversion circuit will be explained using FIG.
For simplicity, the output (remainder number) of the register 75 at time t ₀ is assumed to be 0. The remainder number is indicated by a signal S15 in FIG. 10, and the result of addition of the code length S14 of the unequal length code and the remainder number S15 is indicated by a signal S16.
At time _t0 , the unequal length code is 5 bits, indicated by "00001", as shown in signal S13. Since this code has more than 4 bits, the terminal O ₄ of shifter 72
The previous 4 bits, ie, "0000" are output to ~ _O1 . The modulo arithmetic circuit 73 adds the remainder number 0 and the code length 5. At this time, since the addition result is 5, a carry signal 1 is given to the signal line 173a,
Remainder 1 (binary 01) is connected to signal lines 173b and 173
Output to c. Therefore, at time _t0 , a write pulse is generated as shown by signal S17, and the output data "0000" of shifter 72 is written into the memory as shown by signal S18. The remaining 1-bit code at time t ₀ is output from the input terminal I ₈ of the shifter 71 to the output terminal O ₃ and taken into the register 74 . At time _t1 , the unequal length code is 2 bits of "01" and the previous remainder code is 1 bit, so the 4-bit data to be written into the memory cannot yet be prepared. The previous remainder bit "1" is fed back from register 74 to input terminal _I3 of shifter 71. Also, each bit “1” and “0” of the 2-bit unequal length code
is applied to input terminals I ₄ and I ₅ of shifter 71. At this time, since the number of shifts is 2, the bits "1", "1" and "0" of these terminals I ₃ to I ₅ are output to the output terminals O ₁ , O ₂ and O ₃ of the shifter 71, respectively. and is taken into the register 74. Data “110” taken into register 74
is output to input terminals I ₇ , I ₆ , and I ₅ of shifter 72 at time t ₂ . At time _t2 , 4-bit data "0011" is input to the shifter 71 through the signal line 140. At this time, the shift number of the shifter 72 is 3 (the result of addition of the remainder 1 at time t ₁ and the code length 2 at time t ₂ ), so the shifter 72
The input terminals _I7 to _I4 are connected to the output terminals _O4 to _O1 . Therefore, the data written to the memory at time _t2 has the remainder code "110" at time _t1 and the code " ₀ " for the previous 1 bit of the 4-bit data input at time t2.
The code ``1100'' is the combination of . The remaining 3-bit code "011" out of the 4-bit data is taken into the register 74 via the shifter 71. In this way, the unequal length codes are rearranged and written into the memory every 4 bits.

Generally, if the maximum number of input parallel bits is m bits and the maximum number of parallel bits to be output is l bits, then the first shifter has at least the number of input signals (m+l).
-1) Bit, number of shifts is m, number of output signals is (l
-1) Bits are required. In addition, the number of input signals of the second shifter is (2l-1) bits, and the number of shifts is (l
-1), the number of output signals requires 1 bit. By adding an (l-1) bit register for storing the remainder bit, an accumulator for counting the remainder bit, and a modulo l operation circuit to these shifters, any unequal-length code of O to m bits including invalid numbers can be created. When a combination of .
In this unequal length code conversion circuit, if the number of parallel bits l is set so that surplus bits do not accumulate and overflow (if codes with the maximum code length m occur consecutively, set l = m), It is possible to generate unequal-length codes rearranged in parallel at the same sampling speed as the input data. For example m=
12, l=12, and the sampling rate is 10MHz, the maximum
Unequal length encoding of 120 Mb/S can be achieved, which is extremely advantageous for high-speed processing. Note that the shifter is basically a gate circuit that connects an input line and an output line under specified conditions, and is not limited to the circuit element Am25S10 described above.

In addition to the above-mentioned method, various methods can be considered as a combination method of V code and R code. For example, the following rules can be set: This is Rule 2.

(1) Two types of codes, transition code V ^* and non-transition code V, are assigned to signals other than the most frequently occurring value of the multilevel time series signal, and if the next signal is the most frequently occurring value, it is given the V ^* code,
If the next signal is a signal other than the most frequently occurring value, a V code is given.

(2) For the most frequently occurring value signal, its run length is encoded, and the R code is set according to the same rule as in rule 1 (4).

Encoding according to such a rule requires about twice as many types of V codes as in rule 1, but the information compression efficiency can be improved depending on the statistical properties of the target multilevel time series signal. In this case, it is of course assumed that the unequal length codes to be assigned to each code are optimized. As another modification to Rule 1, there is a method in which when one block consists of one block from the sync code to the sync code, and if there is a run-length code at the end of the block, the last run-length code is not sent. This scheme is applicable to both rules 1 and 2 above.

In the first embodiment of the present invention described above, the number of target multilevel time series signals is one, but this can be extended to a plurality of time series signals. For example, it is common practice to multiplex and transmit two time-series signals, a television signal and an audio signal, or to multiplex and transmit necessary mode information and information indicating the block number for each block. One feature of the present invention is that this information is time-division multiplexed onto parallel m-bit data lines by a multiplexing circuit before performing array conversion of unequal length codes. However, when a plurality of time-series signals occur simultaneously, some effort is required to time-division multiplex these time-series signals.

FIG. 8A shows a specific circuit of a multiplexing circuit that multiplexes a plurality of time-series data generated simultaneously. FIG. 8A is a modification of the multiplexing circuit shown in FIG.
These code length signals are respectively inputted via the . It is assumed that the data to be multiplexed is 4-bit audio data generated at time _t1 in FIG. Therefore,
Since the generation time of the _V1 code and the voice data generation time overlap, simple multiplexing is not possible. In FIG. 2, since there is no valid data at times t ₅ , t ₆ and t ₁₂ , audio data can be multiplexed by using these time slots. If the audio data is to be inserted immediately after the synchronization code S in order to easily identify the insertion position of the audio data, it is sufficient to temporarily store the unequal length code in a memory and read it out after closing the time when the code length becomes 0. That is, in FIG. 8A, the OR gate 61
The unequal length codes and their code length signals multiplexed in and 62 are once written into the memory 600. Gate circuit 603 receives the code length signal and sampling clock pulse 102 and generates a write pulse for memory 600 on output line 133 except when the code length is zero. Further, the gate circuit 603 is connected to the memory 60
Write 0 write pulse Address counter 6
01 to control the write address of the memory 600. Gating circuit 604 generates read clock pulse 136. This gate circuit 604
is controlled by the sampling clock pulse 102 and the gate pulse 134 obtained from the synchronization timing signal 113 through the timing shaping circuit 606 and the address match signal 135 output from the address comparator 605. The read clock pulse is supplied to memory 600 and to read address counter 602 to control the read address.

Multiplexing control is performed as follows. First, the time
At t ₀ and t ₁ , the synchronization code and the unequal length code for outputting audio data are not read from the memory 600 . During this period, the multiplexer 631 outputs the synchronization code generator 65 and the audio data generator 61.
The code generated from 1 is output to the output line 140.
Further, the multiplexer 641 outputs these code length signals to the output line 141. An unequal length code V ₁ is written into the memory 600 during the read suspension period. The address comparison compares the read address and the write address and informs the gate circuit 604 whether there is data to be read in the memory 600 or not.
At time _t2 , the read stop gate is turned off, and since there is data to be read in the memory 600, the unequal length code _V1 is read. By repeating this operation in order, the time axis can be closed using the time when the code length is 0. Furthermore, if such a multiplexing circuit is used, time-division multiplexing of code data becomes possible even when an unequal-length code of an image is generated at time _t0 (no blanking) in FIG. 2. It goes without saying that a memory circuit is not required if there is sufficient blanking time and audio data can be multiplexed during the blanking period.

The features of the unequal-length encoding device of the present invention are listed below: (1) Since run-length encoding is applied to the most frequently occurring signal value, compression efficiency is high.

(2) Since unequal length codes based on information theory can be assigned as V and R codes, compression efficiency can be further improved.

(3) Since the V code and the R code have both signal level information and code transition information, there is no need for a special code that represents only the transition.

(4) The number of V or R codes generated for one time in the time series can be reduced to one or less, and since they do not overlap in the time series, time division multiplexing of V codes and R codes is easy. It is.

(5) After time-division multiplexing multiple code sequences to which codes have been assigned onto parallel m-bit data lines,
Since the signal representing the number of codes is used to perform unequal length code array conversion to remove invalid codes, the unequal length code array conversion circuit can be used in common for multiple series of codes.

(6) The unequal length code array conversion circuit outputs 1-bit parallel data at the same speed as the input data speed, so high-speed operation is possible.

Due to the above features, the present invention can provide an encoding device with high compression efficiency and a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of the encoding circuit of the present invention, FIG. 2 is a schematic diagram showing the control timing, and FIGS. 3 and 4 are the first code and the second code.
5 is a block diagram showing an example of a timing control circuit; FIGS. 7 and 6 are block diagrams showing an example of the configuration of the first and second code generators, respectively; FIG. 8 is a block diagram showing an example of the configuration of a multiplexing circuit, FIG. 9 is a block diagram showing an example of the configuration of an unequal length code array conversion circuit, and FIG. 10 is a schematic diagram showing the timing of unequal length code conversion. and FIG. 8A is a block diagram showing another example of the multiplexing circuit. In the figures, reference numbers indicate the following: 2...
...DPCM encoder, 3...timing control circuit,
4... Second code generator, 5... First code generator,
6... Multiplexing circuit, 7... Unequal length code array conversion circuit, 8... Memory, 31, 35... OR gate,
32...Register, 33...Timing pulse generator, 34...Register, 41, 42, 52, 5
3...ROM, 51...Counter, 61, 62...
...OR gate, 63, 64...multiplexer,
65, 66... code generator, 71, 72... shifter, 74, 75... register, 73... adder,
76...AND gate, 601, 602...Counter, 603, 604...Gate circuit, 606...
...Timing shaping circuit, 605...Comparator, 60
0...Memory, 631, 632...Multiplexer, 611...Speech code generator, 612...Code generator.

Claims (1)

[Scope of Claims] 1. In an encoding device that divides at least one multivalued time series signal expressed in binary and whose frequency of occurrence is biased into blocks in time series and compresses and encodes each block, comprising: means for generating a synchronization code indicative of the multilevel time series signal; a code generating means; a second unequal-length code representing each signal value of the multivalued time-series signal except for the maximum frequency signal; a code representing the maximum frequency signal value and comprising a transition code and a non-transition code; a second code generation means that generates a third unequal length code; and the synchronization code and each of the codes from the first and second code generation means are arranged in parallel m (an integer of m≧2).
On the bit data line, there is a first line representing the continuation length.
After the unequal length code, a second unequal length code representing the value of the signal is output; after the second unequal length code, the second unequal length code is output; time division multiplexing means for outputting an unequal length code that transitions among the third unequal length codes when two or more maximum frequency signal values are consecutive; and each code arranged on the parallel m-bit data line. means for generating a display signal representing the length of the data line; and converting only the number of bits represented by the display signal from each code on the parallel m-bit data line into a predetermined order using the display signal. parallel l
An encoding device comprising means for outputting (an integer of 2 or more) bits onto a data line.