JPH02231734A - Gaas integrated circuit - Google Patents

Gaas integrated circuit

Info

Publication number
JPH02231734A
JPH02231734A JP1053102A JP5310289A JPH02231734A JP H02231734 A JPH02231734 A JP H02231734A JP 1053102 A JP1053102 A JP 1053102A JP 5310289 A JP5310289 A JP 5310289A JP H02231734 A JPH02231734 A JP H02231734A
Authority
JP
Japan
Prior art keywords
diodes
junction
input
diode
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1053102A
Other languages
Japanese (ja)
Inventor
Katsuya Hasegawa
克也 長谷川
Kaname Motoyoshi
要 本吉
Shutaro Nanbu
修太郎 南部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1053102A priority Critical patent/JPH02231734A/en
Publication of JPH02231734A publication Critical patent/JPH02231734A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00315Modifications for increasing the reliability for protection in field-effect transistor circuits

Abstract

PURPOSE:To enable a GaAs integrated circuit to be formed without complicating the process by respectively connecting plural P-N junction diodes in series between each input/output signal line and power source, and connecting at least one of P-N junction diodes so that it may be reverse to other diodes. CONSTITUTION:Two P-N junction diodes 1 and 2, which are connected reversely with each other, are put between an input/output signal line and a grounding power source line. For these protective diodes, the P-N junction diode 1 works as a protective diode to positive surge, and the P-N junction diode 2 functions as a protective diode to the negative surge. By using P-N junction as a protective diode this way, larger electrostatic breakdown strength can be obtained with small area as compared with the case where Schottky junction is used. Accordingly, a drawing-out electrode will do, so long as it is taken out to an N-type GaAs region, and there is no special need to add a process anew for formation of a protective diode. Hereby, a GaAs integrated circuit of high yield rate can be realized.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は入出力保護回路を有するGaAs集積回路に関
する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to GaAs integrated circuits with input/output protection circuits.

従来の技術 GaAsMESFET Cメタノレφセミコンダクター
(シーットキー接合ゲート型)電界効果トランジスタ]
を用いた集積回路は、GaAsの高い移動度のためにシ
リコンを材料とした集積回路では実現できない高速の信
号処理が可能であるため各方面で開発が進められている
Conventional technology GaAs MESFET C methanol φ semiconductor (sheet-key junction gate type) field effect transistor]
Integrated circuits using GaAs are being developed in various fields because they are capable of high-speed signal processing that cannot be achieved with integrated circuits made of silicon due to the high mobility of GaAs.

GaAs集積回路を実用化する上で信号端子の静電耐圧
の問題は大きな課題である。GaAs集積回路は構成基
本単位としてMESFET [:シ目ットキー接合ゲー
ト型電界効果トランジスタコを用いるが、MESFET
は静電耐圧が低くサージに弱いことが知られている。静
電耐圧向上のためには保護ダイオードを内蔵することが
必要である。
In putting GaAs integrated circuits into practical use, the problem of electrostatic withstand voltage of signal terminals is a major issue. GaAs integrated circuits use MESFETs as basic structural units;
is known to have low electrostatic withstand voltage and be susceptible to surges. In order to improve the electrostatic withstand voltage, it is necessary to incorporate a protection diode.

第7図は一般的な保護ダイオードの回路を示す図である
。従来のGaAs集積回路では保護ダイオードとして、
シIットキー接合ダイオードDIOO.D200を用い
ていた。しかしSt集積回路と同等なサージ耐圧を得る
ためには、非常に大きな面積のシ一ットキー接合ダイオ
ードを用いなければならないという問題があった。一方
、このサージ保護ダイオードをPN接合ダイオードで形
成することも可能である。PN接合ダイオードはシロッ
トキー接合ダイオードに比べて静電耐圧は大きく、十分
な静電容量を小面積で得ることができるが、p型GaA
s領域にオーミック電極をとろうとすると、n型電極と
は違った金属材料を用いなければならず、金属材料の蒸
着、フォトリソグラフィー エッチングまたはリフトオ
フなどの工程が新たに必要と1る。集積回路の製造では
、工程の複雑化は歩留まりの悪化に直結し、製造コスト
にも直接影響するので問題である。別の静電保護回路と
しては、入出力信号線に直列抵抗を挿入すると良いこと
が知られているGaAsIC1 GaAs集積回路のよ
うな高速信号を扱う回路では周波数特性の劣化が著しく
、適用することが難しい。
FIG. 7 is a diagram showing a general protection diode circuit. In conventional GaAs integrated circuits, as a protection diode,
Shitkey junction diode DIOO. D200 was used. However, in order to obtain a surge withstand voltage equivalent to that of the St integrated circuit, there was a problem in that a Schittky junction diode with a very large area had to be used. On the other hand, it is also possible to form this surge protection diode with a PN junction diode. PN junction diodes have a higher electrostatic withstand voltage than Sirotchi junction diodes and can provide sufficient capacitance in a small area, but p-type GaA
If an ohmic electrode is to be provided in the s-region, a metal material different from that used for the n-type electrode must be used, and new steps such as metal material vapor deposition, photolithography, etching, or lift-off are required. In the manufacture of integrated circuits, complication of the process is a problem because it directly leads to deterioration in yield and directly affects manufacturing costs. As another electrostatic protection circuit, it is known that inserting a series resistor in the input/output signal line is a good idea.In circuits that handle high-speed signals such as GaAs IC1 GaAs integrated circuits, the frequency characteristics deteriorate significantly, so it cannot be applied. difficult.

発明が解決しようとする課題 以上述べたように従来のGaAs集積回路では、保護ダ
イオードとして、シばットキー接合ダイオードを用いる
と、非常に大きな面積のダイオードを用いなければなら
ず、またPN接合ダイオードを用いると工程の複雑化が
避けられなかった。本発明は、このようなGaAs集積
回路の問題点を解決するサージ保護回路内蔵GaAs集
積回路を提供しようとするものである。
Problems to be Solved by the Invention As mentioned above, in conventional GaAs integrated circuits, if a Shibattky junction diode is used as a protection diode, a diode with a very large area must be used, and a PN junction diode must be used. If used, the process would become unavoidably complicated. The present invention aims to provide a GaAs integrated circuit with a built-in surge protection circuit that solves the problems of the GaAs integrated circuit.

課題を解決するための手段 本発明は、上記課題を解決するため、各々の入出力信号
線と電源線の間に、それぞれ複数のPN接合ダイオード
を直列に接続し、゜前記複数のPN接合ダイオードの少
なくともひとつは他のダイオードとは逆方向であるよう
に接続し、さらに低周波信号の入出力端子には直列抵抗
を挿入するものである。
Means for Solving the Problems In order to solve the above problems, the present invention connects a plurality of PN junction diodes in series between each input/output signal line and a power supply line, and At least one of the diodes is connected in the opposite direction to the other diodes, and a series resistor is inserted in the input/output terminal for the low frequency signal.

作用 本発明は、上記の構成により保護ダイオードとしてPN
接合ダイオードを用いているため、小さな面積のダイオ
ードで保護回路を形成でき、また逆方向に直列に接続さ
れたPNダイオードを用いるため、引出し電極はn型G
aAs領域に対してのみ取り出せばよく、保護ダイオー
ド形成のために、新たな工程を追加する必要は特にない
。また低周波信号の入出力端子にのみ直列抵抗を挿入す
ることにより、集積回路の高周波特性を損なうことなく
シリコン集積回路並の静電耐圧を得ることができる 実施例 第1図に本発明の一実施例の静電保護回路を示す。入力
信号線と接地電源線との間に互いに逆方向に接続された
ふたつのPN接合ダイオード1.2が挿入されている。
Function The present invention uses a PN as a protection diode with the above configuration.
Since a junction diode is used, a protection circuit can be formed with a diode of small area. Also, since a PN diode connected in series in the opposite direction is used, the extraction electrode is an n-type G
It is sufficient to take out only the aAs region, and there is no particular need to add a new process for forming the protection diode. Furthermore, by inserting a series resistor only in the input/output terminals of low frequency signals, an electrostatic withstand voltage equivalent to that of a silicon integrated circuit can be obtained without impairing the high frequency characteristics of the integrated circuit. An electrostatic protection circuit according to an embodiment is shown. Two PN junction diodes 1.2 connected in opposite directions are inserted between the input signal line and the ground power line.

第2図は、第1図の保護回路及びFETの実際のパター
ン図及び断面図を示す例である。IOは半絶縁性GaA
s基板、11,12.18.17はNyJIGaAs領
域であり、例えば185kaVの加速エネルギーでI 
X 1 0”cm−”のドーズ量、S1イオンをイオン
注入する。l3はP型Ga’As領域であり、例えば1
30keVの加速エネルギーで1 x 1 0”cm−
”Znイオンをイオン注入する。14,15.,18.
19はN型GaAs領域に対するオーミック電極で、例
えばAuGe/Ni/Auを蒸着、リフト゜オフしてパ
ターン出しする。このオーミック電極14.15を、そ
れぞれ入力信号線及び接地電源線に接続すれば、第1図
の保護回路が構成できる。このようにして形成された保
護ダイオードは、正のサージに対してはPN接合ダイオ
ード1が保護ダイオードとして働き、負のサージに対し
てはPN接合夕゜イオート゜2が保護ダイオードとして
機能する。いずれにしろPN接合を保護ダイオードに用
いるので、シmyトキー接合を用いる場合に比べて、小
さな面積で大きな静電耐圧を得ることができる。例えば
上記のイオン注入条件の下で、PN接合ダイオード1,
2の長さが90umになるように形成すると、400v
の静電耐圧を得ることができる( 1 0 0 p F
,0Ωのコンデンサ放電法による試験に対して)。
FIG. 2 is an example showing an actual pattern diagram and cross-sectional view of the protection circuit and FET shown in FIG. 1. IO is semi-insulating GaA
s substrate, 11, 12, 18, 17 is a NyJIGaAs region, for example, I
S1 ions are implanted at a dose of X10"cm-". l3 is a P-type Ga'As region, for example 1
1 x 10”cm- with acceleration energy of 30keV
"Ion implantation of Zn ions. 14, 15., 18.
Reference numeral 19 denotes an ohmic electrode for the N-type GaAs region, which is patterned by depositing, for example, AuGe/Ni/Au and lifting off. The protection circuit shown in FIG. 1 can be constructed by connecting the ohmic electrodes 14 and 15 to the input signal line and the ground power line, respectively. In the protection diodes thus formed, the PN junction diode 1 functions as a protection diode against positive surges, and the PN junction diode 2 functions as a protection diode against negative surges. In any case, since a PN junction is used as a protection diode, a large electrostatic withstand voltage can be obtained with a small area compared to the case where a symmetry junction is used. For example, under the above ion implantation conditions, the PN junction diode 1,
If the length of 2 is 90um, it will be 400v.
It is possible to obtain an electrostatic withstand voltage of (100 pF
, for tests using the 0Ω capacitor discharge method).

第3図には保護回路とともに形成されるFETの平面図
及び断面図も示した。18.19はソース及びドレイン
電極、16.17はソース及びドレイン電極下のN型領
域、20はゲート金属、21はFETのチャネルになる
低濃度のn型領域である。保護ダイオード部分の引き出
し電極はN型GaAs領域からのみ取り出すため保護回
路の形成のために新たに増える工程はP型GaAs領域
13を形成するイオン注入工程のみですむので、集積回
路の製造にとっては大きなメリットである。
FIG. 3 also shows a plan view and a sectional view of the FET formed together with the protection circuit. 18 and 19 are source and drain electrodes, 16 and 17 are N-type regions under the source and drain electrodes, 20 is a gate metal, and 21 is a lightly doped n-type region that becomes a channel of the FET. Since the extraction electrode of the protection diode part is taken out only from the N-type GaAs region, the only additional step required to form the protection circuit is the ion implantation step for forming the P-type GaAs region 13, which is a significant step in the manufacture of integrated circuits. This is an advantage.

第3図は本発明の別の実施例である。入力信号線と接地
電源線に挿入した本発明にかかる2個のダイオード群5
0を電源線と入力信号線の間にも形成したものであり、
より大きな対サージ性を確保することができる。第4図
は本発明のまた別の実施例である。入力信号線と接地電
源線に挿入した2個のダイオード群50を電源線と入力
信号線の間にも形成し、さらに直列抵抗30を挿入した
ものであり、さらに大きな対サージ性を確保することが
できる。ただし、この直列抵抗は高周波特性には悪影響
を与えるので注意が必要である。
FIG. 3 shows another embodiment of the invention. Two diode groups 5 according to the present invention inserted into the input signal line and the ground power line
0 is also formed between the power supply line and the input signal line,
Greater surge resistance can be ensured. FIG. 4 shows yet another embodiment of the invention. Two groups of diodes 50 inserted into the input signal line and the ground power line are also formed between the power line and the input signal line, and a series resistor 30 is further inserted to ensure even greater surge resistance. Can be done. However, care must be taken as this series resistance has a negative effect on high frequency characteristics.

第5図はSCFL (ソース●カップルド●FETIロ
ジック)により構成されたGaAs集積回路の一例であ
る可変分周器の回路ブロック図である。この回路はIG
Hz帯の入力(IN)をふたつのモード●コントロール
信号(NC,S!)の高低により、l28/129/l
li4/G5の4通りの分周比に切り換えて、出力(O
UT)するようなGaAs集積回路である。静電保護回
路を内蔵しない時の静電耐圧は30から150vであり
、実用上大きな問題である。本発明の保護回路をこの可
変分周器に適用した例を述べる。
FIG. 5 is a circuit block diagram of a variable frequency divider which is an example of a GaAs integrated circuit constructed by SCFL (source coupled FETI logic). This circuit is IG
Hz band input (IN) can be set in two modes: l28/129/l depending on the level of control signals (NC, S!)
Switch to the four division ratios of li4/G5 and set the output (O
It is a GaAs integrated circuit such as UT). The electrostatic withstand voltage without a built-in electrostatic protection circuit is 30 to 150V, which is a big problem in practical use. An example in which the protection circuit of the present invention is applied to this variable frequency divider will be described.

IGHzの高周波信号が印加される入力端子(ILIN
)には第3図に示す保護回路、その他の低速(10MH
z程度)で動作する端子(IC,SIF,OUT)には
第4図で示す保護回路(直列抵抗1kΩ)を使用した。
Input terminal (ILIN) to which IGHz high frequency signal is applied
) has the protection circuit shown in Figure 3, and other low speed (10MH
A protection circuit (series resistance of 1 kΩ) shown in FIG. 4 was used for the terminals (IC, SIF, OUT) that operate at temperatures around

本発明の保護回路を適用すると第6図に示すように25
0V以上の静電耐圧を得ることができる。入力端子(I
N , IN)にも第4図の保護回路を施せば、静電耐
圧を400v程度まで上げることはできるが、高周波特
性に悪影響を及ぼし、例えば1kΩの直列抵抗を使用す
ると分周器の最高動作周波数はIGHzから700MH
zにまで低下してしまうので、ここには第3図のものが
望ましい。
When the protection circuit of the present invention is applied, 25
Electrostatic withstand voltage of 0V or more can be obtained. Input terminal (I
If the protection circuit shown in Figure 4 is applied to N, IN), the electrostatic withstand voltage can be increased to about 400V, but this will have a negative effect on the high frequency characteristics, and if a series resistor of 1 kΩ is used, for example, the maximum operation of the frequency divider will be reduced. Frequency is from IGHz to 700MHz
z, so the one shown in FIG. 3 is desirable here.

発明の効果 以上述べたように本発明を用いれば、保護ダイオードと
してPN接合ダイオードを用いているため、小さな面積
のダイオードで保護回路を形成でき、また互いに逆方向
に直列に接続されたPNダイオードを用いるため、引出
し電極はn型GaAs領域に対してのみ取り出せばよく
、保護ダイオード形成のために、新たな工程を追加する
必要は特にないため、高歩留まりのGaAs  集積回
路を実現でき、また低周波信号の入出力端子にのみ直列
抵抗を挿入することにより、集積回路の高周波特性を損
なうことなく高い静電針圧を得ることができ、その実用
的価値はきわめて大きい。
Effects of the Invention As described above, by using the present invention, since a PN junction diode is used as a protection diode, a protection circuit can be formed using diodes with a small area, and PN diodes connected in series in opposite directions can be formed. Since the extraction electrode only needs to be taken out for the n-type GaAs region, and there is no need to add a new process to form the protection diode, it is possible to realize high-yield GaAs integrated circuits, and also to realize low-frequency By inserting a series resistor only at the signal input/output terminal, high electrostatic stylus pressure can be obtained without impairing the high frequency characteristics of the integrated circuit, and its practical value is extremely large.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路図、第2図は本発
明の一実施例の保護回路の平面図及び断面図、第3図、
第4図は本発明の別の実施例を示す回路図である。第5
図は本発明の1実施例であるGaAs可変分周器の回路
ブロック図、第6図は第5図の可変分周器の保護回路の
有無による静電耐圧をしめす図、第7図は従来の保護回
路を示す回路図である。 1,2●●●PN接合ダイオード、50●●●ダイオー
ド群。 代理人の氏名 弁理士 粟野重孝 ばか工名第 図 第 図 αυ <b> 第 図 第 図 第 図 第 図
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a plan view and a sectional view of a protection circuit according to an embodiment of the present invention, and FIG.
FIG. 4 is a circuit diagram showing another embodiment of the present invention. Fifth
The figure is a circuit block diagram of a GaAs variable frequency divider that is an embodiment of the present invention, Figure 6 is a diagram showing the electrostatic withstand voltage of the variable frequency divider of Figure 5 with and without a protection circuit, and Figure 7 is a diagram of the conventional variable frequency divider. It is a circuit diagram showing a protection circuit of. 1, 2●●●PN junction diode, 50●●● diode group. Agent's name Patent attorney Shigetaka Awano Baka Tech name Figure Figure αυ <b> Figure Figure Figure Figure

Claims (4)

【特許請求の範囲】[Claims] (1)各々の入出力信号線と電源線の間に、それぞれ複
数のPN接合ダイオードが直列に接続され、前記複数の
PN接合ダイオードの少なくともひとつは他のダイオー
ドとは逆方向であるように接続されていることを特徴と
するGaAs集積回路。
(1) A plurality of PN junction diodes are connected in series between each input/output signal line and a power supply line, and at least one of the plurality of PN junction diodes is connected in a direction opposite to that of the other diodes. A GaAs integrated circuit characterized by:
(2)各々の入出力信号線と電源線の間に、それぞれ複
数のPN接合ダイオードが直列に接続され、前記複数の
PN接合ダイオードの少なくともひとつは他のダイオー
ドとは逆方向であるように接続され、前記入出力信号線
と内部回路との間に直列に抵抗が挿入されていることを
特徴とするGaAs集積回路。
(2) A plurality of PN junction diodes are connected in series between each input/output signal line and a power supply line, and at least one of the plurality of PN junction diodes is connected in a direction opposite to that of the other diodes. A GaAs integrated circuit characterized in that a resistor is inserted in series between the input/output signal line and the internal circuit.
(3)複数の入出力信号線をもつGaAs集積回路にお
いて、高周波信号の入出力信号線と電源線の間には、そ
れぞれ複数のPN接合ダイオードが直列に接続され、前
記複数のPN接合ダイオードの少なくともひとつは他の
ダイオードとは逆方向であるように接続され、低周波信
号の入出力信号線と電源線の間には、それぞれ複数のP
N接合ダイオードが直列に接続され、前記複数のPN接
合ダイオードの少なくともひとつは他のダイオードとは
逆方向であるように接続され、前記低周波信号の入出力
信号線と内部回路との間に直列に抵抗が挿入されている
ことを特徴とするGaAs集積回路。
(3) In a GaAs integrated circuit having a plurality of input/output signal lines, a plurality of PN junction diodes are connected in series between the input/output signal line of the high frequency signal and the power supply line, and each of the plurality of PN junction diodes At least one diode is connected in the opposite direction to the other diodes, and a plurality of P
N-junction diodes are connected in series, at least one of the plurality of PN-junction diodes is connected in the opposite direction to the other diodes, and the N-junction diodes are connected in series between the input/output signal line of the low frequency signal and the internal circuit. A GaAs integrated circuit characterized in that a resistor is inserted in the GaAs integrated circuit.
(4)高周波信号が分周器の入力信号であり、低周波信
号が分周比設定信号および分周出力信号であり、入力信
号を分周比設定信号に応じた分周比に分周して分周出力
するような機能を有する特許請求の範囲第3項記載のG
aAs集積回路。
(4) The high frequency signal is the input signal of the frequency divider, the low frequency signal is the division ratio setting signal and the division output signal, and the input signal is divided into the division ratio according to the division ratio setting signal. G according to claim 3, which has a function of frequency-dividing and outputting
aAs integrated circuit.
JP1053102A 1989-03-06 1989-03-06 Gaas integrated circuit Pending JPH02231734A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1053102A JPH02231734A (en) 1989-03-06 1989-03-06 Gaas integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1053102A JPH02231734A (en) 1989-03-06 1989-03-06 Gaas integrated circuit

Publications (1)

Publication Number Publication Date
JPH02231734A true JPH02231734A (en) 1990-09-13

Family

ID=12933428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1053102A Pending JPH02231734A (en) 1989-03-06 1989-03-06 Gaas integrated circuit

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0575023A (en) * 1991-09-13 1993-03-26 Nissan Motor Co Ltd Input/output protector for integrated circuit
JP2007288210A (en) * 2007-06-18 2007-11-01 Renesas Technology Corp Semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0575023A (en) * 1991-09-13 1993-03-26 Nissan Motor Co Ltd Input/output protector for integrated circuit
JP2007288210A (en) * 2007-06-18 2007-11-01 Renesas Technology Corp Semiconductor integrated circuit

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