JPH02228169A - Laser beam modulated signal generating circuit - Google Patents

Abstract

PURPOSE:To keep the continuity of a memory read clock signal and to obtain a good picture quality by providing a delay means which successively delays a series picture signal with the clock signal to output plural delay picture signals and a selecting means which selects one signal. CONSTITUTION:A P/S converter 5 takes in picture signals corresponding to N-number of picture elements read out from a memory 4 in parallel and converts them to a series picture signal by a memory read clock signal(RCK), and this signal is inputted to a shift register 8. The register 8 shifts the picture signal of one picture element as the unit by a clock signal (CK) and outputs an 8-bit parallel picture signal whose delay time is extended by every one clock, and this signal is inputted to a data selector 9. A latch 10 latches the value of a counter 2 by a synchronizing signal(SYNC) and inputs it to the select control terminal of the selector 9, and then, the selector 9 selects the output of the register 8 designated by this designation and outputs it as a modulated signal from a terminal 7. Thus, the RCK continuously keeps a certain period to obtain the signal of good picture quality.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a laser beam modulation signal generation circuit used in a laser beam printer.

(Prior Art) As is well known, in a laser beam printer, a laser beam is scanned in the main scanning direction to form a desired leading edge on a photosensitive drum, and this leading edge is transferred and recorded with toner, etc. When scanning the laser beam, it is necessary to modulate the laser beam in accordance with the image to be recorded.

FIG. 3 is a circuit diagram of a conventional laser beam modulation signal generation circuit. In the figure, 1 is a clock generator that outputs a clock signal CK with a frequency of 0 times the 1 pixel frequency (for example, n = 8), and 2 is a clock generator that divides the clock CK output from the clock generator 1 and has a period of 1 pixel. A counter 3 generates a memory read clock signal RCK corresponding to the memory address counter (3) that counts the read clock signal RCK and outputs an address signal in units of multiple pixels to the memory 4.
MAC), 4 is a memory, and 5 is a parallel/serial conversion circuit (hereinafter referred to as P/S) for converting an 8-bit parallel image signal outputted from the memory 4 into a serial 8-bit image signal.

Here, in the memory 4, image signals for modulating the laser beam are stored in units of eight pixels in the main scanning direction for each memory address.

In the above configuration, the clock CK generated from the clock generator 1 is frequency-divided by, for example, 8 by the clock counter 2 and is supplied to the MAC 3 and P/85 as the read clock signal RCK of the memory 4. When the synchronization signal 5YNC indicating the scanning timing of the laser beam obtained by a synchronization detector (not shown) is input from the input terminal 6, the MAC 3 sends an address signal to the memory 4 and a latch signal to the P/S 5 in accordance with the memory read clock signal RCK. Start generation of LT. The P/S 5 takes in the image signals for 8 pixels read out in parallel from the memory 4 using the latch signal LT inputted every time for the image signals for 8 pixels, and then reads out the image signals from the memory using the memory readout clock signal RCK. The signal is converted into a time-series serial image signal pixel by pixel, and output as a laser beam modulation signal from the output terminal 7 to a laser scanner unit (not shown). This operation is repeated every time the synchronization signal 5YNC arrives, that is, for each line in the main scanning direction.

However, when performing the above operation, since there is no synchronization relationship between laser beam scanning and readout clock RCK, the synchronization signal 5YNC shown in FIG. 4(a)
With respect to the timing, the read clock signal RCK shifts for each line as shown in (b) and (d) of the figure
The laser beam modulation signals LS of each #J element of PO to P8 generated based on such a read clock signal RCK also shift as shown in FIGS. This deviation is at most one cycle of the read clock RCK, that is, one pixel, and the pixel position in the main scanning direction is shifted, degrading the image quality.

In order to improve this problem, if the synchronizing signal 5YNC is connected to the reset terminal of the counter 2 as shown at 11A in FIG. 3, and the counter 2 is reset by the periodic signal 5YNC, the time clock in FIG. As shown in ty-h, the timing difference between the synchronizing signal 5YNC and the read clock signal is corrected at the timing when the synchronizing signal 5YNC is input as shown in FIGS. 3(b), (d), and (f). , the laser beam modulation signal LS is also shown in (c) and (e) in the same figure.
.

The timings are aligned as shown in (Q), and the deviation is suppressed to within one period of the clock signal CK applied to the counter 2. In this example, since the frequency of the counter 2 is divided by 8, only a shift of 1/8 of the read clock signal RCK, that is, a shift of 1/8 pixel of the image signal occurs. For this reason, good painting can be obtained.

However, in this case, Fig. 5 (b+,
The read clock signal RCK shown in (d) and <f) has a discontinuous period before and after the timing of synchronization@5YNC.

Therefore, when the read clock signal RCK is used to control a circuit other than the laser beam modulation signal generation circuit, various problems occur due to the period fluctuation.

(Problems to be Solved by the Invention) As described above, in the conventional laser beam modulation signal generation circuit, the synchronization signal 5YNC and the memory read signal RCK are not in a synchronous relationship, so the laser beam modulation signal LS for each line is
A timing shift occurs, making it impossible to obtain a good image.In order to improve this, counter 2 is sent as a synchronous signal
If reset is performed using C, there is a problem in that the period of the memory read clock signal RCK becomes partially discontinuous, making it impossible to use it as a clock for other control circuits.

The present invention eliminates these problems and aligns the timing of the laser beam modulation W4 signal for each line while keeping the memory successive clock signal at a continuous constant cycle, thereby providing a laser beam modulation signal that can provide good image quality. The purpose is to provide a generation circuit.

(Structure of the Invention) (Means for Solving Problem yI) The present invention provides a clock signal generating means for generating a clock signal with a frequency of 0 times that of one pixel (an integer of n≧2), and this clock signal generating means. frequency dividing means for dividing the frequency of a clock signal generated by n to generate a read clock signal with a period corresponding to one pixel; memory address designating means for outputting an address signal; Parallel/serial converting means to output, and serial image signals outputted from the parallel/serial converting means are sequentially delayed by a clock signal generated from the clock signal generating means, and each pixel is processed by 1/n pixel period. a delay means for outputting n delayed image signals; and a delay means for outputting n delayed image signals;
Among the delayed image signals of g, one delayed image signal corresponding to the frequency division value of the frequency dividing means at the generation timing of the # synchronization signal is selected, and the selected delayed image signal is used as a laser beam modulation signal of one pixel. and a selection means for outputting as.

(Function) In the present invention, data is read from the memory while maintaining the continuity of the memory read clock signal, and the serial image signal output from the parallel/serial conversion means is converted into the clock signal generated from the clock signal generation means. to obtain n delayed image signals delayed by 1/n pixel period for each pixel, and among these n delayed image signals, the same WA
One delayed image signal corresponding to the frequency division value of the frequency dividing means at the generation timing of the @ symbol is selected, and the selected delayed image signal is output as a laser beam modulation signal of one pixel. Therefore, the deviation of 1ii* for each line can be suppressed to 1/n, and there is no discontinuous part in the cycle of the memory read clock, so it can be used as a clock signal for other control circuits without any problems. be able to.

(Embodiment) Fig. 1 is a circuit diagram showing an embodiment of the present invention, in which 1 is a clock generator, 2 is a counter, 3 is a MAC 14 is a memory, and 5 is a P/S 16 is an input terminal of a synchronous signal @5YNC. , 7 is an output terminal for the laser beam modulation signal LS, 8 is a shift register, 9 is a data selector, and 10 is a latch.

The clock signal CK generated by the clock generator 1 is frequency-divided by, for example, 8 by the counter 2, and the clock signal CK is divided into 8 by the counter 2, and the clock signal CK is divided by 8, and the clock signal CK is generated by the counter 2.
It is supplied to MAC3 and P/S5 as CK. M.A.
C3 generates a memory read clock signal @RCK when a synchronization signal 5YNC indicating the scanning timing of the laser beam obtained by a synchronization detector (not shown) is input from the input terminal 6.
Accordingly, generation of an address signal to the memory 4 and a latch signal LT to the P/S 5 is started. The P/S 5 is connected to the memory 4 by the latch signal LT input every 8 pixels.
After capturing image signals for 8 pixels read out in parallel from
The image signals are converted into serial image signals in response to the memory read clock signal RCK, sequentially output, and input to the shift register 8. The shift register 8 shifts the input image signal of approximately 1 pixel size using the clock signal CK before frequency division, outputs an 8-bit parallel image signal with a delay of 11 flll increasing by 1 clock, and inputs it to the data selector 9. . On the other hand, the latch 10 receives the count value of the counter 2 (2°=Q1, 21=Q2.22
=Q3) and inputs the value to the selection control terminal of the data selector 9. The data selector 9 selects the output of the shift register 8 specified by the output of the latch 10, and outputs it from the output terminal 7 to a laser scanner unit (not shown) as a laser beam modulation signal LS.

Figure 2 shows its operating waveform diagram, where (a> is the synchronizing signal 5YNC, (b) is the clock signal CK1, and (C) is the same as the clock signal CK1.
is the count value n of counter 2 (n=0 to 7), (d),
(Q), (j> is the read clock signal RCK, (e),
(h), (l is memory readout image signal LSS, (f), (
j) and (J) show the laser beam change II @ No. LS.

The operation of this embodiment will be explained below based on FIG.

First, when the synchronizing signal 5YNC arrives at the timing shown in FIG. 2(a), the MAC 3 starts the read operation of the memory 4 as described above, and the latch 10 latches the count value n of the counter 2.

Since counter 2 performs frequency division by 8, n is rOJ
~ "7" value. and. The count value increases each time the clock signal GK is input from "0" to "7", returns to "0" by the next clock signal CK that reaches "7", and repeats the increasing operation again. . Therefore, memory read clock signal! RCK is counter 2's callan t
-frin is low level between "0-3", "4-7"
During this period, the waveform is at a high level.

Now, if the synchronization signal 5YNC is input at the timing n=7 as shown in FIG. 2(C), the memory read clock signal @RCK will be at the timing shown in FIG. The signal is output in synchronization with the timing as shown in FIG. 2(e). The data selector 9 is set to select the image signal delayed by n+1 bits of the shift register 8 according to the value applied to the selection control terminal, that is, the output of the latch 10. In this case, the 8-bit delayed output is selected and the laser beam modulation signal LS is output at the timing shown in FIG.

In addition, when n=4, memory read clock signal RCK
The timing is as shown in (q) in the same figure, and the memory readout image signal LSS is outputted as shown in (h) in the same figure. The data selector 9 selects the 5-bit delayed output and outputs it as the laser beam modulation signal LS at the timing shown in FIG. As a result, the timing of the signal LS coincides with the timing shown in FIG. 3(f).

Furthermore, if n=0, memory read clock signal RC
K is at the timing shown in FIG. 5(j), and the data of the memory readout image signal LSS is outputted as shown in FIG. 4(k). The data selector 9 selects the output with a 1-bit delay, and selects the output with a 1-bit delay (
It is output as a laser beam modulation signal LS at the timing of il). As a result, the timing of the signal S is as shown in the figure (
f”) and (i). And,
n=7, n=4. In any case where n=o, there is no interference with the count value of the counter 2, so no discontinuous portion occurs in the memory read clock signal RCK.

〔Effect of the invention〕

As explained above, in the present invention, the memory read clock signal is 3T! The data is read from the memory while maintaining continuity, and the serial image signals output from the parallel/serial conversion means are sequentially delayed by the clock signal generated from the lock signal generation means. /
Obtain n delayed image signals delayed by n pixel periods, and select one delayed image signal corresponding to the frequency division value of the frequency dividing means at the generation timing of the synchronization @ signal from among the n@ delayed image signals. , this selected delayed image signal is output as a laser beam modulation signal for one pixel. Therefore, it is possible to suppress the image shift for each line to 1/n and maintain good image quality, and there is no discontinuity in the period of the memory read clock signal, so it can be used as a clock signal for other control circuits. The effect is that it can be used without any problems.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a time chart for explaining its operation, FIG. 3 is a circuit diagram of a conventional laser beam modulation signal generation circuit, and FIGS. FIG. 5 is a time chart for explaining the operation of the conventional laser beam modulation signal generation circuit shown in FIG. 1...Clock generator, 2...Counter, 3...
Memory address counter, 4... Memory, 5... Parallel/serial conversion circuit, 6... Input terminal, 7... Output terminal, 8... Shift register, 9... Data selector, 10. ··latch. Figure 1 Figure 3 Figure 4

Claims (1)

[Scope of Claims] A memory that stores an image signal for modulating a laser beam in units of multiple pixels in the main scanning direction is provided in one memory address, and the image signal in units of multiple pixels stored in each address of this memory is provided. In a laser beam modulation signal generation circuit that reads out image signals in parallel, converts the image signals into time-series serial image signals using a readout clock signal with a period corresponding to one pixel, and outputs the signal as a laser beam modulation signal, n of one pixel is used. A clock signal generating means for generating a clock signal with a frequency twice (an integer of n≧2), and a read clock signal having a period corresponding to one pixel by dividing the clock signal generated from the clock signal generating means by n. a memory address designating means for counting the read clock signals outputted from the frequency dividing means and outputting address signals in units of a plurality of pixels to the memory; and a plurality of clock signals read from each address of the memory. Parallel/serial conversion means for converting a pixel-by-pixel image signal into a time-series serial image signal using a readout clock signal output from the frequency dividing means, and outputting the serial image signal output from the parallel/serial conversion means; a delay means for sequentially delaying the image signal by a clock signal generated from the clock signal generation means and outputting n delayed image signals delayed by 1/n pixel period per pixel; Among the n delayed image signals outputted from the means, one delayed image signal corresponding to the frequency division value of the frequency dividing means at the generation timing of the synchronization signal is selected, and the selected delayed image signal is divided into one pixel. 1. A laser beam modulation signal generation circuit comprising: selective output means for outputting the laser beam modulation signal as a laser beam modulation signal.