JPH02224370A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make the current density of a part of a wiring the nearest to a signal generating source smaller than that of a wiring constant in width so as to protect the wiring against disconnection due to electromigration by a method wherein the width of a part of the signal wiring relatively close to the signal generating source is made larger than that of a part of the signal relatively distant from the signal generating source. CONSTITUTION:The width of a part of a signal wiring 1 relatively close to a signal generating source 2 is made larger than that of a part of the signal wirings 1 relatively distant from the signal generating source 2. The signal wirings 1 so formed as to become larger in width as approaching to the signal generating source 2 functions in such a way that the current density of the part of the wiring 1 relatively near to the signal generating source is made to decrease lower than that of the wiring 1 constant in width. As the signal wiring 1 becomes thinner in width as receding from the signal generating source 2 and decreases in capacitive load, the part of the wiring 1 on the signal generating side is made to decrease in current density. By this setup, the signal wiring 1 on a signal generating source can be improved in resistance to electromigration.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuit devices, and furthermore, to the signal wiring structure thereof, and is effective when applied to, for example, clock signal power supply systems, word lines and bit lines in memories, etc. related to technology.

[Prior art]

A clock signal power supply system for supplying a clock signal, which is used as a synchronization signal for a processor, etc., to each functional block inside the processor, inputs a clock signal generated by a clock pulse generator to various functional blocks via signal wiring. Transmit to transistor. At this time, if the undesired load formed by the capacitance component or resistance component of the signal wiring is large, a lock driver consisting of an inverter circuit is interposed in the middle of the signal wiring. . Further, the selection terminals of a large number of memory cells are coupled to a word line for selecting a memory cell. For example, in a MISFET (metal insulated field effect transistor) type memory, the selection terminal is connected to the selection terminal of a selection MISFET. It is used as a gate electrode. Such MI
For the word line to which the gate electrode of the SFET is coupled.

The gate-drain capacitance and gate-drain capacitance of the MISFET concerned
Source-to-source capacitance constitutes an undesirable load, which increases as the number of memory cells coupled to the -word lines increases. Therefore, a word driver that drives the word line from one end to the other requires a relatively large driving ability.

By the way, the width of the signal wiring in a conventional semiconductor integrated circuit device, such as the clock signal wiring of the processor and the word line of the memory cell, is usually formed to have a constant width from the signal generation source to the signal receiving section. The same applies to semiconductor integrated circuit devices that are automatically placed and routed using a CAD (computer aided design) system.

An example of a document describing signal wiring in a semiconductor integrated circuit device is Japanese Patent Laid-Open No. 107140/1983.

[Problem to be solved by the invention]

Regarding signal wiring of semiconductor integrated circuit devices, it is necessary to prevent disconnection due to electromigration (hereinafter simply referred to as EMD) from the viewpoint of reliability of operation.
It is also necessary to reduce the signal transmission delay from the viewpoint of improving the operating speed.

Electromigration is a phenomenon in which metal wiring begins to move by exchanging momentum with carriers, and it becomes more pronounced as the current density in the wiring increases.

For this reason, as the width of the signal wiring decreases as the degree of integration of semiconductor integrated circuit devices increases, the density of current flowing through the wiring increases, making EMD more likely to occur. According to the studies of the present inventors, this EMD is likely to occur in areas where the current density is high, and therefore, in signal wiring formed with the same width, it becomes more noticeable as the EMD approaches the signal generation source. That is, undesired capacitance components such as parasitic capacitance and stray capacitance are formed in the signal wiring, but when a signal current is supplied from the signal generation source, the undesired capacitance components are transferred to the signal generation source. The signal wiring is charged in order from the side closest to the signal source, and conversely, when the signal wiring is discharged, it is discharged in order from the position closest to the signal generation source. For example, if we consider the case where current is supplied to a signal wiring, the current supplied from the signal generation source is sequentially used to charge undesired capacitance components until it reaches the end of the signal wiring. In a signal wiring formed by , the current density increases the closer it is to the signal generation source, and as a result, when the width of the signal wiring is the same, EMD is more likely to occur as it is relatively closer to the signal generation source. The longer the signal wiring becomes, and the more the undesired load on the signal wiring increases,
Since the driving ability of the signal generation source must be increased, EMD in the vicinity of the signal generation source becomes more significant.

In addition, in signal wiring of the same width, the signal on the source side is
Since the capacitive loads in the succeeding stage are sequentially driven from now on, the signal delay on the signal generation source side during wiring delay is relatively influenced by components caused by the resistance of the wiring, and conversely, on the signal receiving end side. The signal transmitted to the signal line has already driven the capacitive component of the signal wiring, and there is no need to discharge the capacitance after that, so the delay time is determined by the component due to capacitance compared to the component due to resistance. becomes more dominant. From this point of view, the signal delay component in a signal wiring of the same width has a relatively large capacitance component and a large resistance component depending on the distance from the signal generation source, so that the overall signal delay component increases. The inventor discovered that the signal transmission is delayed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that can prevent EMD from occurring relatively easily in signal wiring on the signal generation source side.

Another object of the present invention is to provide a semiconductor integrated circuit device that can reduce signal transmission delay at a position relatively close to a signal generation source.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the width of the signal wiring at a position relatively close to the signal generation source is made wider than the width of the signal wiring at a position relatively far from the signal generation source.

At this time, the width of the signal wiring may be made gradually wider as it approaches the signal generation source, steplessly wider as it approaches the signal generation source, or the width of the signal wiring may be made wider as it approaches the signal generation source. branch in the direction closer to the source of the signal.

The sum of the widths of the signal wirings arranged in parallel in a branched state at any position from the signal generation source can be made larger than the wiring width in a non-branched state. Further, a second signal wiring made of a material having a lower resistance than the first signal wiring near the signal generation source can be connected in series with the first signal wiring made of the above-mentioned signal wiring.

In addition, when focusing on the resistance value of the signal wiring, the resistance value per unit length of the signal wiring at a position relatively close to the signal generation source is compared to the resistance value per unit length of the signal wiring at a position relatively far from the signal generation source. The resistance value per unit length of the signal wiring is formed to be lower than that of the signal wiring.

[For production]

According to the above means, the signal wiring, which is formed to be wider as it approaches the signal generation source, has a current density at a position relatively closer to the signal generation source in the signal wiring compared to a signal wiring with a constant width. It works to reduce the Further, the signal wiring becomes thinner and its capacitive load gradually decreases as it moves away from the signal generation source, so that this also works to reduce the current density on the signal generation source side.

These things improve the electromigration resistance of the signal wiring closer to the signal generation source.

In addition, the signal wiring, which is formed wider as it approaches the signal generation source, has less influence on signal delay at a position closer to the signal generation source than a conventional signal wiring formed with the same width. A relatively large resistance component tends to be reduced, and a capacitance component that has a relatively large influence on signal delay tends to be reduced at a position near the signal receiving end. The signal delay at a position close to the signal generation source is largely affected by the resistance component, and the signal delay at a position close to the signal receiving end is greatly influenced by the capacitance component, so the amount of increase in the capacitance component on the signal generation source side In a range where the amount of increase in the resistance value component on the signal receiving end side is relatively small, the signal delay in the signal wiring can be reduced.

In addition, the shape of the signal wiring whose width gradually increases is similar to that formed by connecting multiple wirings of different widths in series, so it cannot be stored in the CAD system. Assets on conventional automatic placement and routing software can be used as is. Further, the signal wiring formed wide in a stepless manner can be formed in a smaller area than when it is formed wide in a stepwise manner, thereby reducing undesired capacitance components.

In addition, by making the material of the first signal wiring closer to the signal generation source a material with a lower resistance value than the material of the second signal wiring connected in series with it, the influence of the resistance value component can be increased relatively. This reduces the signal transmission delay on the side of the signal generation source where the signal is large.

In addition, even if the width of the wiring layer is the same, the cross-sectional area is increased by using a thicker wiring layer, etc., and the resistance value per unit length of the signal wiring near the signal generation source is increased relative to the signal. By forming the resistance value per unit length of the signal wiring at a position far from the generation source, it is possible to improve the electromigration resistance performance of the signal wiring on the signal generation source side in the same way as when focusing on the signal wiring width. improvement,
or achieve a reduction in signal delay.

(Embodiment 1) FIG. 1 is a plan view of a semiconductor integrated circuit device (hereinafter also simply referred to as gate array) formed by a gate array method, which is an embodiment of the present invention.

Although the gate array shown in this figure is not particularly limited,
CMISFET (complementary MISFET) circuit type basic cells 11 are regularly arranged in the center of the surface of the semiconductor substrate 10, and these basic cells 11 are connected by signal wiring according to a required logic configuration. The wiring pattern for configuring the required logic in the gate array using the basic cells 11 is determined according to the specifications desired by the user, and a CAD system or the like is used to design such a wiring pattern.

The signal wiring of the gate array shown in this figure was designed and automatically arranged using the above-mentioned CAD system. The signal wiring is formed in wiring channels 12 formed between regularly arranged columns of basic cells 11. A large number of I10 cells 13, which can be selectively used as an output buffer circuit, an input buffer circuit, or an output buffer circuit, are formed around the area in which the basic cells 11 are formed, and the above-mentioned semiconductors outside of the I10 cells 13 are formed. A bonding pad 14 for electrical connection with the outside is formed on the outer periphery of the substrate.

A clock power supply system is formed in the gate array in this embodiment. Although not particularly limited to this, a clock signal supplied from the outside is transmitted to various logic circuit blocks as a synchronization signal or a timing signal. This figure representatively shows a part of the clock power supply system, which is connected to the I10 cell 13, which is an input buffer, and receives, for example, a system clock signal supplied from the outside, and divides the frequency. After that, a clock generator 15 supplies clock signals to necessary logic blocks, a clock buffer 16 is formed at the output stage of the clock generator 15, and a clock signal is received from the clock buffer 16, and the logic blocks 17.19 The clock buffer 18 and 20 supply clock signals to the inside of the clock buffer 16, and a signal wiring 1 for transmitting the clock signal from the clock buffer 16. The signal wiring 1 is branched into two lines from the middle, and each of the signal lines 1 is branched into two lines, each of which is connected to the clock buffer 1.
8.20 is connected. The signal wiring 1 is formed so that its width becomes gradually wider as it approaches the clock buffer 16 as a signal generation source, or in other words, it becomes gradually thinner as it approaches the clock buffer 18, 20.

Undesired stray capacitance is formed between the signal wiring 1 and the semiconductor substrate or between the signal wiring 1 and other wiring, and the clock buffer 18. which is to be driven by the signal wiring 1. Undesirable parasitic capacitance such as gate capacitance is formed in the transistor 20 . The undesired floating capacitance and undesired parasitic capacitance become undesired capacitance components to be driven by the signal wiring 1. Above signal distribution A
The undesired capacitance component that 11l should drive is relatively large;
Further, since the resistance component in the signal wiring is large, and furthermore, clock signals must be supplied to a plurality of logic blocks, the clock buffer 16 is required to have a large driving ability. Therefore, the above clockpup 716
forms two CMIS inverters on the basic cell,
These are connected in parallel. The clock buffers 18 and 20 supply clock signals to the basic cells in the logic block, and since the load to be driven is smaller than that of the clock buffer 16, they are configured by a single CMIS inverter with a small driving capacity. has been done.

FIG. 2(a) shows a detailed view of the clock buffer 16, and the interlayer insulating film is omitted in this figure.

The clock buffer 16 is a two-parallel CMIS inverter formed by connecting signal wiring and power supply wiring to the basic cell 11. That is, the clock buffer 16 has two P-shaped wells formed in the N-type well region 36.
A channel type MISFETP, P2, and two N channel type MISFEs formed in the P type well region 37.
TN, it is composed of N2. Above MISFETP
1. P is formed by three P-type semiconductor regions formed in parallel, and in this figure, the P-type semiconductor regions at both ends are M
ISFETP, source electrode 23, and MISFETP
2 source electrode 25, and the central P-type semiconductor region is M
ISFFTP,.

This becomes the drain electrode 24 common to P2. MISFE above
The TN layer and N2 are formed of three N-type semiconductor regions formed in parallel, and in this figure, the N-type semiconductor regions at both ends are the source electrode 26 of the MISFET TN layer and the MISFE TN layer.
TN, and the central N-type semiconductor region becomes a drain electrode 27 common to MISFETs N1 and N2. Between the three N-type semiconductor regions formed in parallel, there is a gate electrode 2 common to MISFFTP, ,N.
1, and the gate electrode 2 common to MISFFTP, ,N.
2 is formed. The source electrodes 23 and 25 of the MISFFTP, P2 are connected to the high level power supply terminal GND through the contact hole 29,
, , N, source electrodes 26 and 28 are in the contact hole 3
It is connected to the ground terminal Vss with a low level through the terminal Vss. A wiring 31 for transmitting a clock signal supplied from the outside to the clock buffer 16 is connected to the gate electrodes 21 and 22 via a contact hole 32, and also transmits a clock signal output from the clock buffer 16. The signal wiring 1 is the contact hole 3
3 through the P-channel type MISFET P1. P,
drain electrode 24. and N-channel MISFET
N1. It is connected to the drain electrode 27 of N. The width of the signal wiring 1 in the vicinity of the clock buffer 16 is wider than that of conventional signal wiring formed with the same width.

FIG. 2(Q) shows an equivalent circuit of the clock buffer 16. Wiring 3 on the input side according to the input clock signal
When MISFET N1.1 is set to high level, MISFET Pl and P2 are turned off, and MISFET N1. Since N2 is in the on state, the ground voltage GN is applied to the signal wiring Mc1 on the output side.
A low level signal corresponding to D is output. In other words, the charges stored in the signal wiring 1 are discharged. Also, when the input side wiring 31 is set to low level, the MISF
ETP□, P2 are on, MISFETN, .N.

is in the off state, the signal wiring 1 is connected to the power supply voltage Vc
c is supplied and charged. In this way, the clock buffer 16 repeats the operation of charging the signal line 1 to the power supply voltage Vcc and discharging it to the ground voltage GND in response to changes in the low level/high level of the clock signal supplied from the outside. .

A detailed diagram of the clock buffer 18.20 is shown in FIG. 2(b). Like the clock buffer 16, the clock buffer 18.20 is a CMIS inverter formed by connecting signal wiring and power supply wiring to the basic cell 11. Of the three P-type semiconductor regions formed in parallel to each other, the one located in the center becomes the source electrode 23A, and the P-type semiconductor region adjacent to the source electrode 23A is connected to the source electrode 23A via the source electrode 23A and the gate electrode 21A. drain electrode 24
A, and a P-channel type MI S FFTP is formed. Furthermore, among the three N-type semiconductor regions formed in parallel in the P-type well region 37, the central one becomes the source electrode 26A, and the gate electrode 26A is common to the MISFETP.
The N-type semiconductor region adjacent to the source electrode 26A through 1A becomes the drain electrode 27A, and the N-channel type M
ISFETN is formed. The signal wiring 1 that supplies the signal output from the Glock buffer 16 is connected to the gate electrode 2LA via the contact hole 32A. Source electrode 2 of the above MI S FFTP3
3A is connected to a high level power supply terminal vcc through a contact hole 29A, and the source electrode 26A of the MISFETN is connected to a low level ground terminal GND through a contact hole 30A. The drain electrodes 24A, 27A are connected to an output side wiring 35 via a contact hole 33A. The width of the signal wiring 1 in the vicinity of the clock buffer 18 and 20 is as shown in FIG. 2(a).
The width of the signal wiring 1 is narrower than the width of the signal wiring 1 in the immediate vicinity.

FIG. 2(d) shows an equivalent circuit of the clock buffer 18.20. The above clock buffers 18 and 20
is a CMIS inverter circuit that combines an N-channel type MISFETN and a P-channel type MISFFTP3, and the signal wiring 1 on the input side is connected to the power supply voltage V c c
When it is set to a high level corresponding to the ground voltage GND, 1Ml5FETPj is turned off and MISFETN is turned on, so that a low level signal corresponding to the ground voltage GND is output to the wiring 35 on the output side. Moreover, when the signal wiring 1 is set to low level, MISFET N3 is in the on state.
Since MISFET N3 is turned off, the wiring 35 is supplied with the power supply voltage Vcc and charged. Similar to the clock buffer 16 shown in FIG. 2(Q), the clock buffers 18 and 20 charge and discharge the signal wiring in accordance with the low level/high level change of the transmitted clock signal. When the clock buffer 16 drives the signal line 1 based on the input clock signal, the signal line 1 is repeatedly charged and discharged. When the signal line 1 is charged, the undesired capacitance components of the signal line 1 are sequentially charged from the current supply side, so that the current flowing through the signal line 1 is not directly connected to the clock buffer 16. Maximum. By the way, the width of the signal line 1 is equal to the width of the clock buffer 16.
Since the current density is maximized in the vicinity of the clock buffer 16, the current density flowing through the signal wiring 1 in the vicinity of the clock buffer 16 can be reduced compared to a signal wiring with a constant width, and the EMD resistance of the wiring 1 can be improved. Furthermore, the width of the signal wiring 1 is formed to be narrower as it approaches the clock buffer 18.20, so the width of the signal wiring 1 in the vicinity of the clock buffer 18.20 is narrower than that of a signal wiring with a constant width. has been done. For this reason, the clock buffer 18°2
The undesired capacitance component formed in the signal wiring 1 in the vicinity of 0 is reduced compared to the signal wiring with a constant width.

The value of the current flowing through the signal wiring 1 to charge the capacitance component is also reduced. Due to this.

Focusing on the undesirable capacitance component formed by the signal line 1, the current density in the vicinity of the clock buffer 16 is further reduced, and the EMD resistance of the signal line 1 is further improved.

In the vicinity of the clock buffer 16, the resistance component of the signal line 1 is reduced compared to a signal line of constant width. In addition, as described above, the clock buffer 18
．． The undesired capacitance component in the vicinity of the signal line 20 is reduced compared to a signal line having a constant width. The signal delay of the signal wiring 1 is such that the resistance value component having a relatively large influence on the signal delay decreases at a position close to the clock buffer 16, and the signal delay increases at a position close to the clock buffer 18, 20. Since the capacitance component that has a large influence on the signal line 1 is reduced, the signal delay in the signal wiring 1 tends to be reduced. However, since the signal wiring 1 is formed wide on the clock buffer 16 side and thin on the clock buffer 18.20 side, the capacitance component on the clock buffer 16 side is
The resistance value component increases on the ゜20 side, but the resistance value component decreases on the clock buffer 16 side and the clock buffer 1
The shape and dimensions of the signal wiring 1 are determined so that the effect of reducing signal delay due to the reduction of the capacitance component on the 8.20 side is relatively greater.

According to the above embodiment, the following effects are obtained.

(1) Since the signal wiring 1 is formed to become wider as it approaches the clock buffer 16, the current density in the vicinity of the clock buffer 716 is reduced compared to a signal wiring of a constant width, and the EMD of the signal wiring 1 is reduced. It has the effect of improving resistance to alcohol.

(2) Since the signal line 1 is formed to become thinner as it approaches the clock buffer 18, 20, an undesired capacitance component is formed in the signal line.

It is smaller than the signal wiring having a constant width, and the current value for charging the capacitance component can be reduced. As a result, the current density in the vicinity of the clock buffer 16 is further reduced, and the signal distribution i! This has the effect of further improving the EMD resistance of No. 1.

(3) Since the signal line 1 is formed to become wider as it approaches the clock buffer 16, compared to a signal line with a constant width, the resistance value component on the clock buffer 16 side has a relatively large effect on signal delay. Moreover, on the side of the clock buffers 18 and 20, capacitance components that have a relatively large influence on signal delay tend to be reduced. As a result, the signal delay in the signal wiring 1 is reduced in a range where the increase in the capacitance component on the clock buffer 16 side and the increase in the resistance value component on the clock buffer 18.20 side are relatively small. effective.

(4) Since the signal wiring 1 has the same shape as when it is formed by connecting multiple wirings of different widths in series, automatic placement and wiring can be performed using a CAD system using conventional software as is. There is an effect that it can be done.

[Embodiment 2] FIG. 3 shows an embodiment in which the signal wiring according to the present invention is applied to a word shunt line of a DRAM.

The DRAM shown in this figure has a memory cell area 50 configured by arranging, for example, one-transistor type memory cells 40 in a matrix, and selection terminals of the memory cells 40 are connected to word lines 41 corresponding to each row. is combined with Each word line 41 is made of polycrystalline silicon, and since it also serves as the gate electrode of the selection transistor of the memory cell 40, it is formed with a constant width. Word line 4 above
1 is divided in the middle, and the divided word lines 41 are commonly connected to a word shunt line 42 made of aluminum, which has a lower resistance than polycrystalline silicon.

Word drivers 43 are provided on both sides of the memory cell area 50.
, 43A are arranged, and the adjacent word shunt lines 42 are connected to different word drivers 43A.
, 43A. The word shunt line 42 is formed so that its width gradually increases as it approaches the word drivers 43, 43A. The word shunt line 42 is formed in the same shape as when multiple wires of different widths are connected in series, and therefore the word shunt line 42 is automatically placed by a CAD system using conventional software as is. It is easy to form with wiring.

Further, since the adjacent word shunt lines 42 are coupled to the output terminals of different word drivers 43, 43A, the wide portions and thin portions of the adjacent word shunt lines 42 are arranged alternately, and It is possible to secure the spacing necessary to insulate the word shunt lines 42 from each other. Therefore, the word shunt line can be formed to be wider closer to the word driver without reducing the degree of integration of the memory cells.

In the DRAM of this embodiment, in order to access an arbitrary row in the memory cell area 50, a row address signal is first applied to the row address buffer 45 from the outside, and an internal complementary address is output from the row address buffer 45. The signal is decoded by the row address decoder 44, and depending on the signal from the row address decoder 44, one of the two divided word drivers 43 and 43A selects and drives one word shunt line 42. However, undesirable stray capacitance is formed between the word shunt line 42 or word line 41 and the semiconductor substrate, or between the word shunt line 42 or word line 41 and other wiring. A large number of memory cells are connected to the word line 41, and undesired parasitic capacitances are formed at the gates of the selection transistors of the memory cells, and the sum of the parasitic capacitances becomes a large value. The above-mentioned undesired stray capacitance and large parasitic capacitance become undesirable load components to be driven by the word shunt line 42. When the word drivers 43, 43A drive the word shunt line 42 to the selected level, a large undesired capacitance component formed in the word shunt line 42 due to the drive current is transferred to the side near the word driver 43, 43A. Since the word shunt line 42 is sequentially charged, the current value flowing through the word shunt line 42 is very large, and reaches its maximum value in the vicinity of the word drivers 43, 43A. By the way, the word shunt line 42
is formed wider as it approaches the word drivers 43, 43A, so the word drivers 43, 43A
The current density in the word shunt line 42 in the immediate vicinity is suppressed to be lower than that in a word shunt line having a constant width, so that the EMD resistance of the word shunt line 42 can be improved.

Since the word shunt line 42 is formed to become thinner as it goes away from the word driver 43 or 43A, the undesired capacitance component at the end of the word shunt line 42 is reduced compared to a word shunt line with a constant width. . Therefore, the current value flowing when the word shunt line 42 is driven to the selection level can be reduced.
The EMD resistance of the word shunt line 42 can be further improved by further reducing the current density in the vicinity of the word driver 43° 43A of the word shunt line 42.

The word shunt line 42 is connected to the word driver 43,
Since it is formed wider as it approaches 43A, the resistance value component of the word shunt line 42 in the vicinity of the word driver 43 or 43A is as follows.

This is reduced compared to a constant width word shunt line. Further, as described above, the undesired capacitance component at the end of the word shunt line 42 is reduced compared to a word shunt line having a constant width. The above word driver 43, 43
At a position close to A, the resistance value component that has a relatively large effect on signal delay decreases, and the word shunt line 4
Since the capacitance component that has a relatively large influence on signal delay is reduced at the end of the word shunt line 42 having a large undesired capacitance component, it is possible to obtain a tendency to reduce the signal delay of the word shunt line 42 having a large undesired capacitance component. By reducing the signal delay of the word shunt line 42.

The time required to select the memory cell located farthest from the word drivers 43, 43A can be shortened, thereby shortening the access time of the DRAM. However, since the word shunt line 42 is wide on the word driver 43, 43A side and thin at the end, the capacitance component increases on the word driver 43, 43A side, and the resistance component increases on the end. ,
The word shunt is designed so that the effect of reducing the signal delay due to the reduction in the resistance value component on the side of the word driver 43.43A and the capacitance component at the end is relatively larger than the amount of increase in the signal delay. The shape and dimensions of 1li42 have been determined.

According to the above embodiment, the following effects are obtained.

(1) The storage capacity of DRAM tends to increase, and since a large number of memory cells are connected to the word shunt line 42, an undesirable capacitance component is large, and the current value flowing through the word shunt line 42 is large. However, since the word shunt line 42 is formed to become wider as it approaches the word drivers 43, 43A, it has the effect of improving EMD resistance as in the first embodiment.

(2) Word shunt line 42 is word driver 43.4
Since it is formed so that it becomes wider as it approaches 3A, in the range where the amount of increase in the capacitance component on the side of the word driver 43. In the word shunt line 42, the signal delay is reduced, and the time required to select the memory cell located farthest from the word drivers 43, 43A can be shortened, thereby shortening the access time of the DRAM. It has the effect of being able to

(3) Word shunt line 42 is word driver 43.4
Since it is formed so that it becomes gradually wider as it approaches 9A, it has the effect that automatic placement and wiring using a CAD system is easy, similar to the first embodiment.

(4) Word driver 43.43A is memory cell area 5
Since the adjacent word shunt lines 42 formed at both ends of the memory cell area 50 are connected to different word drivers 43 43A, the wide portions of the adjacent word shunt lines 42 are connected to different sides of the memory cell area 50 This has the effect that a high degree of integration can be maintained while ensuring insulation between the word shunt lines 42.

[Embodiment 3] FIGS. 4(a) to 4(k) show an embodiment of signal wiring to which the present invention is applied, different from that adopted in Embodiments 1 and 2.

In this figure, signal wiring IA to IK, signal generation source 2. Only the signal receiving end 3 is shown, and a detailed explanation of a semiconductor integrated circuit device specifically using the above signal wiring is omitted.

FIG. 4(a) shows a signal wiring IA whose width gradually increases as it approaches the signal generation source 2, similar to the signal wiring employed in the first and second embodiments.

Unlike the first and second embodiments, only one signal receiving end 3 is connected to the signal wiring IA. Since the signal wiring IA is formed to be wider in stages as it approaches the signal generation source 2, the EMD resistance is improved as in Examples 1 and 2, automatic placement and wiring by a CAD system is easy, and the signal generation source In a range in which the amount of increase in the capacitance component on the second side and the amount of increase in the resistance value component on the signal receiving end 3 side are relatively small, the signal delay in the signal wiring is reduced.

FIG. 4(b) shows a signal wiring IB whose width gradually increases as it approaches the signal generation source 2. In FIG.

Similar to the signal wiring IA, the signal wiring IB has a shape in which multiple wirings with different widths are connected in series.
The locations where the wiring width changes are different on both sides of the wiring.

FIG. 4(c) shows a signal wiring IC whose width gradually increases as it approaches the signal generation source 2.

The signal wiring IC is formed in a tapered shape.

Compared to the case where the width of the signal wiring is increased stepwise, the signal wiring can be formed in a smaller area, and undesired capacitance components can be reduced.

FIG. 4(d) shows a signal wiring ID whose wiring width at the tip is constant and which is formed in a tapered shape from the middle toward the signal generation source 2.
is shown. The above-mentioned signal wiring ID is used when the above-mentioned signal wiring IC is to be formed, but it is restricted by layout rules such as contact hole dimensions, and the width of the above-mentioned signal wiring tip cannot be formed to be narrower than a certain level. Can be done.

Figure 4(e) shows a signal wiring IE with a shape close to an n-dimensional curve such as a hyperbola, quadratic curve, or cubic curve or an exponential function curve.
is shown. Similar to the signal wiring IC, the signal wiring IE can be formed in a smaller area than when the width of the signal wiring is gradually increased, and undesired capacitance components can be reduced. In addition, the above signal wiring IE
has a side profile close to an n-dimensional curve or an exponential curve, so
It becomes possible to make the current density substantially the same at all positions. That is, at any position on the signal wiring, the current value required to charge the undesired capacitance component formed in the signal wiring located further from the signal generation source 2 than that position is 2, and the rate of increase becomes larger as the signal generation source 2 is approached. When the width of the signal wiring is gradually widened according to the rate of increase in the current value, the signal wiring I
It has a side surface shaped like an n-dimensional curve or an exponential function curve, as shown by E, and in this case, it is also possible to make the current density substantially the same at all positions.

In FIG. 4(f), the width at the tip is constant, and the signal wiring I is formed in the shape of an asymptote from the middle toward the signal generation source 2.
F is shown. The above signal wiring IF is the above signal wiring IE.
This method can be used in cases where the width of the tip of the signal wiring cannot be made narrower than a certain level due to constraints imposed by layout rules such as contact hole dimensions.

FIG. 4(g) shows signal wiring IG that is branched midway in a direction close to the signal generation source 2 and arranged in parallel in a branched state. In this embodiment, the signal wiring IG is branched into two parts near the signal generation source 2 and arranged in parallel, and the width of each branched signal wiring and the signal wiring of the non-branched part are the same. but.

The sum of the widths of the parts near the signal generation source 2 is the signal receiving end 3.
It is wider than the width of the part closest to the .

Therefore, the signal wiring IG can prevent the occurrence of EMD and reduce signal delay.

FIG. 4(h) shows an example in which a plurality of signal generation sources 2 are connected to the signal wiring IG. One or more signal wires can be connected. When such signal wiring is used, a signal generation source 2 such as a buffer with a large driving capacity is required, but there are layout problems.

If it is difficult to form a large-sized buffer due to the limit on the number of simultaneous switching gates per cell column, it is possible to provide equivalent capacity by arranging multiple buffers with small drive capacity and connecting the output wiring. .

FIG. 4(i) shows a signal wiring structure in which the material of the signal wiring changes as it goes from the signal generation source 2 to the signal receiving end 3. As shown in FIG. The signal wiring 1 is formed by connecting a wiring 80 near the signal generation source 2 and a wiring 81 near the signal receiving end 3 through a contact hole 82. In this case, the contact hole 82 is locally thin as in the signal wiring IJ shown in FIG. 1(j), or as shown in FIG. 4(k).
The wiring 80, which may be locally thickened like the signal wiring IK shown in FIG. Considering the case where the signal wiring IN is formed of polycrystalline silicon, the resistance value that affects the signal delay in a portion relatively close to the signal generation source 2 is smaller than that of the case where the signal wiring IN is formed of only polycrystalline silicon. Since the component is reduced, the signal delay of the single wiring can be reduced. Further, the wiring 80 may be relatively EMD-free, for example.
Considering the case where the wiring 81 is made of tungsten, which has a high resistance, and the wiring 81 is made of, for example, aluminum, which has a relatively low EMD resistance, the signal generation source has the largest current value flowing through the signal wiring 1. Since the material in the vicinity of 2 is tungsten, which has a relatively high EMD resistance, it is possible to prevent the occurrence of EMD. Further, as shown in this figure, both the wirings 80 and 81 are formed in a tapered shape with a wider width on the signal generation source 2 side so that the resistance value component decreases as it approaches the signal generation source 2. The durability can be improved.

Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, although the gate array adopted in Example 1 is of a fixed channel type in which channels are formed between cell rows, the gate array is not necessarily limited to this, and a spread type without channels can also be adopted.

In addition, in Example 2, the signal wiring according to the present invention is
Although the case where it is applied to AM has been explained, it is not necessarily limited to this, and it is applicable to SRAM (Static RAM).
It can also be applied to signal wiring of semiconductor memory devices such as AM).

Further, although the word shunt line 42 in the second embodiment is made of aluminum, it is not necessarily limited to this, and other conductive materials such as tungsten can be appropriately employed.

Furthermore, although the word line 41 in the second embodiment is formed to have a constant width, it is not necessarily limited to this, and the word line 41 itself may be formed to become wider as it approaches the signal generation source. Since the word line also serves as the gate electrode of the selection transistor of the memory cell, it is necessary to consider the disadvantage that changing the width of the word line means changing the channel length of the transistor.

Further, although the signal wiring IG in Embodiment 3 is one in the immediate vicinity of the signal receiving unit 3, it is not necessarily limited to this, and may be formed in a plurality of wirings. Specifically, the sum of the widths of the wirings close to the signal generation source 2 needs to be larger than the sum of the widths of the wirings relatively far from the signal generation source 2.

Or the signal wirings IA and C in the third embodiment.

The side shapes of D, E, F, G, H, and I are symmetrical with respect to the center line, but they are not necessarily limited to this. For example, one side surface may be made of a straight line. Alternatively, an asymmetric shape may be adopted as appropriate.

The above explanation will mainly focus on the invention made by the present inventor, which is the field of application that forms the background of the invention, such as gate arrays and
Although the case where it is applied to a RAM has been described, the present invention is not limited thereto, and can be widely used in other semiconductor integrated circuit devices.6 The present invention has a signal wiring that transmits a signal in at least one direction. Conditions can be applied to those.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical ones are as follows.

That is, by forming the width of the signal wiring at a position relatively close to the signal generation source to be wider than the width of the signal wiring at a position relatively far from the signal generation source, The current density in the wiring is reduced compared to a signal wiring with a constant width, which has the effect of improving EMD resistance.

In addition, since the signal wiring is formed thinner as it goes away from the signal generation source, the capacitance component is reduced near the signal receiving end compared to a signal wiring with a constant width, and the current value for charging the capacitance component is reduced. is also reduced. Therefore, the current density in the wiring is further reduced, which has the effect of further improving EMD resistance.

In addition, the width of the signal wiring is wider as it approaches the signal generation source, and narrower as it is farther away from the signal generation source, so compared to a signal wiring of a constant width, the width of the signal wiring is narrower at a position closer to the signal generation source. A resistance value component that has a relatively large influence on delay is reduced. Further, at a position close to the signal receiving end, the capacitance component that has a relatively large influence on signal delay is reduced. This has the effect that the signal delay in the signal wiring can be reduced within the range where the amount of increase in the capacitance component on the signal generation source side and the amount of increase in the resistance value component on the signal receiving end side are relatively small. be.

Furthermore, by gradually increasing the width of the signal wiring as it gets closer to the signal generation source, it is possible to automatically arrange the signal wiring without making any major changes to the software of the conventional CAD system. be.

Furthermore, by making the width of the signal wiring steplessly wider as it approaches the signal generation source, the signal wiring can be formed in a smaller area than when it is made wider stepwise; This has the effect of reducing undesired capacitance components.

In addition, focusing on the resistance value of the signal wiring, we calculated the resistance value per unit length of the signal wiring near the signal generation source, and the resistance value per unit length of the signal wiring at a position relatively far from the signal generation source. By forming the resistor to be lower than the resistance value, it is possible to improve the electromigration resistance performance on the signal generation source side of the signal wiring or to reduce signal delay, similar to when focusing on the signal wiring width. effective.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a gate array in which the signal wiring according to the present invention is used in the clock power supply system, and FIGS. 2(a) to (d) are detailed diagrams and equivalent diagrams of the clock buffer in the gate array shown in FIG. 1. Circuit diagram, FIG. 3 is a plan view of the main part of a DRAM using the signal wiring according to the present invention as a word shunt line, and FIGS. 4(a) to (k) show examples of signal wiring to which the present invention is applied, respectively. It is a diagram. DESCRIPTION OF SYMBOLS 1... Signal wiring, 2... Signal generation source, 3... Signal receiving end, 1o... Semiconductor board, 11... Basic cell,
16°18...Clock buffer, 40...Memory cell, 1...Word line, 42...Word shunt line. 43°43A...Word driver. Figure 1 - Signal wiring 13 - 110 Cell 14 - Bonding I < Nod 16 S18/20 - Clock I/I

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device equipped with a signal wiring that transmits a signal in one direction, the width of the signal wiring at a position relatively close to the signal generation source is determined by A semiconductor integrated circuit device in which the width of the signal wiring is wider than the width of the signal wiring at a position remote from a source. 2. The semiconductor integrated circuit device according to claim 1, wherein the width of the signal wiring is gradually increased as it approaches the source of the signal. 3. The semiconductor integrated circuit device according to claim 1, wherein the width of the signal wiring is increased steplessly as it approaches the source of the signal. 4. The signal wiring includes a first signal wiring closer to the signal generation source and a second signal wiring formed of a material having a higher resistance value than the first signal wiring, connected in series. The semiconductor integrated circuit device according to any one of claims 1 to 3, comprising: 5. The signal wiring is branched along the way in a direction relatively close to the signal generation source, and the sum of the widths of the signal wirings that are branched in parallel at any position from the signal generation source is non-uniform. 4. The semiconductor integrated circuit device according to claim 1, wherein the width of the wiring is larger than the wiring width in the branched state. 6. In a semiconductor integrated circuit device equipped with signal wiring that transmits signals in one direction, the resistance value per unit length of the signal wiring at a position relatively close to the signal generation source is calculated as the relative value of the signal generation. A semiconductor integrated circuit device in which the resistance value per unit length of the signal wiring is formed to be lower than that at a position far from a source.