JPH02223251A - Wideband time division switching system - Google Patents

Abstract

PURPOSE:To perform wideband switching even when a time slot is selected at random by providing a sequence correction means to transmit sequence information as part of data for control and to perform the sequence correction of multiple data at a reception side. CONSTITUTION:A transmission means 71 to transmit the sequence information for the sequence correction of the multiple data as part of the data for control synchronizing with the multiple data to be sent at every frame to the multiplexed input side highway of a time division exchange is provided at a transmission side. And a sequence correction means 722 to perform the sequence correction of the multiple data when all the multiple data transmitted in the same frame are accumulated in the planes on one sides of buffer memories 724, 726 and 728 by outputting the contents of the buffer memories is provided at the reception side. Thereby, when two or more pieces of relating data exist separately in one frame on a time division speech path, the relativity of the data can be guaranteed, and the throughput of the exchange can be prevented from being lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic switching system, and in particular to wideband time division switching switch control for handling multiple traffic of 64 Kb/sXN from 64 Kb/S to about the primary rate. Regarding the method.

[Conventional technology]

Conventionally, time-sharing switches execute switching by writing all the information for one frame on the highway into memory, and then reading out the information in a different order.
Multiple traffic (
64K b/s (XN) using a normal 64 Kb/s time division switch, it becomes impossible to preserve the order of the signals on the input side and the signal order on the output side.

FIG. 6 shows the configuration of a standard time division switch with a conventional three-stage T-3-T (time division-space division temporal division) configuration.

FIG. 7 shows the configuration of the 128 multiplex time division primary switch (PSWO) in FIG. 6, and FIG. 8 shows an operational diagram. To explain the basic operation of a time division switch with reference to each figure, in Fig. 7, each line (MW
The information from O to HW3) is temporarily stored in the registers (RegO to Reg3) at timing A as shown in FIG.

This information is synchronized with the write address counter (WAC), and the WA of the memory switch (MS) is synchronized with the write address counter (WAC) at the write timing (W) of the memory switch read/write timing.
It is stored in the address shown in C in a time-division manner. This operation is repeated with one period of 125 μs. On the other hand, in the control memory (CM), the read timing of the control memory read/write timing is synchronized with the read address counter (RAC) representing the output time slot value.
R), control memo! It is configured to read the contents of the J (CM), and by performing a read operation to the memory switch (MS) based on the read data from the control memory (CM), any input side time slot (HWX −
CHX) information to any output side time slot (TSXX)
) can be output.

FIG. 8 shows a case where input information of HWO/CHO is output to output time slot) 3 (TS3).

[Problem to be solved by the invention]

Here, using the time division switch shown in Fig. 7, 64Kb
/ Considering the case of wideband switching of SX3,
192Kb/s (64Kb) shown in Figure 9(A)
/ s
When it reaches the time division switch via , and is written to the memory switch (MS) at the timing shown in Figure 9 (B), if the output side time slot is unconditionally selected, the output side time slot is Examples of the transmitted 192 Kb/s information are the cases shown in FIGS. 9(C), 9(D), and 9(E), but the order of the information is not guaranteed in cases other than FIG. 9(C).

To explain this point in detail, when data transmission is performed by connecting a data terminal with a transmission rate of 64 Kb/s or higher to a 64 Kb/s exchange, a series of data is divided into data for two or more lines within one frame. and will be transmitted separately (for 64Kb/sx3, 3 lines). Since these separate data groups have a close relationship and continuity within the same frame, it is necessary that input and output of the time division switch also occur within the same frame. In the claimed invention,
Hereinafter, such a series of data will be referred to as multidimensional data.

Now, as shown in FIG. 9(A), three data A, B, and C that are related within one frame, that is, 64 Kb/s×
The multi-dimensional data of 3 is connected to each channel of the input line (hereinafter referred to as C
(abbreviated as H) number Nα0. 1 and Nα2, and these lines are converged and input as shown in Figure 9 (B). A time division switch connects empty output side time slots (hereinafter referred to as OT).
(abbreviated as S) number NQI, 6.11 is selected and each data A
I, Bl.

Each CI is inserted and output (Figure 9(C))
Then, these data are output within the same frame and their relationship is preserved. However, as shown in FIG. 9(D), when OTS 1.3.11 is selected for each of the outputs of the three data A to C of 64 Kb/s, the data B is output to the memory switch. Since writing is not in time for reading (that is, insertion into OT S Na 3), data B of the previous frame (one cycle before) is always output to 0TSNα3, and the order between data A and C is not guaranteed. , it becomes impossible to maintain relevance at the receiving data terminal. Similarly, in FIG. 9(E), data B and C are always the data of one frame before. In a time division switch, as shown in Figure 9 (C), if a software algorithm is created to select the output side time slot so that reading is always performed after writing to the memory switch within the same frame, this can be done. 64 K b /
Even when exchanging s x n multi-dimensional data, the order and relevance are preserved, but this increases the processing time and block rate in selecting free time slots, and as a result, the processing capacity of the exchange itself is reduced. .

On the other hand, an example of a time division switch with a double buffer configuration in which two memory switches are used, and when one is in the write mode, the other is in the read mode is disclosed in Japanese Patent Application No. 108,647/1983 filed by the same applicant. Japanese Patent Publication No. 1986-194
660 Public Relations). When the above-mentioned 64 Kb/s x n exchange is performed using such a time division switch, the order and relevance of each data can be preserved.

However, this system requires two memory switches in each time division switch, making the entire system expensive. In addition, in networks that have already been constructed using conventional time-division switches that are not duplexed, all time-division switches must be replaced or modified to double buffering, which means that multiple data There is a problem that networks with small traffic volumes are disadvantageous due to excessive costs.

The purpose of the present invention is to provide a method that can be used when a frame on a time-division channel contains two or more pieces of related data (i.e., a 64 K b/s x n exchange). In networks, the aim is to provide a time-division switching system that guarantees the relevance of data and does not reduce the throughput of switching equipment.

[Means to solve the problem]

The present invention provides transmission data of K bits and L bits (L≧
2) In a time division exchange system equipped with a time division exchange for exchanging control data, when exchanging multiple data of K bits×P (2≦P≦Q) that constitutes a series of data within one frame. , in synchronization with the multiple data transmitted frame by frame to the Q-multiplexed input highway of the time division exchange, sequence information for correcting the order of the multiple data as part of the control data. A transmitting means for transmitting is provided on the transmitting side, and the Q multiplexing of the exchange is performed.
at least three buffer memories for receiving and accumulating the multidimensional data from the output highway; storage means for sequentially accumulating the multidimensional data in the at least three buffer memories based on the received order information; and an order correcting means for correcting the order of the multi-dimensional data by outputting the contents of the buffer memory when all of the multi-dimensional data transmitted in the same frame are accumulated on one side of the buffer memory; It is characterized by being prepared for.

〔Example〕

Referring to FIG. 1, one embodiment of the present invention includes a time division switch 1 and a plurality of lines HWO to HWO accommodated in this switch 1.
HW4. ! :, multiplexer 80 connected to this line
．． 81 and demultiplexers 82, 83, digital subscriber circuits (DLCs) 60 accommodated in each multiplexer and demultiplexer, and data for broadband services (e.g. 64 Kb; /5X3=192 Kb/s multiplexing). It consists of a terminal 90 and an interface device 70 connected between the DLC 60 and the terminal 90, respectively.

Exchange 1 has multiple primary switches (time division switches) PS
WIO to PSWI2, multiple secondary switches (space division switches) SSW20 to 22, and multiple tertiary switches (
It includes time division switches) TSWs 30 to 32, a serial/parallel (S/P) converter 40, and a parallel/serial (P/S) converter 50. This exchange 1 is the same as the conventional exchange shown in FIG. 6 in time-division exchange operation, and therefore the order of multiple data in an I frame is not guaranteed upon output.

Four uplink lines H-WO to HW3 are connected to the input of each S/P converter 40. Each line includes a data line 84 for call signals (in the case of telephone exchange) and transmitted data (in the case of data exchange), and a control line 85 for control data exchanged between terminals, between exchanges, or between terminals and exchanges.
(Details will be explained later). on the other hand,
The output of each P/S converter 50 is four downlink H
Connected to WO to HW3.

Uplink transmission data output from each DLC 60 is input to a multiplexer 80, multiplexed, and output to a data line 84. Similarly, uplink control data output from each DLC 60 is input to a multiplexer 81, multiplexed, and output to a control line 85. Further, the downlink transmission data and control data from the exchange 1 are sent to a demultiplexer 82.
．． 83, are separated and distributed to each DLC 60.

Next, an overview of data transfer in the system shown in FIG. 1 will be explained with reference to FIG. Transmission data sent from the data terminal on the transmission side is input to the interface device 70 and output to the DLC 60 together with control data. The DLC 60 performs known control specific to exchanges, and transmits data,
Each control data is input to a multiplexer 80.81. Digital data time-division multiplexed into 32 channels (one channel is 8-bit serial data) is sent from the multiplexer 80.81 to each of the lines HWO to HW3 every frame (125 μS) (see Figure 2). c.
) to (")). The 8-bit data of each channel CHO to CH31 is inputted sequentially to the 8-bit registers 401 to 404 of the S/P converter 40, and is converted into 8-bit parallel data by a 256 KHz latch pulse (Fig. 2 (g)). 8 as data
The data is stored in bit registers 405-408. Multiplexer 409 selects eight of these registers 405-408.
The bit parallel data is multiplexed into 1 frame 128 channels by combining 16 bits for 1 high time with all data for ICH and input to the primary switches 10 to 12 as data with time slat numbers 0 to 127 (Fig. 2). (h),
(i)). In the primary switches 10 to 12, time slot conversion is performed under the control of a central processing unit (not shown) as is well known.

Next, use the secondary switches 20 to 22 to select the desired tertiary switch 3.
Connections to 0 to 32 are made, and this tertiary switch 30 to
Further time slot conversion is performed at 32. P/S
Converter 50 performs an operation opposite to that shown in FIG. That is, the 128-channel multiplexed 16-bit parallel data is separated into 32-channel multiplexed data by the demultiplexer 509, converted to 32-channel multiplexed serial data via the 8-bit registers 501 to 508, and then demultiplexed by the demultiplexer 8.
The signals are separated at 83 and sent to each DLC 60.

The transmission data and control data sent to each DLC 60 are sent to the corresponding interface device 70, and based on the control of the control data, the transmission data is sent to the receiving terminal 90. Through the above operations, communication between arbitrary terminals is performed.

In this system, from the terminal 90, the 6
When transmitting 4 Kb/sX3 multiple data, the order of the multiple data at the output of the exchange 1 is not guaranteed. Therefore, in the system of this embodiment, the receiving side interface device 70 is configured to correct this order.

The details of this interface device 70 will be explained with reference to FIG. This device 70 is composed of a data transmitter 71 and a data receiver 72. The transmitting unit 71 has a buffer memory 713 that receives and stores data to be transmitted from the terminal 90, and a frame head pulse and a four-way pulse (both sent from the exchange 1) for transmission, which are allocated to the own device for transmission. Channel detection circuit 711 that identifies a channel and transmits data for one channel
, a data transmission circuit 712 that sends one channel of 8-bit data inputted from the buffer memory 713 to the DLC 60, and a ternary counter 714 that increments the count by one each time the transmission frame increments by one. A control data transmitting circuit 715 is provided which transmits the count result of the counter 714 to the DLC 60 as 2-bit data (hereinafter referred to as order information) of control data (8 bits) at the same time as transmit data.

The data receiving unit 72 includes a channel detection circuit 721 that determines the channel assigned to the device for reception from frame head pulses and clock pulses for reception, a data reception controller 722, and data sent from the DLC 60. Three buffer memories 724, 726, 728 for storing each frame, and a detection circuit 723 provided corresponding to these buffer memories to detect whether all data in each buffer memory has been stored and notify the controller 722, 725, 727, and a control data receiving circuit 729 that extracts the above-mentioned order information from the control data synchronized with the received data and notifies the controller 722.
and an interface circuit 730 for sending the outputs of the buffer memories 724, 726, 728 to the terminal 90. Here, the buffer memory 7-24, 726
Each of .728 has an area of at least 8 bits x 3 areas = 24 bits so that all multidimensional data for one frame can be stored. The controller 722 is
Writing to each buffer memory is controlled from the output of the detection circuit 721 and the output of the reception circuit 729. That is,
One buffer memory that stores received data is changed cyclically based on received order information. Details will be explained later.

In addition, the controller 722 has each detection circuit 723, 725
．． Reading of each buffer memory is controlled by the output of 727. That is, when all of the multidimensional data in one transmission frame is stored in one buffer memory,
The detection circuits 723, 725 and 727 provided corresponding to the buffer memory detect this fact from the controller 72.
Upon receiving this notification, the controller 722 sends the multiple data in the buffer memory to the terminal 90 via the interface circuit 730.

Next, the present invention will be described in detail using specific examples with reference to FIGS. 1 and 3 to 5. Now, suppose that the terminal 90 starts transmitting multiple data A, B, and C from the Nth frame (
Figure 3). At this time, the terminal 90 first sends at least one frame's worth of data (24 bits) to the buffer memory 713 of the interface device 70. The channel detection circuit 711 selects the channel No. 0.1 to which data should be transmitted.
When each of the two channels is detected, data for each channel is taken out from the buffer memory 713 and transmitted by the data transmitting circuit 712.

At this time, the order information counted by the ternary counter 714 is sent out via the control data sending circuit 715 in synchronization with the transmission data. That is, "00" is used as the order information for the three data AO, BO, and CO of the Nth frame, which is the transmission start frame. Next (N+
1) In the frame, "01", which is incremented by one, corresponds to the multi-dimensional data AI, Bl, and C1, is incremented by the next (N+
2) In the frame, multi-dimensional data A2. B2. "10" is sent in response to C2. In the (N+3)th frame, 3
The count of the decimal counter 714 returns to the original value and becomes “00” again.
(Figure 4). The multidimensional data sent in this way is
Assume that when passing through two time switches (primary and tertiary switches) in the exchange 1, the order is as shown in FIG. 4 due to the way the exchange takes internal time slots. That is, the multiple data AO, BO, and Co transmitted within the Nth frame are received across the Mth frame and the (N+1)th frame.

The control data is also received in exactly the same order as the multiple data.

Note that due to the nature of the exchange, A, A, and A in the same frame
The order between B and 0 does not change.

In other words, data A is always on the first channel for both transmission and reception.
is coming.

The operation performed when the interface device 70 on the receiving side starts receiving from the Mth frame will be described in detail. When each of the 0th to 2nd channels assigned to this interface device 70 for reception is detected, the channel detection circuit 721 notifies the controller 722.

Based on a combination of this notification and the order information notified from the circuit 729 at the same time as the data is received, the controller 722 determines in which area of which buffer memory the received data at that time is stored, and performs writing control.

To elaborate, Buffer Memo! 7724°726.728
are order information ro OJ and ro N, respectively.

It corresponds to "10". Also, in the three reception channels within the l frame, the first and second channels.

The third channel is located in each buffer memory area 1.
Area 2. Compatible with area 3. Specifically, the fifth
As shown in the figure, multiple data AO received on the Oth channel of the Mth frame is stored in area 1 of the buffer memory 24. In the 1st and 2nd channels of the Mth frame, neither multiple data nor order information is received, so nothing is written. Next, in the (M+1)th frame, the received data Al is stored in area 1 of the buffer memory 726.

On the other hand, it can be seen from the order information "00" that the data BO and CO are data of a frame earlier than the data A1 received in the same received frame. Each is stored in area 3. Next, in the (M+2)th frame, data A2 is accumulated in area 1 of the buffer memory 728, and data B1, C1
is area 2. of buffer memory 726. Each is accumulated in area 3. In this (M+2)th frame, the three multiple data AO to CO transmitted in the Nth frame for transmission are stored in the buffer memory 724 in the correct order, as shown in the figure. The detection circuit 723 detects that the entire area of the buffer memory 724 is filled and notifies the controller 722 of this. Upon receiving this notification, the controller 722 instructs the buffer memory 724 to output, thereby sending a series of multiple data AO-Go to the terminal 90 via the interface circuit 730.

Thereafter, the controller 722 clears the buffer memory 724 and prepares for reception of the (M+3)th frame. Thereafter, the same procedure is repeated, and data A1 to C1 are output from the buffer memory 726 in the (M+3)th frame. In this way, by using the three buffer memories cyclically, the order of multi-dimensional data is guaranteed, so that broadband switching is possible without using a special time switch in the exchange l.

In this embodiment, the data receiving buffer memory of the interface device 70 will be explained in terms of three aspects, and the order information used to properly use these three buffer memories is based on 2 bits of 8 bit control data. It was explained that it would be used. However, as is clear from FIG. 5, the data reception buffer memory has at least three sides (M
- In a frame, two sides are used for writing and one side is used for output)), and it is clear that the number of bits of order information changes depending on the number of sides.

For example, if 3 bits of order information are used, the number of usable buffer memory planes is up to 23=8 planes.

Further, one data reception buffer memory may have an area (three in the embodiment) that can store all the multiple data in at least one frame.

Furthermore, once a call is set up in exchange I, the internal time slot selected at that time remains unchanged until the call is terminated. Therefore, the order relationship of multiple data in received data remains fixed until the communication ends. Utilizing this property, if you monitor the order information of the first few frames at the start of data transmission/reception and recognize the pattern, the data reception buffer memory can be stored in the controller 722 without having to transmit the order information one by one. Control becomes possible.

〔Effect of the invention〕

As described above, according to the present invention, broadband exchange can be performed even if time slots are randomly selected without configuring a special time division switch.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart illustrating the outline of data transmission in FIG. 1,
FIG. 3 is a block diagram explaining the details of FIG. 1, FIGS. 4 and 5 are diagrams explaining the operation of FIG. 1, and FIG. 6 is a block diagram showing a standard three-stage switching configuration in a time division switching system. 7 are block diagrams showing a conventional time division switch, and FIGS. 8 and 9 are time charts explaining the conventional operation. 1...Time division switch, 10-12.30-32
......Time division switch, 20-22...
Space division switch, HWO to HW3... line,
60...Digital subscriber circuit, 70...
...Interface device, 90...Data terminal, 71...Data transmitter, 72...Data receiver. Representative Patent Attorney Susumu Uchihara Figure 3! Zuswitch (f) 22℃ switch (7-time separation Zui Utsu 3; Missing switch (Dip tube j Switch ji M6 diagram to Naruichi \ θ 弯

Claims (4)

[Claims] (1) K bits of transmission data and L bits (L≧2)
In a time division switching system that includes a time division switch that exchanges control data, the K bits x forming a series of data within one frame
When exchanging multiple data P (2≦P≦Q), the multiple data is transmitted in synchronization with the multiple data transmitted frame by frame to the Q-multiplexed input highway of the time division exchange. The transmission side is equipped with a transmission means for transmitting order information for order correction as part of the control data, and at least three planes for receiving and accumulating the multiplexed data from the Q-multiplexed output highway of the exchange are provided. a buffer memory; a storage means for sequentially accumulating the multiple data in the at least three buffer memories based on the received order information; 1. A wideband time-division exchange system, characterized in that a receiving side is provided with an order correcting means for correcting the order of the multi-dimensional data by outputting the contents of the buffer memory when the multi-dimensional data is accumulated on one side. (2) The order information is set corresponding to each side of the buffer memory, and the storage means stores the received multidimensional data on the side of the buffer memory indicated by the order information received together with the data. A broadband time division switching system according to claim (1). (3) The transmission means includes an R-adic counter (R≧3) that increments for each transmission frame, the order information is data obtained by encoding the output of this counter, and the number of sides of the buffer memory 3. The broadband time division switching system according to claim 2, wherein is an R-plane. (4) The broadband time division switching system according to claim 3, wherein the storage means stores the received multiple data by cyclically using the R-plane buffer memory.