JPH02222241A - Loop communication system - Google Patents

Abstract

PURPOSE:To reduce the circuit scale by loading a communication data and a control data on separate time slots of a 1st frame and sending the resulting data to the 1st transmission line. CONSTITUTION:A frame 9 being a 1st frame is circulated to a transmission line 3 at the loop side being the 1st transmission line and a 2nd frame 11 is circulated in a transmission line 7 of a line side being a 2nd transmission line. Then a signal time slot 27 and a communication time slot of a frame 11 received from the line are separated in the station 1 sending a data to the loop and the data are loaded and transmitted on the time slot of the frame 9 of other loop respectively. Thus, it is not required for the station 1 receiving the data from the loop to provide a demultiplex circuit for the signal time slot 27 and the circuit scale is reduced as a whole.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) TECHNICAL FIELD The present invention relates to loop communication systems.

(Prior Art) With the development of the information society, various network systems have been developed that interconnect multiple information systems (stations) via data transmission paths to realize more advanced information processing.

Among them, a loop communication system as shown in FIG. 7 is used. A loop communication system consists of a loop side and a line side, and the loop side consists of multiple stations 1 (1-1...1
-n) are connected in a loop by a transmission line 3, and the line side is connected to each station 1 and terminal equipment 5 (5-1...5-n) such as a private branch exchange (PBX) or a time division multiplexer (TDM). ) are connected to each station 1 by a transmission line 7 via an interface (not shown). One of the stations 1 is a control station 1-1.

On the loop side, a frame 9 as shown in FIG. 8 circulates on the transmission path 3, and communication between the stations 1 is performed using the frame 9. On the line side, frames 11 as shown in FIG.
Communication between them is performed using frames 11. Communication between the terminal devices 5 is carried out via the transmission path 3 with data loaded in frames 11 to 9.

Frame 9 rotates every 125 seconds and is composed of a plurality of time slots. Here, 1 time slot is 64k
Corresponds to a bps line. These multiple time slots are allocated to a synchronization area 13, a control information area 15, and a line switching area 17.

The synchronization area 13 indicates the beginning of frame 9 and the control information area 1
5. Allocate a unique pattern that does not appear in the circuit switching area 17, thereby synchronizing the frame 9.

The control information area 15 is an area for exchanging control information such as line allocation between the control station 1-1 and the station 1.

Furthermore, the control station 1-1 transmits line setting data to each station 1 using the control information area 15 during system configuration, and each station 1 enables communication between the terminal devices 5 based on the received line setting data. .

The format of the control information area 15 is shown in FIG. The control information area 15 includes an air blockage control area 19 and a destination information area 21.
, a source information area 23, and an information area 25.

An air blockage control area 1 indicates whether this area is in use or not, a destination information area 21 indicates the destination station 1, and a source information area 2
3 indicates the transmission source station 1, and information between the stations 1 is stored in the information area 25.

The circuit switching area 17 is an area allocated for communication between the terminal devices 5.

The transmission speed of frame 11 shown in FIG. 9 is 2.048 Mb.
ps, eight frames 11 are bit multiplexed and sent to station 1.
and the terminal device 5.

This frame 11 consists of 32 time slots.

The time slot No. 0 is a signal time slot 27, and the signal time slot 27 consists of 8 bits. 1
The bit (F bit) is 125μsec and frame 11
Used as a synchronization bit.

The second bit (MF bit) is a multi-frame synchronization bit, and the multi-frame synchronization pattern '0111111
Repeat step 1'. The third bit (S bit) is terminal device 5
This is a bit that notifies you of a failure. 4th to 8th bits (
One bit is assigned to each channel (A bit) and carries channel control data. However, the 4th to 8th bits (A bit) of multiframes 1 and 8@
is not specified.

Time slots 1 to 15 and 17 to 31 of frame 11 are loaded with communication data such as voice or data.
Corresponds to channels 1-30. Time slot number 16 is not specified.

Data from the terminal device 5 mounted on the frame 11,
It is mounted on the frame 9 and communicates with other terminal devices 5 via the transmission line 3. At this time, if there is a one-to-one connection between the terminal devices 5, a transparent line can be provided by allocating 32 time slots in the line switching area 17 of frame 9, which is the number of time slots in frame 11.

However, if it is required to change the connection destination for each channel, the signal time slot 27 is required for each connection destination.
It will also be necessary to transfer the information. In this case, a circuit for extracting a specific A bit from the signal time slot 27 on the receiving side is required only at the connected destination. There are 30 circuits that extract a specific A bit when the destination needs to be changed for each channel.
It becomes necessary. Therefore, there was a problem that the circuit scale increased.

(Problem to be Solved by the Invention) In communication between terminal devices connected to a station, when changing the connection destination in units of channels, it becomes necessary to transfer the signal time slot for each connection destination, and the reception A circuit for extracting a specific A bit from a signal time slot is required only at the other end of the connection, which poses a problem in that the circuit size increases.

The present invention has been made in view of these problems, and an object of the present invention is to provide a loop communication system with a reduced circuit scale.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a system in which a plurality of stations are connected by a loop-shaped first transmission path, and a first frame circulates around the first transmission path,
In a loop communication system, each of the stations and a terminal device are connected by a second transmission path, and a second frame in which communication data and control data are separately loaded is exchanged in the second transmission path. includes a first recognition unit that recognizes communication data and control data included in the second frame received from the second transmission path; and communication data and control data that are recognized by the first recognition unit. a first transmitting means for loading the first frame into separate time slots and transmitting the first frame to the first transmission path; a second recognition means for recognizing communication data and control data; and a second recognition means for mounting communication data and control data recognized by the second recognition means in the second frame and transmitting the same to the second transmission path. It is characterized by comprising a transmitting means.

(Operation) In order to achieve the above object, the present invention provides that the first transmitting means loads the communication data and control data recognized by the first recognition means in separate time slots of the first frame, and Since the first frame is transmitted over the transmission path, the station receiving the first frame does not need the same number of control data separation circuits as the number of connected partners, reducing the circuit scale.

(Example) An example of the present invention will be described in detail below based on the drawings.

The loop communication system of this embodiment is similar to that shown in FIGS. 7 to 9, and the first frame 9 shown in FIG. 8 circulates on the transmission path 3 that is the first transmission path. However, the second transmission line 7, which is the second transmission line, has a second transmission line shown in FIG.
frames 11 are coming and going.

The configuration of station 1 will be explained.

FIG. 2 is a block diagram showing the general configuration of station 1. Station 1 includes a receiving section 29, a frame control section 31, a transmitting section 33, a transmission/reception control section 35, a line interface 37, and a CPU 39.
, memory 41.

The receiving section 29 extracts a clock from the serial data on the transmission line 3 and outputs the received clock and received data (serial) to the frame control section 31.

The transmitter 33 receives the transmit data and the transmit clock from the frame controller 31, and transmits the transmit data (serial) synchronized with the transmit clock onto the transmission line 3.

The frame control section 31 detects the beginning of the frame 9 from the received data (serial) inputted from the receiving section 29, and outputs the time slot number and the corresponding received data (parallel) to the transmission/reception control section 35. It also processes transmission data (parallel) input from the transmission/reception control section 35 and outputs a transmission clock and transmission data (serial) to the transmission section 33 .

The transmission/reception control unit 35 uses the received data and time slot number received from the frame control unit 31 to determine the control information area 15.
and read circuit switched area 17. Control information area 15
Control information is exchanged with the control station 1-1 from the data in the line switching area 17 and the time slot number is output to the line interface 37. In addition, the transmission data output from the line interface 37 is sent to the frame control unit 3.
Send to 1.

The line interface 37, which is the main part of the first recognition means, the first transmission means, the second recognition means, and the second transmission means, uses data input from the transmission/reception control section 35 to communicate with the terminal device 5.
The data assigned to the
and sends it to the terminal device 5 (not shown). Further, data inputted from the terminal device 5 via the transmission path 7 is incorporated into data sent to the transmission/reception control section 35 and output.

The CPU 39 sets initial values in each register during system configuration. Further, the CPU 39 controls the transmission/reception control unit 35 to transmit and receive control information stored in the control information area 15.

The memory 41 is used as a buffer for storing a control program for operating the CPU 39 and for transmitting and receiving data between the CPU 39 and the transmission/reception control section 35.

Next, details of the frame control section 31, reception control section 35, and line interface 37 of the station 1 will be explained.

FIG. 3 is a block diagram showing the configuration of the frame control section 31. The frame control section 31 includes a serial-to-parallel conversion section 43, a latch section 45, a word counter 47, a word synchronization section 49, a slot counter 51, a frame synchronization section 53, selector 55
, a C bit insertion section 57, a frame transmission control section 59, and a parallel/serial conversion section 61.

The serial-to-parallel converter 43 receives received data and a receive clock from the receiver 29 (see FIG. 2), converts the received data into serial-to-parallel, and outputs the serial-to-parallel converter to the latch section 45.

The word counter 47 creates a word clock from the received clock and outputs the word clock to the latch section 45, word synchronization section 49, slot counter 51, and transmission/reception control section 35 (see FIG. 2).

The latch section 45 latches the output of the serial/parallel converter 43 at the timing of the word clock output from the word counter 47 . The latch section 45 outputs data to the word synchronization section 49, the frame synchronization section 53, and the selector 55.

The word synchronization unit 49 detects a difference of 2 in the C bit in order to establish word synchronization. If an error in the C bit is detected several times in a row, it is determined that the word synchronization has been lost. do.).

The word out-of-sync detection signal is output to the word counter 47. When the word counter 47 receives the word out-of-synchronization detection signal, it shifts the timing to the latch section 45 by one bit and outputs it. As a result, the latch section 45 outputs the data shifted by 1 bit to the word synchronization section 49. The word synchronizer 49 further checks the C bit of this data. Repeat the above operation until word synchronization is established.

When the frame synchronization unit 53 detects the beginning of frame 9 from the data input from the latch unit 45, it initializes the slot counter 51.

The slot counter 51 is initialized by the output of the frame synchronizer 53 and counts the word clock generated by the word counter 47 to detect the timing of each time slot.

The output of the slot counter 51 is output as a time slot number to the transmission/reception control unit 35 together with the word clock and received data.

On the other hand, the C bit insertion section 57 inserts a C bit into the transmission data sent from the transmission/reception control section 35 and sends the transmission data to the selector 55.

The selector 55 mounts the transmission data sent from the C bit inserting section 57 in a time slot according to instructions from the frame transmission control section 59 and sends it to the parallel-to-serial conversion section 61 . Note that when there is no transmission data from the C bit inserting section 57, the selector 55 selects the data received via the serial/parallel conversion circuit 43 and the latch section 45 and supplies it to the parallel/serial conversion circuit 61.

Frame transmission control section 59 gives an instruction to select data from C bit insertion section 57 to selector 55 in response to a transmission request sent from transmission/reception control section 35 .

The parallel-to-serial conversion circuit 61 performs parallel-to-serial conversion on the transmission data sent from the selector 55 and outputs the result.

FIG. 4 is a block diagram showing the configuration of the transmission/reception control section 35. The transmission/reception control section 35 includes a control information transmission/reception section 63, a selector 65, a delay circuit 67, a boat control section 69, and a selector 71.

During system configuration, the CPU 39 (see FIG. 2) sets the start time slot number and end time slot number of the control information area 15 in the registers in the control information transmitting/receiving section 63.

When the CPU 39 is notified by the control information transmitting/receiving unit 63 that the packet has been received, the CPU 39 stores the packet in the control information receiving area (receiving buffer) on the memory 41 and processes the received packet. Furthermore, when transmitting to another station, the packet is stored in advance in the control information transmission area (transmission buffer) on the memory 41, and the control information transmitting/receiving section 63 is notified that there is a packet to be transmitted.

The control information transmitting/receiving unit 63 determines the start and end of the control information area 15 by comparing the start time slot number and end time slot number of the control information area 15 set by the CPU 39 with the time slot number input from the frame control unit 31. know. Control station 1- using control information area 15
1 and sends and receives control information.

Furthermore, the control information transmitting/receiving section 63 always controls the control information area 1.
The blockage control area 19, destination information area 21, and source information area 23 of No. 5 are monitored. When receiving data from another station, if a packet indicating the own station is detected in the destination information area 21, the CPU 39 is notified that the packet has been received. Packets not addressed to the mortar station and gaze exchange area 17 are output to the selector 71 as they are.

Also, when transmitting data to another station, the control information transmitting/receiving section 6
3 is notified by the CPU 39 that there is a transmission packet. When the control information transmitting/receiving unit 63 detects an empty state (a packet that is not in use) in the empty/busy control area 19 of the control information area 15, it transmits a transmission packet. Freeing used space (
The sending station performs the blocking and emptying of the blockage control area 19.

The delay circuit unit 67 adjusts the amount of delay of the output from the control information transmitting unit 63 by:A between the line interface 37 connected to the boat and the one having the maximum delay.

The boat control section 6 receives the control information transmitting/receiving section 63 and the selector 65 according to the transmission request signal from each line interface 37.
and operates the selector 71.

The selector 65 selects transmission data output from each line interface 37 according to instructions from the boat control section 69.

Selector 71 selects transmission data output from selector 65 and delay circuit 67 according to instructions from boat control section 69 .

The line interface 37 will be explained with reference to FIGS. 1, 5, and 6.

FIG. 1 is a block diagram showing the configuration of the line interface 37. The line interface 37 includes a reception frame memory 73, a selector 75, a reception communication path MA P 77, a reception control path MAP 79, a line transmission time slot counter 81, and a line transmission multiplier. Frame counter 83, line transmission bit counter 85, selector 87, shift register 8
9, control bit generation section 91, selector 93, parallel/serial conversion section (P/5) 95, serial/parallel conversion section (S/P) 97, multiframe detection section 101, line reception multiframe counter 103, line reception time slot counter 105,
Loop transmission time slot counter 107, transmission channel MAP 109, transmission control path MAP 111, selector 11
3. It consists of a transmission frame memory 115.

The line transmission time slot counter 81 counts the time slot number of frame 11 and calculates the reception channel MAP 7.
7 and the reception control path MA P 79.

The line transmission multi-frame counter 83 counts the multi-frame number of frame 11 and reads the reception control path MA P
? Output to 9.

Line transmission bit counter 85 counts the bit number of frame 11 and outputs it to reception control path MAP 79 and selector 87.

The reception channel MAP 77 is composed of memory and is written by the CPU 39 (see FIG. 2) during system configuration.

The reception channel MAP 77 shows the time slot number of frame 9 on the loop side that is received and the time slot number of frame 11 on the line side in which the data is loaded and transmitted.

As shown in FIG. 5(a), the time slot number of frame 11 on the line side is written as the address, and the time slot number of frame 9 on the loop side corresponding to the address is written as the data. Since the address "00" corresponding to time slot No. 0 of frame 9 is assigned by the reception control path MAP, "0" is written in the data of the reception channel MAP, and the time slot of frame 11 is not assigned. In addition, frame 9 also applies to address "16" corresponding to the unspecified 16th time slot of frame 11.
No time slots are assigned.

The reception channel MA P 77 receives data input from the line transmission time slot counter 81 from "1 to 15.17".
31'', the time slot number of the corresponding frame 9 is output to the selector 75 using it as an address.

The reception control path MAP79 is composed of a memory, and is written by the CPU 39 during system configuration.

The reception control path MAP 79 indicates the time slot number of the frame 9 on the loop side to be received, and the multiframe number and bit number of the frame 11 on the line side in which the data is loaded and transmitted.

Here, since the control data is loaded in the 0th time slot, the loading location can be determined by specifying the multiframe number and bit number (9th
(see figure).

As shown in FIG. 5(b), the address consists of 6 bits, the upper 3 bits indicate the multiframe number of frame 11 on the line side in binary notation, and the lower 3 bits indicate the signal of frame 11 on the line side. The bit number of the time slot 27 is shown in binary notation. That is, multiframe numbers "1" to "8" correspond to address numbers r 0OOJ ("0" in decimal notation) to r fill ("7" in decimal notation), and bit numbers "1" to "8" ” is address number r
0OOJ (“0” in decimal system) to r IIIJ
(corresponds to "7" in decimal system).

Since multiframe numbers 1 and 8 do not contain A-bit information (see FIG. 9), the time slot of frame 9 is not allocated.

When the data input from the line transmission time slot counter 81 is "0", the reception control path MAP 79 uses the data input from the line transmission multi-frame counter 83 as the upper three bits of the address, and reads the data from the concave line transmission bit counter 85. The time slot number of frame 9 corresponding to the address is output to the selector 75, with the input data as the lower three bits of the address.

The selector 75 outputs the time slot number as an address to the reception frame memory 73. When writing,
The time slot number output from the transmission/reception control unit 35 is output to the reception frame memory 73. When reading,
The time slot number output from the reception channel MAP 77 or the reception control path MAP 79 is stored in the reception frame memory 7.
Output to 3. That is, the line transmission time slot counter 81 indicates the time slot number "1~15.17~31".
”, the selector 75 selects the output of the reception channel MAP77, and when the line transmission time slot counter 81 indicates the time slot number “0”, the selector 75 selects the output of the reception control path MAP79.

The reception frame memory 73 is a dual-port memory with a capacity to store one frame of reception data input from the transmission/reception control section 35. When writing, selector 75
With the timeslot number input from as the address,
The received data input from the transmission/reception control section 35 is written. At the time of reading, data to be transmitted to the line side is read using the time slot number manually entered by the selector 75 as an address.

The selector 87 includes a line transmission time slot counter 8.
When 1 indicates the time slot number "0", the time slot in which the control data is loaded is input from the reception frame memory 73. This time slot consists of 8 bits, and the selector 87 selects any A bit from No. 0 to No. 7 of the time slot received from the loop side based on the output of the line transmission bit counter 85.

The selector 87 is a line transmission time slot counter 81
While indicates "0", the output of the receive frame memory 73 is selected repeatedly five times, and the 5 A bits are stored in the shift register 89.

Shift register 89 stores 5 A bits which are sequentially output from selector 87 five times.

A control bit generation circuit 91 generates each control bit of FSMFSS (see FIG. 9).

The selector 93 selects the output of the reception frame memory 73 while the line transmission time slot counter 81 indicates the time slot number [1 to 15. The outputs of register 89 and control bit generation circuit 91 are selected.

A parallel/serial converter CP/5) 95 converts the output of the selector 93 into serial data and sends the serial data to the line side.

A serial/parallel converter (S/P) 97 converts serial data from the line side into parallel data.

Multiframe detection section 101 monitors the second MF bit of time slot No. 0, and initializes line reception multiframe counter 103.

The line reception multi-frame counter 103 indicates frame 11.
The transmission control path MAP is calculated by counting the multi-frame number of
Output to III.

The line reception time slot counter 105 is frame 11.
Count the time slot number and map the transmission path
109 and the transmission control path MAP111.

Loop transmission time slot counter 107 counts the time slot number received from the loop side and outputs it to selector 113, line reception time slot counter 105, and line reception multiframe counter 103.

The transmission channel MAP 109 is composed of memory, and is written by the CPU 39 during system configuration.

The transmission channel MAP 109 indicates the time slot number of frame 11 on the line side that is received and the time slot number of frame 9 on the loop side in which the data is loaded and transmitted.

As shown in FIG. 5C, the address is the time slot number of frame 11, and the data is the time slot number of frame 9 on the loop side corresponding to the address.

Since the address "00" corresponding to time slot No. 0 of frame 11 is assigned by the transmission control path MAP III, "0" is written in the data of the transmission channel MAP 109, and the time slot of frame 9 is not assigned. Also, for the address "1B" corresponding to the 16th time slot of frame 11, which is not specified, frame 9
No time slots are assigned.

In the transmission channel MAP 109, the line transmission time slot counter 105 indicates the time slot number "1~15.17~
31", the line reception time slot counter 1
The time slot number of the corresponding frame 9 is output to the selector 113 using the data input from 05 as an address.

The transmission control path MAP111 is composed of a memory, and is written by the CPU 39 during system configuration.

The transmission control path MAP 111 indicates the multiframe number of the frame 11 on the line side that is received and the time slot number of the frame 9 on the loop side in which the data is loaded and transmitted.

Here, since the control data is loaded in the time slot No. 0, the time slot in which it is loaded can be determined by specifying the multiframe number (see FIG. 9).

As shown in FIG. 5(d), the address is the multiframe number of frame 11, and the data is the time slot number of frame 9 on the loop side corresponding to the address.

Multi frame numbers “1” to “8” are address numbers “
Corresponds to numbers 0 to 7. Since multiframe numbers 1 and 8 do not contain A-bit information, the time slot of frame 9 is not allocated.

When the line transmission time slot counter 105 indicates time slot number "0", the transmission control unit MAP III
The time slot number of the corresponding frame 9 is output to the selector 113 using the data input from the line transmission multi-frame counter 103 as an address.

Selector 113 outputs the time slot number as an address to transmission frame memory 115.

When reading, loop transmission time slot counter 1
The time slot number output from 07 is output to the transmission frame memory 115. At the time of writing, the time slot number output from the transmission channel MAP 109 or the transmission control path MAP 111 is output to the transmission frame memory 115. That is, the line reception time slot counter 105 indicates the time slot number "1~15.17~31".
, the selector 113 selects the transmission channel MAPI09.
Select the output of line reception time slot counter 10
5 indicates time slot number "0", selector 11
3 selects the transmission III path MAP III (7) output.

The transmission frame memory 115 is a dual-port memory with a capacity to store one frame of transmission data. When writing, the serial/parallel conversion circuit (S/P) 97 uses the time slot number input from the selector 113 as an address.
Writes the transmission data input from. At the time of reading, data to be transmitted to the loop side is read using the time slot number input from the selector 113 as an address. When reading control data as transmission data, A1-A30
8 bits of the signal time slot 27 of frame 11 containing any 5 bits are selected and output.

Next, the operation of station 1 will be explained.

The operation when transmitting data from the loop side to the line side will be explained.

The reception frame memory 73 receives the reception data input from the transmission/reception control section 35 using the time slot number inputted from the transmission/reception control section 35 as an address. When the data input from the line transmission time slot counter 81 is "1~15.17~31", the receiving channel MA
P77 outputs the corresponding loop side time slot number to the selector 75, and the selector 75 outputs the time slot number to the reception frame memory 73. The reception frame memory 73 outputs the reception data corresponding to the time slot number to the selector 93.
is output to the parallel-to-serial converter (P/5) 93.

When the data input from the line transmission time slot counter 81 is "0", the reception control path MAP 79 determines the corresponding loop side from the data input from the line transmission multiframe counter 83 and the line transmission bit counter 85. The time slot number is output to the selector 75, and the selector 75 outputs the time slot number to the reception frame memory 73. The reception frame memory 73 outputs the reception data corresponding to the time slot number to the selector 87.

The selector 87 selects the A bit from the data output by the reception frame memory 73 according to the count of the line transmission bit counter 85, and outputs it to the shift register 89.

While the line transmission time slot counter 81 indicates "0", the above operation is repeated five times, and the output of the selector 87 is sequentially stored in the shift register 93, and the 5 A bits are stored in the shift register 93.

The 5 A bits output from the shift register 89 and the F, MF, and S bits generated from the control bit generator 91
The respective control bits are output together to the selector 93, and from the selector 93 to the parallel-to-serial converter (P/5) 93.

The parallel/serial converter (P/5) 93 converts the input data into serial data and sends it to the line.

The operation when transmitting data from the line side to the loop side will be explained.

Serial data on the line side is serial/parallel converter (S/P) 97
The data is converted into parallel data and output to the transmission frame memory 115 and the multi-frame detection circuit 101.

The multiframe detection circuit 101 monitors the MF of the second bit of the 0th time slot, and initializes the line reception multiframe counter 103.

When the line transmission time slot counter 105 indicates a time slot number "1~15.17~31", the transmission channel MAP 109 outputs the corresponding loop side time slot number to the selector 113, and the selector 113 The number is output to the transmission frame memory 115. The transmission frame memory 115 converts the communication data loaded in that time slot number into a parallel/serial converter (S/P).
Enter from 97.

Furthermore, when the line transmission time slot counter 105 indicates the time slot number "0", the transmission control path MAP II
I outputs the loop side time slot number corresponding to the multiframe number input from the line reception multiframe counter 103 to the selector 113;
outputs the time slot number to the transmission frame memory 115.

The transmission frame memory 115 receives control data loaded in the time slot number from the parallel/serial converter (S/P) 97.

When reading data from the transmission frame memory 115,
Selector 113 is loop transmission time slot counter 1
The time slot number output from 07 is selected and output to the transmission frame memory 115, and the transmission frame memory 115 outputs data using the time slot number as an address.

Referring to FIG. 6, the receiving channel MA P 77, the receiving control section MA P 79, the transmitting channel MAP 109, and the transmission controlling section MAP 111 will be explained in more detail.

For the reception channel MAP 77 and the transmission channel MAP 109 of the two communicating stations, a common loop-side time slot is assigned to the line-side time slot in which communication data is loaded, respectively.

For the reception control unit MAP79 and the transmission control unit MAPIII of the two communicating stations, time slots dedicated to transmission on different loop sides are assigned to time slots on the line side in which control data is loaded, respectively.

For example, a method of allocating a channel 1 line (a communication path for transmitting and receiving voice or data) between the terminal device 5-2 and the terminal device 5-3 will be explained.

Channel 1 of frame 11 on the line side is assigned the 100th time slot in the circuit switching area of frame 9 on the loop side.

Reception channel MAP of each station 1-2 and station 1-3
77 and transmission channel MAP 109, the time slot number of frame 11 on the line side corresponding to channel 1 is number 1, so the time slot number r100J of frame 9 on the loop side is written in the address "Ol". This makes it a terminal bag! 5-2 and terminal device 5-31■1
11th episode data can be loaded on channel l and communicated.

Next, channel 1 is connected between the terminal device 5-2 and the terminal device 5-3.
The allocation of time slots for transmitting and receiving the A1 bit, which is the control data of channel 1, when the line is allocated will be explained.

Assign time slot No. 200 in the circuit switching area of frame 9 as a transmission-only time slot for station 1-2,
Time slot No. 201 in the circuit switching area of frame 9 is assigned as a time slot dedicated to transmission for stations 1-3.

In the transmission control unit MAPIII of station 1-2, the A1 bit is included in the second multiframe, so the address of the A1 bit is "0■". Therefore, the address "吋"
On the other hand, the time slot number r of frame 9 on the loop side
200J is written.

In the reception control unit MAP79 of station 1-3, since the A1 bit is the 4th bit of the second multiframe,
The address of the bit is r0OIIOIJ (binary number). Therefore, the time slot number r 200J of frame 9 on the loop side is written to address r 0OIIOIJ.

This allows communication from the terminal device 5-2 to the terminal device 5-3 with the channel 1 control data (A1 bit) loaded in the 200th time slot.

Furthermore, in the transmission control unit MAPIII of the station 1-3,
The time slot number 201 of frame 9 on the loop side is written to the address "Ol" indicating the second multiframe corresponding to the A1 bit.

In the reception control unit MA P 79 of the station 1-2, for the address r0OIIOIJ (binary number) indicating the 4th bit of the 2nd multiframe corresponding to the A1 bit,
Time slot number of frame 9 on the loop side, "2"
is written.

This allows communication from the terminal device 5-3 to the terminal device 5-2 by placing the control data (A1 bit) of channel 1 in time slot No. 201.

Furthermore, a method of allocating a channel 2 line (a communication path for transmitting and receiving voice or data) between the terminal device 5-2 and the terminal device 5-4 will be explained.

The 101st time slot in the circuit switching area of frame 9 on the loop side is assigned to channel 2 of frame 11 on the line side.

Receive channel MA of each station 1-2 and station 1-4
In P 77 and the transmission channel MAP 109, the time slot number of frame 11 on the line side corresponding to channel 1 is number 2, so the time slot number r101J of frame 9 on the loop side is written in the address "mouth 2". Thereby, communication between the terminal device 5-2 and the terminal device 5-4 can be carried out by carrying the call data on the channel 2.

Next, allocation of time slots for transmitting and receiving the A2 bit, which is control data for channel 2, will be explained.

Time slot No. 200 in the circuit-switched area of frame 9 is assigned as a transmission-only time slot for station 1-2, and time slot No. 202 in the circuit-switched area of frame 9 is assigned as a transmission-only time slot for station 1-4. Assign time slots.

In the reception control unit MAP79 of station 1-4, since the A2 bit is the 5th bit of the second multiframe, the A2
The address of the bit is roollloJ (binary number). Therefore, the time slot number r200J of frame 9 on the loop side is written to address r001110J.

This allows communication from the terminal device 5-2 to the terminal device 5-4 with channel 2 control data (A2 bit) loaded in time slot number 200.

In the transmission control unit MAPIII of the station 1-4, the A2 bit is included in the second multiframe, so the address of the A2 bit is "Ol". Therefore, the address “01
”, the time slot number r202J of frame 9 on the loop side is written.

In the reception control unit MAP79 of station 1-2, since the A2 bit is the 5th bit of the second multiframe, the A2
The address of the bit is roollloJ (binary number). Therefore, the time slot number r202J of frame 9 on the loop side is written to address r001110J.

This allows communication from the terminal device 5-4 to the terminal device 5-2 by placing the control data (A2 bit) of channel 2 in the 202nd time slot.

In this way, in the station 1 transmitting to the loop side, the signal time slot 27 and the communication time slot of the frame 11 received from the line side are separated and loaded into the time slots of frame 9 on separate loop sides. Send.

At this time, the loop-side time slot assigned to the signal time slot 27 differs depending on each station. In each station, the number of multiframes containing A-bit information in the signal time slot 27 is six, numbered 2 to 7, so for these six signal time slots 27, six different loop side Allocate a timeslot for transmission only.

In addition, in the station 1 receiving from the loop side, in order to extract an arbitrary A bit, the reception control unit MAP 79 specifies the time slot number of the frame 9 on the loop side in which the A bit is installed and the A bit. The multi-frame number and bit number on the line side are stored. station 1
Then, this reception control unit MA P 79 extracts and assembles the A bit corresponding to the channel assigned to its own station, and further assembles the signal time slot 27 with other control bits (F, MF, S). frame 1
1 and transmits it to the terminal device 5.

In this way, in this embodiment, station 1 transmitting to the loop side:
Since the signal time slot 27 received from the line side and the communication time slot are separated and transmitted to the loop side, station 1 receiving from the loop side does not need a separation circuit for the signal time slot 27. (The overall circuit scale is reduced.

Furthermore, station 1 that transmits to the loop side allocates the time slot 27 for signals received from the U-line side to the loop side for transmission only, so station 1 that receives from the loop side is not related to its own station. Control for returning control data from the reception frame memory 73 to the transmission frame memory 115 is no longer necessary, and the circuit scale is further reduced.

[Effects of the Invention] As explained above, according to the present invention, a loop communication system with a reduced circuit scale can be provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of the line interface of this embodiment, FIG. 2 is a block diagram showing the configuration of the station of this embodiment, FIG. 3 is a diagram showing the configuration of the frame control section of this embodiment, and FIG. 4
The figure shows the configuration of the transmission/reception control section of this embodiment, and FIG.
a) is a diagram showing the reception channel MAP of this embodiment, and FIG.
b) is a diagram showing the reception control path MAP of this embodiment, and FIG.
c) is a diagram showing the transmission communication path MAP of this embodiment, and Fig. 5 (
d) is a diagram showing the transmission control path MAP of the present embodiment, a diagram showing the correspondence of frames in , and Fig. 6(a) is a diagram showing the transmission control path MAP of the present embodiment.
FIG. 6(b) is a diagram showing the reception channel MAP, reception control path MAP, transmission channel MAP, and transmission control path MAP of station 1-2 in this embodiment. M
A diagram showing an AP, a transmission communication path MAP, and a transmission control path MAP,
FIG. 6(c) is a reception channel map of station 1-4 in this embodiment.
. Reception control path MAP, transmission communication path MAP, transmission control path MA
7 is a diagram showing the configuration of a loop communication system, FIG. 8 is a diagram showing frames on the loop side, and FIG. 9 is a diagram showing frames on the line side. 3.7...Transmission path, 9.11...Frame, 51.
... Slot counter, 73 ... Reception frame memory, 77 ... Reception communication path MAP, 79 ... Reception control path MAP 181 ... Line transmission time slot counter,
83... Line transmission multi-frame counter, 85...
- Line transmission bit counter, 103... Line reception multi-frame counter, 105... Line reception time slot counter, 107... Loop transmission time slot counter, 109... Transmission channel MAP, 111...
・Transmission control path MAP, 115...Transmission frame memory Applicant Toshiba Corporation Patent attorney Suyama Sa - Atsushi 2] (a) (b) Figure 5 (C) (d) (a) Station 1- 2 (b) Month 1-5 Ayu 7 Figure

Claims (2)

[Claims] (1) A plurality of stations are connected by a loop-shaped first transmission path, a first frame circulates on the first transmission path, and each station and a terminal device are connected by a second transmission path, 2
In a loop communication system in which a second frame carrying communication data and control data separately is sent back and forth on a transmission path, each station transmits a second frame to the second frame received from the second transmission path. a first recognition means for recognizing communication data and control data mounted thereon; and a first recognition means for loading the communication data and control data recognized by the first recognition means into separate time slots of the first frame, and a first transmitting means for transmitting to a first transmission path; a second recognition means for recognizing communication data and control data included in the first frame received from the first transmission path; a second transmitting means for mounting communication data and control data recognized by the second recognition means in the second frame and transmitting the same to the second transmission path; (2) In the first transmitting means, the control data is loaded in different time slots depending on the station of the first frame, and in the second transmitting means, the control data is loaded in the first frame of the control data to be transmitted to the own station. The mounted position in the first frame is memorized, and the control data sent to the own station is extracted from the control data received from the stored position and the second frame is loaded.
2. The loop communication system according to claim 1, wherein the loop communication system transmits to a transmission path.