JPH02220534A - Distributed processing type packet exchange - Google Patents

Abstract

PURPOSE:To make the use of a packet buffer memory efficient and to shorten the processing time by controlling the transmission of a packet to the line control section of an opposite party and its own terminal equipment in each line control section. CONSTITUTION:An exchange processing processor EXP 141(142) is provided with line control sections CCT1011-10n1(1021-10n2) connecting to bidirectional data bus 131(132), a call control section 111(112) applying the setting/interruption of a logic channel when a packet is transmitted/received with other EXP via a system bus 15 and a control section 121(122) to the bus 15. Each CCT uses a packet buffer area having a packet length decided by a terminal equipment via a line 30(40) to transfer the packet received from the terminal equipment in division or continuously in matching with the packet length of the CCT of each transmission opposite party, and every time a packet reception CCT is stored in a buffer area, it is sent to the terminal equipment as one packet.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a distributed processing type packet switch.

(Prior Art) Conventionally, in a line control unit of a distributed processing type packet switch that performs packet switching processing by separating data packets and call control packets, each bucket buffer area of the packet buffer memory has the same length, and When a line controller connected via a bidirectional data bus transfers a received packet to a line controller that accommodates the destination line, the data packet stored in the bucket buffer area is transferred once. Therefore, in order to accommodate terminals with different packet lengths in a conventional distributed processing packet switch, the line controller accommodating the terminals must be transferred to the bucket buffer area of the other party's line controller. The stored data packets are once rewritten in the memory of the main memory control unit, and then divided or assembled to the packet length of the other party's line control unit using program processing, and each packet is returned to the packet buffer memory and sent to the other party's line control unit. It was supposed to be transferred.

[Problem to be solved by the invention]

In the conventional distributed processing type packet switch mentioned above, the length of each bucket buffer area of the packet buffer memory of the line control unit is the maximum packet length allowed by the packet network, so it is shorter than the maximum packet length. When sending and receiving packets, the usage efficiency of the packet buffer memory is poor, and in order to combine multiple packets into one packet or to exchange packet lengths to divide long packets, data packets in the packet buffer memory must be The data must be moved to the memory of the main control section of the line control section, and disassembly and assembly must be performed there by program processing, which has the drawback of taking a long processing time.

[Means to solve the problem]

The distributed processing type packet switch of the present invention includes a packet buffer memory configured of a plurality of bucket buffer areas each having a packet length predetermined by the accommodated line, and a packet buffer memory configured to receive packets transmitted from a terminal. Then, means for detecting the packet length of the other party's line control unit to which the packet should be transferred; and means for detecting the packet length of the other party's line control unit to which the packet should be transferred; , means for dividing the packet into the length of the packet to be transferred to the other party's line controller and sequentially transferring it to the other party's line controller via a bidirectional data bus, and when the detected packet length is longer than the packet length of the own line controller; When the received packets are a series of packets with the same destination divided from one message, means for continuously forwarding the packets to the other party's line control unit until the packet length is reached; and receiving side line control. means for sending each data packet to the line as one packet each time the transfer of data packets to one packet buffer memory is completed upon receiving a notification of divisional transfer from the receiving side line control unit; Upon receiving the notification, all line control units have a means for successively storing the transferred packets in one packet buffer memory, and transmitting them to the line as one packet when the packet length of the packet buffer memory is reached. .

[Effect]

Each line control unit has a unique packet length that is predetermined by the terminal it accommodates, and the packet buffer memory is divided into a plurality of packet buffer areas each having the unique packet length as a unit, The line control unit that receives the packet from the terminal divides or continuously transfers the received packet to the line control unit accommodating the destination terminal according to the packet length of the line control unit. The line control unit on the receiving side, which receives the packets, collects them into one packet and sends them to the terminal each time storage is completed in the 51 bucket buffer areas, thereby efficiently using the packet buffer memory of all line control units. In addition, it is possible to eliminate the need for packet length conversion by program processing in the main control unit.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a distributed processing type packet switch according to the present invention, and FIG. 2 is a block diagram of a bidirectional data bus 13 within the switching processor 141 shown in FIG. The line control unit 10. , ~10n1, and FIG. 3 is a diagram showing the state of packet transfer between the packet buffer memory 2:11.232 of the line control unit '0++ and 10.2.

This embodiment consists of a loop-shaped system bus 15 and switching processors 14+ and 14□ connected thereto. The switching processor 14+ (142) is connected to the bidirectional data bus 13. (132) are connected to the line control units 1011 to 10. , l (1012 to 10n2), and a call control unit 11 . that sets/disconnects logical channels when transmitting/receiving packets to/from other switching processors via the system bus 15 . (item 2), a system bus control unit 121 (122) that controls transmission and reception of packets to and from the system bus 15, and a bidirectional bus Ml+ (132).
) The bus arbiter 27+ (
272). Line control unit 10. , -1
0. , are lines 301 to 30., respectively. , and accommodates a terminal (not shown) through the line 30. -30 and the line control units lO3, -10n, a level conversion unit 261. which adjusts the transmission level between them. ~26. ．． ．． , a transmission control section 25I, to 25o1 that processes frame-level transmission control procedures, and a packet buffer memory 233 consisting of a plurality of bucket buffer areas with a packet length predetermined by the terminal (not shown) accommodated therein. -23o1 and a buffer memory control unit that returns a unique packet length in response to the timing from other line control units, and controls writing of received packets to packet buffer memories 23° to 23n1 and reading during transmission. 24□ to 24o, and status bus control units 2111 to 21.21 that request the right to use the bidirectional data bus +3°. , detects the packet length of the destination line controller, and if the packet length is shorter than the packet length of the own line controller, sends a division transfer notification and divides the received packet into that packet length. If the packet is transferred to the destination line control unit or the received packet is one message divided into multiple packets and sent consecutively, the packet length of the destination line control unit is longer than the own line control unit. If the packet length is longer than the packet length, a continuous transfer notification is sent,
A data bus control unit 221 that continuously transfers a series of packets until the packet length reaches the destination line control unit and receives the transferred packets. ~22n, and a main control unit 20~20n that controls each of these units, specifies the destination line control unit of the received packet, and instructs to combine the transmitted packets based on the received division or continuous transfer notification.
Consisting of Line control unit 10 of exchange processing processor 14□
．． □ to 1On2 have exactly the same configuration.

Next, the operation of this embodiment will be explained with reference to FIG.

Line control section! When 011 receives the packet 36 transmitted from the line 301 to the line 302, the level converter 261
After converting the transmission level to a level for exchange processing at ゜, detecting a transmission error in the transmission control unit 2511, and correcting the error by instructing retransmission if there is an error, the buffer memory control unit 24□ The received packet is separated into a data packet and a call control packet and stored in the bucket buffer area 3 of the designated number of the packet buffer memory 23□1.
1 and the corresponding bucket buffer area (not shown) for call control packets, and the main control unit 20 indicates reception completion.
to notify. The main control unit 20□ determines the line control unit 10 that accommodates the destination line 302 of the received call control packet based on the logical channel number included in the header information of the received call control packet. , and the bus arbiter 27 . requests the right to use the data bus 291.

Bus arbiter 27. The line control unit 10. has been given permission to use the data bus 29 from the line control unit 10. , the data bus control unit 22 of
11 is a line control unit 102. The packet length is detected, and since the packet length is No., the line control unit +02. 3 data packets of the received packet stored in the packet buffer area 31 from the beginning.
The first data is divided into data packets 33. as the line control unit 102. Similarly, the second divided data packet 34. , third divided data packet 3
5. Transfer. This transferred data packet is transferred to the line controller 10. , are received by the data bus control unit 2221, and stored in the bucket buffer areas 43, 44, and 45 by the buffer memory control unit 2421, respectively.

Furthermore, the divided data reception packet 33. , 34□,
35. The data bus control unit 22□1 notifies the main control unit 2021 of the completion of the transfer operation for each transfer.
It gives an instruction to send a packet to line 30□. In response to this instruction, the buffer memory control unit 242I controls each divided data packet 331 . :]4+, 35+ are sequentially sent to the transmission control unit 25□. The sent packet is sent to the transmission control unit 252. An error detection code is added to each packet to become transmission packets 33o, 34a, and 35o, which are sequentially converted to a transmission level by a level converter 2621 and sent to the line 302.

In addition, the line control unit 1021 changes the line from the line 30° to the line 301.
A plurality of packets 37o, 38o, and 39o, in which one message is divided into unique packet lengths, addressed to the terminal are successively received and stored in the bucket buffer areas 47, 48, and 49 of the packet buffer memory 23□. and,
Line control unit 10. , firstly, the call control packet of the received packet 37° is forwarded to the line control unit 10. , and obtained the right to use the bidirectional data bus 291, and learned that the packet length of the line control unit lO0, was three times as long.
The line controller 10++ is notified of continuous transfer, and the call control packet of the received packet 37o and the received data packet 371 are transferred to the packet buffer memory 23. The line control unit 10++ stores the received data packet 37 in the bucket buffer area 32. Similarly, the received data packets 381.39+ are transferred to the bucket buffer area 32, and a series of received data packets 37□38, 39 . is stored, the data bus control section 22□ starts the main control section 20. The main control unit 20.1 then instructs the buffer memory control unit 2411 to transmit the transfer operation. In response to this transmission instruction, the buffer memory control unit 24,1 transmits the packets stored in the bucket buffer area 32 as one packet. Thereafter, this packet is added with an error detection code by the transmission control section 2511 and becomes a transmission packet 46, which is converted to a transmission level by the level conversion section 26□1 and sent to the line 301.

(Effects of the Invention) As explained above, the present invention uses a bucket buffer area with a packet length predetermined by the terminal accommodated in each line control unit, and transfers packets received from the terminal to the destination party. Each line is divided or continuously transferred according to the packet length of the line control unit, and the line control unit that receives the transferred packet sends it to the terminal as one packet each time it is stored in the bucket buffer area. The packet buffer memory of the control section can be used efficiently, and the processing time can be shortened by eliminating the need for packet length conversion by program processing in the main control section.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a distributed processing type packet switch according to the present invention, and FIG. 2 is a block diagram of an embodiment of the distributed processing type packet switch of the present invention. Bidirectional data bus 13. The line control units lO1-10. ．． . The block diagram of FIG. 3 is the line control unit 'O++, 102
．． packet buffer memory 23. , 232. FIG. lO□~10. ,,10. □~10n2---Line control unit, 11, 11□...Call control unit, +2. ,
122...System bus control unit, +3. , 13
．． ...Bidirectional data bus, 14,,142...
...Exchange processing processor, 15...
. . . System bus, 2011-20n1 . . . Main control unit, 21, , ~21. ．． ...Status bus control section, 22°~22o1...Data bus control section, 23□
~23n,...Packet buffer memory 24°~2
4o1...Buffer memory control unit, 25.1 to 25
o,...transmission control unit, 26.1-26.1...
Level converter, 27, 27□...Bus arbiter, 30, ~30o, 40. ~40n...Line, 3
3o~35°, 46......Transmission packet,
33, ~35□371~391...Received data packet, 36, 31°~39o...Received packet.

Claims (1)

[Claims] 1. One or more switching processors are connected by a loop-shaped system bus, and each switching processor performs call control over packets received from or transmitted to the line it accommodates. A line control unit separates or combines packets into data packets and controls the transmission and reception of packets, a call control unit performs setting/disconnection of logical channels when transmitting and receiving packets via the system bus, and a call control unit controls packet transmission to the system bus. In a distributed processing packet switch that includes a system bus control unit that controls transmission and reception, a bidirectional data bus that connects these units, and a bus arbiter that controls the granting of usage rights to the bidirectional data bus, A packet buffer memory consists of multiple packet buffer areas each having a predetermined packet length as a unit, and when a packet transmitted from a terminal is received, the packet length of the other party's line control unit to which the packet should be transferred is stored. If the detected packet length is shorter than the packet length of the own line control unit, the received packet stored in the packet buffer memory is divided into packet lengths of the other party's line control unit to be transferred and sequentially divided. , means for transferring to the other party's line control unit via a bidirectional data bus, and a series of identical destinations to which received packets are divided from one message when the detected packet length is longer than the packet length of the own line control unit. When the packet is a packet of Each time a packet transfer is completed, each data packet is sent to the line as one packet, and when a continuous transfer notification is received from the receiving side line control unit, the transferred packets are continuously transferred to one packet buffer area. 1. A distributed processing type packet switching system characterized in that all line control units have means for storing the packet as one packet and sending it out to the line as one packet when the packet length reaches the packet length of the packet buffer memory.