JPH02220130A - Logic circuit - Google Patents

Abstract

PURPOSE:To attain the high speed working of a logic circuit even with the multi-bit addition by using a terminal to input a carry signal receiving from a lower rank bit, a terminal to input the inverted carry signal, a terminal to output a carry signal to a higher rank bit, and a terminal to output the inverted carry signal. CONSTITUTION:The final stage circuit of a carry intelligent circuit is provided with the terminals to input a carry signal Ci received from a lower rank bit and its inverted signal CiN together with the terminals to output a carry signal Co to a higher rank bit and its inverted signal CoN respectively. In other words, the final stage of the carry intelligent circuit is formed with a gate having the small fan-in/fan-out frequency and with use of the signals SiN and CoN of signals Ci and Co respectively. Thus the working speed of the final stage is increased and the carry intelligent circuit can work at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed, low-power consumption logic circuit suitable for integrated circuits in general.

[Conventional technology]

As a conventionally known example, ``Ultrahigh Speed Compound Semiconductor Device'' (Baifukan, 1986. p281J) can be mentioned.

With the recent increase in the speed of integrated circuits for digital arithmetic operations, it is desired to increase the speed of adders, which are the most basic components of arithmetic operation circuits. The adder is not only a so-called adder that performs addition, but also a basic component of arithmetic units such as ALU and multiplier.
It controls the speed of logic LSI.

As is well known, the high-speed performance of a multi-bit adder is dominated by the high-speed performance of a carry signal. Conventionally, as a means to increase the carry propagation speed of a multi-bit adder, a carry look-ahead adder (Carry Lo
OK Ahead: CLA) is well known. Figure 2 shows an “ultrahigh-speed compound semiconductor device” (
Baifukan, 1986. It is a logic diagram of the 4-bit CLA described in p. 281). Pj=Aj■Bj AjsBj is the j-th bit augend.

[Problem to be solved by the invention]

The conventional technique shown in FIG. 2 has one problem in that when applied to a multi-bit adder, a sufficient increase in speed cannot be achieved. This will be explained below.

The delay time of the CLA circuit is the time from inputting the carry signal Ci from the lower bit to outputting the carry signal Co to the most significant bit, and is determined by the final stage circuit. For example, in the circuit shown in Figure 2, the AND gate L
3 and the delay time of OR gate L4. However, in the conventional circuit, this L3. Since L4 is a connection with a large fan-in number or fan-out number, the operating speed will be returned.

CLA circuits are often used connected in series, as in the 32-bit carry look-ahead circuit shown in Figure 3. Here, eight 4-bit carry look-ahead circuits are connected in series to form a 32-bit carry look-ahead circuit. It consists of In this case, Ci of the next CLA unit is connected to CO. Therefore, L3
has a fan-in number of 5. The fan-out number is 1, and L4 has a fan-in number of 5. The fan-out number is 4. Since gates with large fan-out and fan-in numbers are used in this way, the delay time of the CLA circuit is more than 10 times the delay time ti of a simple inverter circuit.

An object of the present invention is to provide a logic circuit that operates at high speed even in multi-bit addition.

[Means to solve the problem]

The above object is that the final floor circuit of the carry look ahead circuit has a terminal for inputting a carry signal from the lower bits and its inverted signal, and a terminal for outputting the carry signal and its inverted signal to the upper bits. This is achieved by configuring the structure.

[Effect]

In the present invention, by utilizing the carry signal from the lower bit and the inverted signal of the carry signal to the upper bit, the final stage of the carry look-ahead circuit is configured with a gate having a small fan-in number and a small fan-out number. . This makes it possible to speed up this final stage and speed up the one-digit look-ahead circuit.

〔Example〕

The present invention will be explained below using examples. The 4-bit carry look-ahead circuit of the first embodiment is shown in FIG. Carry signal C1, its inverted signal CiN, carry propagation width signal PJ
(j=1 4L carry generation signal G j (j=1
-4) as the input signal and carry signal C to the upper bit.
o, its inverted signal Co N-1 carry signal Cj (J
=1-3) is output. Here, P J w G j is defined by the following logical formula using the augend AJtBJ.

Gj=Aj-Bj...(1)P
j=AjOBj...(2)
This 4-bit carry look-ahead circuit consists of a 3-bit carry look-ahead circuit and a final stage. The 3-bit carry look ahead circuit uses the conventional circuit shown in FIG. 2, but the final stage circuit is different from the conventional circuit.

As the 3-bit carry look-ahead circuit, any circuit may be used as long as it has the same logic output as this logic diagram, and it will operate exactly the same as the conventional circuit.

Next, the operation of the final stage logic circuit will be explained.

First, derive the logical formula necessary to explain this logical operation. Using the general formula for the 0 carry signal, the following formula holds: Cj; Gj + Pj - Cj - 1... (3) where -Aj
eBJ is the j-th digit augend, and Cj is the j-th digit carry signal. Furthermore, the following equation can be easily obtained from equations (1) and (2).

Gj-Pj=O (4) By repeatedly using equation (3), the fourth digit carry signal C4 (=Co) is expressed by the following equation.

C4=G4+P4・[G3+P3・(G2+P2・(G
1 + P 1・C1))] =G4+P4・(G 3 + P 3・(G2+P2・
G1))+P4・P3・P2・Pl・Ci
...(5) Defining logical values R and S using the following equations,
R=G4+P4・(G3+P3・(G2+P2
・G1)) SmF3・P3・P2・PI C4 is expressed as the following formula.

C4=R+5LIC1 Furthermore, since Co=C4, Co=R+5−Ci −(6).As can be easily obtained by using equation (4), R− and S have the following relationship. 8=O...(7) Using the relationship S+5N=1, R=R・(S+SN) Furthermore, using equation (7), R=R fist SN...(8)
From equations (6) and (8), G o =R-8N+ S-Ci -(9
) This can be shown in an Euler diagram as shown in FIG. 4 (A). Using this diagram, it can be seen that equation (9) is equivalent to the following equation.

CoN-(R-5N+5-Ci)N...(1
1), but it can be seen from the Euler diagram in FIG. 4(B) that it is equivalent to the following equation.

Co N=(R-8N)N・(S-C1)N...(
12) In this example, (10), (12) derived above
Construct a logic circuit using the formula. First, logic gate L1
Generate R and S using 3°Li2. This R and S are C
Together with i and CiN, it becomes an input to logic gates L5 and L6. Logic gates L5 and L6 are exactly the same logic circuit, and the logic gates L5. The truth table for L6 is shown in FIG. 1(B).

Above L5. To configure L6 using actual transistors and FETs, see, for example, FIGS. 5 and 6.

The circuit shown in FIG. 7 can be used. Figure 5 shows n
This circuit uses the wired logic of the transfer gate using channel MOS transistors and a CMOS inverter. Figure 6 shows the wired logic of the CMOS clocked inverter, and Figure 7 shows the wired logic of the transfer gate and the bipolar 90M08 circuit. It uses an inverter. The correspondence between these circuit configurations and the logical functions shown in FIG. 1(A) can be easily confirmed by referring to the truth table shown in FIG. 1(B). Any of these circuits can be used as a simple inverter circuit.
A carry signal to the upper bits can be generated with a delay time approximately equal to the installation. Therefore, it is much faster than conventional circuits.

In the above embodiment, the logic circuit of the present invention is constructed using insulated gate field effect transistors, but junction field effect transistors (JFETs) and metal semiconductor junction field effect transistors (MESFETs) may also be used. Of course, similar effects can be obtained.

Furthermore, in the circuit of FIG. 5, n-channel MOS transistors M1, M2 . M5. The threshold voltage of M6 is applied to p-channel MOS transistor M3. By setting the voltage lower than the threshold voltage of M7, power consumption can be reduced. This is because the high level of nodes Nl and N2 is equal to the ttt source voltage V.
cc, n-channel MOS transistors Ml, M2 .
M5. It can only go up to a point as low as the threshold voltage of M6.

Therefore, if the threshold voltage of the p-channel MOS transistor is set higher than that of the n-channel, the CMOS inverter M3. Leakage current in M4 can be reduced.

Furthermore, it is easy to apply this embodiment to carry lookahead circuits other than 4 bits. Equation (5) can be easily extended to any bit length. That is, by repeatedly using equation (3), a linear equation is obtained.

Cj = Gj + Pj・[Gj−1+Pj−1・(G
j −2+ P j −2...(G 2 + P 2
・Gl))]+Pj−Pj−1・・P2・Pl・Ci
...(13) Here, once again.

R=Gj+Pj・[Gj −1+Pj−1・(aj−2
+pj-z...(G2+P2・G1)) If we set ko5=Pj・P, j-1...P2・Pl, (6
) formula can be applied as is.

FIG. 8 shows an example of a 32-bit adder constructed using the 4-bit carry look ahead circuit described above.

This adder inputs the augend Aj*BJ and receives the sum signal S
j (j is 1-32), Gj is a carry generation signal, Pj is a carry ledger signal, Cj is a carry signal, and V
cc is the power supply voltage.

This adder consists of a PG generation block, a 4-bit carry look-ahead circuit block, and a full adder block. In the PC generation block, P J e according to equations (1) and (2)
The one-carry look-ahead block that generates a signal Gj and outputs the signal to the one-carry look-ahead circuit generates a carry signal Cj and outputs it to the full adder. The full adder block performs addition and outputs a sum signal.

At the same time, a carry signal is output again, but this is unnecessary because it has already been output by the carry look ahead circuit, so it is left open without being connected.

The actual 32-bit addition operation will be explained next. When all the input signals Aj*Bj (j=1 to 32) are input at the same time, the PG generation block generates a signal PJ*GJ, and the 4-bit carry look ahead circuit U1...
- Input to U8. Upon receiving this input, the gate L13 of FIG. 1(A). LL4 operates and signals S and R are
...It will be confirmed almost simultaneously within U8. Next, at Ul, since Ci is grounded and CiN is fixed at high level, the gate L5. L6 operates and carry signals Co, Co
Output N to U2. The operating speed of this Ul is determined by the speed of the gate L14, which has a large fan-in number, and is comparable to the conventional carry look-ahead circuit. On the other hand, U2~
In U8, since the signals S and R have already been determined, L5. Only the time required for the operation of L6 is required, and the operation is extremely fast. L5. Since L6 operates with approximately the delay time required by installing an inverter, U2 to U8 operate approximately by installing an inverter, and the time for 32-bit addition is also greatly shortened compared to the conventional method.

As explained above, in the 4-bit carry look-ahead circuit, the first
If the present invention shown in the figure is used, it can operate at extremely high speed.
In the present invention, which can realize a 2-bit adder, the fan-in number and fan-out number are Only a small gate is required to operate, and it is fast.

〔Effect of the invention〕

In the present invention, in the final stage circuit of the carry look-ahead circuit, by utilizing the lower and δ carry signals and the inverted signal of the carry signal to the upper pitch i, gates with a small fan-in number and a small fan-out number are used.

It constitutes the final stage of the carry look ahead circuit. This makes it possible to speed up this final stage and speed up the carry look-ahead circuit. 4
In the bit carry look-ahead circuit, while the conventional circuit required a delay time approximately 10 times that of a simple inverter circuit, the present invention operates with a delay time corresponding to a simple inverter stage. In other words, the 0-carry look-ahead circuit, which is approximately -digit faster than the conventional one, uses an adder, an arithmetic logic unit (ALU)
).

It can be applied to parts of logic LSIs that require the highest speed, such as parallel multipliers, and can greatly speed up those parts.

[Brief explanation of the drawing]

FIG. 1(A) is a diagram showing a carry look-ahead circuit according to a first embodiment of the present invention, and FIG. 1(B) is a diagram showing a logic gate L5. Figure 2 shows the truth table of L6, Figure 2 shows a conventional carry look-ahead circuit, and Figure 3 shows a 32-bit carry look-ahead circuit using a conventional 4-bit carry look-ahead circuit. Figure 4 is an Euler diagram proving the basic logical formula of the carry look-ahead circuit of the present invention, and Figures 5, 6, and 7 are the carry look-ahead circuit of the present invention shown in Figure 4. FIG. 8 is a diagram showing an example in which a logic circuit used in the present invention is constructed using transistors. FIG. 8 is a diagram showing an example in which a 32-bit adder is constructed using the carry look-ahead circuit of the first embodiment of the present invention. L3. L8. Lll, L13...AND gate, L4
...OR gate, L5. L6. L14...logic gate, L7. L9. LIO, L12...NAND gate, L4 = OR gate, vcc...power line, C
L...Carry input signal from lower bit, CiN...
・Inverted input signal of carry signal from lower bit, Pl-
32...Carry ledger signal, G1-32...Carry generation signal, Go...Carry output signal to upper bit. CoN...Inverted output signal of carry signal to upper bit, C1-32... Carry signal, [1-8...4-bit carry look-ahead circuit, Ml, M2. M4-6. M8-10
．． Ml2-16. M18-M2O, M23-24. M2
7-28.31-32. M2S-36...n channel MOS transistor, M3°M7. Mll, Ml7. M
21. M22. M2S. M26. M29-30. M2S-34,...p channel MOS transistor, Q1-Q4...npn bipolar transistor. (Co) th (in C3+ Loshi?? shi81..7 C41=nisha ni 3 Lx shi1 (A) Hozu 1st pull

Claims (1)

[Claims] 1. In a carry look-ahead circuit, a terminal for inputting a carry signal from lower bits, a terminal for inputting an inverted signal thereof, a terminal for outputting a carry signal for upper bits, and a terminal for inputting a carry signal for upper bits, and A logic circuit characterized by having a terminal that outputs an inverted signal. 2. In the n-bit carry look ahead circuit, let the j-th digit augend be Aj, Bj, and Pj = Aj ■ Bj, Gj = Aj
・When logical values Pj and Gj are defined by Bj, Gn+Pn
・[Gn-1+Pn-1・{Gn-2+Pn-3...
(G2+P2・G1)...}] or similar logic such as an inverted signal of this logic and Pn・Pn-1...
A logic circuit characterized in that it generates a logic called Pn or a logic similar thereto, and uses this to generate a carry signal of the highest order.