JPH02217895A - Display device - Google Patents

Abstract

PURPOSE:To speed up display data transfer by counting transfer clocks by counters by every driving circuit units and inputting display data of corresponding picture element groups according to the counted values. CONSTITUTION:Data-side electrodes x1-xn of a display panel 11 are connected to a data-side driving circuit 12, scan-side electrodes y1-ym are connected to a scan-side driving circuit 3, and each of the driving circuit units 12 and 13 is provided with a counter 15 which counts a transfer clock CK synchronized with the transfer of display data to detect the transfer timing of the display data of the picture element groups corresponding to the driving circuit units 12 and 13 according to the counted values of the counters 15. Then, the display data of the respective picture element groups are inputted to the corresponding driving circuits 12 and 13. Consequently, the inputting operation of the display data by the driving circuits 12 and 13 is not delayed and the display data can be transferred at a high speed.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a display device such as a liquid crystal display device.

BACKGROUND OF THE INVENTION FIG. 3 is a block diagram showing a schematic configuration of a simple matrix drive type liquid crystal display device. In the figure, the display panel 1 has a plurality of data side electrodes X1 to Xn (hereinafter referred to as
An arbitrary data-side electrode is represented by the symbol X) and a plurality of scans ([111 poles Y1 to Ym (hereinafter, an arbitrary scanning-side electrode is represented by the symbol Y) are intersected via a liquid crystal layer. The data side electrode
The intersection between the Y and the scanning side electrode Y forms a pixel (represented as a capacitor in the figure), and these pixels are arranged in a matrix.

The data side electrodes x1 to Xn of the display panel 1 are connected to the data side drive circuit 2, while the scan side electrodes Y1 to Ym are connected to the scan side drive circuit 3, and are connected to the data side drive circuit 2 and the scan side drive circuit 3. A display control circuit 4 is connected to control these circuits.

The data side drive circuit 2 includes a scanning line, that is, a scanning side electrode Y
A function of inputting the display data of pixels for each one scanning line serially transferred from the display control circuit 4 according to the line sequence, and applying the modulation voltage ■9 corresponding to the display data to the corresponding data side electrode X. On the other hand, the scan-side drive circuit 3 selects scan-side electrodes Y corresponding to one scan line of display data to be transferred line-sequentially, and applies a write voltage ■1 to the selected scan-side electrodes Y. An effective voltage corresponding to the difference between the modulation voltage (A) and the write voltage (■) is applied to each pixel that has a function, and depending on whether or not the effective voltage exceeds the light emission threshold voltage of the liquid crystal, the display Depending on the data, the pixels are turned on (light-emitting state) or off (non-light-emitting state), thereby displaying an image.

The data side drive circuit 2 and the scanning side drive circuit 3 are constituted by drug type circuits. For example, as shown in FIG. It is constituted by a plurality of drive circuit chips 61 to Gq (hereinafter, any drive circuit chip is represented by the symbol G) individually associated with each pixel group divided into a plurality of groups.

In the conventional data-side drive circuit 2, among the display data for each one scanning line that is serially transferred from the display control circuit 4 according to the arrangement order of pixels on the scanning-side electrode Y, the first M
The drive circuit chip G1 corresponding to the pixel group located at the lowest pixel group (for example, the pixel group located at the left end among the pixel groups arranged in the longitudinal direction of the scanning line) receives the chip enable output CE1 from the display control circuit 4 and Corresponding display data is captured, and upon completion of capture, a chip enable output CE2 is output from this drive circuit chip G1.

The next drive circuit chip G2 that receives the output CE2 in the chip enable takes in the corresponding display data.The same operation is performed up to the last stage drive circuit chip G9, thereby displaying data for one scanning line. It is configured so that the capture is completed.

Problem to be Solved by the Invention However, in the configuration of the conventional data-side drive circuit 2 described above, the next-stage drive circuit chip G enters the operating state after receiving the chip enable output CE from the previous-stage drive circuit chip G. It takes some time for this to occur, and this time causes a delay in the display data capture operation, making it difficult to accurately set the timing of the display data and the transfer clock used to transfer the display data. In particular, when increasing the screen size of a display device, a large amount of display data is required, and the display data transfer speed must be increased accordingly. This will hinder the

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a display device that enables high-speed transfer of display data without causing any delay in the display data capture operation in the drive circuit.

Means for Solving the Problems The present invention divides a plurality of pixels arranged in a matrix into a plurality of pixel groups, with pixels of a plurality of adjacent columns as one group, and individually The drive circuit units are associated with each other, and the display data of each pixel group is taken in by the drive circuit unit corresponding to the pixel group among the display data of each row of pixels that is serially transferred according to the arrangement order of the pixels in the row direction. In a display device that drives a corresponding pixel with an output according to captured display data, each drive circuit unit is provided with a counter that counts a transfer clock that is synchronized with the transfer of display data, and the count of this counter is A display device characterized in that the display data of each pixel group is taken into the corresponding drive circuit unit by detecting the transfer timing of the display data of the pixel group corresponding to the drive circuit unit based on the value. It is.

Effect According to the present invention, the transfer clock is counted by the force counter for each drive circuit unit, and each drive circuit unit starts capturing display data at the corresponding timing based on the count value, so that the capture operation is performed quickly. There are no associated delays.

Embodiment FIG. 1 is a block diagram showing a schematic configuration of a simple matrix drive type liquid crystal display device which is an embodiment of the present invention. Its schematic structure is the same as that of the conventional liquid crystal display device described above, and the display panel 11 includes a plurality of data-side electrodes x1 to xn (hereinafter, any data-side electrode is represented by the symbol X) and a plurality of It is constructed by three-dimensionally intersecting the scanning side electrodes y1 to ym (hereinafter, any scanning side electrode is represented by the symbol y) via a liquid crystal layer, and the data steel weight Sx and the scanning side electrode y are The intersections form pixels, and these pixels are arranged in a matrix.

Further, the data side electrodes x1 to Xn of the display panel 11 are connected to the data side drive circuit 12, and the five scan side electrodes y1 to ym are connected to the scan side drive circuit 3, and the data side drive circuit 12 and the scan fll1wA drive circuit 13. Similarly to the conventional liquid crystal display device, the display control circuit N14 for controlling these circuits is connected to the display control circuit N14.

FIG. 2 is a block diagram showing a more specific configuration of the data side drive circuit 12.

In other words, the data side drive circuit 12 includes a plurality of drive circuit chias individually associated with each pixel group that is divided into a plurality of groups, with pixels on a plurality of adjacent data side electrodes X being one group. 7gl-gq (hereinafter, any drive circuit chip will be represented by the symbol g).

Each drive circuit chip g synchronizes with the display data transferred from the display control circuit 14 to the data side drive circuit 12.
It also has an N-ary counter 15 that counts the transfer clock CK input from the display control circuit 14 to the data side drive circuit 12, a chip select decode circuit 16, and an internal circuit 17 including a shift register, a latch circuit, and the like.

The chip select decode circuit 16 compares the count value of the N-ary counter 15 with a value specified by, for example, a multi-bit chip enable selection signal d given from the display control circuit 14, and when they match, A select signal p is output to put the internal circuit 17 into an operating state.

Chip select decode circuit 16 of each drive circuit chip g
The chip enable selection signal d inputted to the chip enable selection signal d differs for each drive circuit chia 1g. That is, in this embodiment, for example, for the drive circuit chip gk corresponding to the pixel group of the second rank (the pixel group positioned from the left among the pixel groups arranged in the longitudinal direction of the scanning line), the first A chip enable selection signal dk that specifies the number of pixels on one scanning line from the pixel group of the rank to the pixel group of the (kl)th rank is input, and the chip select decoding circuit 16 receives this selection signal d.
It has a function of converting k into data of the above number of pixels.

Similarly, regarding the chip enable selection signal d input to other drive circuit chips g, the number of pixels up to the pixel immediately before the first pixel in the pixel group corresponding to the drive circuit chip g is converted. The internal circuit 17 of each drive circuit chip g has a function of taking in display data transferred from the display control circuit 14 and applying a modulation voltage VH corresponding to the display data to the corresponding data side electrode X.

Further, as in the case of a conventional liquid crystal display device, the scanning side drive circuit 13 is a scanning side type [! It has a function of selecting y line sequentially and applying a write voltage VII to the selected scanning side type aiy.

Next, in synchronization with display data for each one scanning line that is serially transferred from the 0 display control circuit 14 according to the arrangement order of pixels on the scanning side electrode y to explain the operation of the liquid crystal display device, a transfer clock CK is transmitted. Also data side drive circuit 12
is input to each drive circuit chip g, and each drive circuit chip g
Each N-ary counter 15 counts the transfer clock CK.

The chip enable selection signal d1 specifying the number of pixels [0] is given to the chip select decode circuit 16 of the first stage drive circuit chip g1, and therefore, even before the N-ary counter 15 counts the transfer clock CK. A select signal p is applied from the chip select decode circuit 16 to the internal circuit 17, and the internal circuit 17 is put into an operating state before the start of display data transfer. Therefore, at the same time as the transfer of display data starts, the display data is captured by the internal circuit 17, and the N-ary counter 15 receives the transfer clock C as many times as the number of pixels corresponding to this drive circuit chip g1.
When K is counted, that is, when the display data of the pixel corresponding to this drive circuit chip g1 is captured, the output of the select signal p is stopped, and the capture of display data by the internal circuit 17 is completed.

Since the chip select decode circuit 16 of the second-stage drive circuit chip g2 is supplied with the chip enable selection signal d2 that specifies the number of pixels on one scanning line of the first pixel group, the N-ary counter 15 counts the transfer clock CK by the number of pixels, the chip select decode circuit 16 sends a select signal p to the internal circuit 17.
is given, and the internal circuit 17 starts taking in display data.

That is, the collection of display data by the second-stage drive circuit chip g2 starts from the next display data after the display data acquisition of the first-stage drive circuit chip g1 is completed, and When display data corresponding to the number of pixels on one scanning line of the pixel group corresponding to chip g2 is captured, the capture operation is stopped. Therefore, the display data of the corresponding pixel is also captured in the second stage drive circuit chip g2. Thereafter, the display data of the corresponding pixel groups are respectively captured in the drive circuit chips g of each stage in the same manner.

A modulation voltage corresponding to the display data for one scanning line is applied from the data side drive circuit 12 to each data side electrode x1 to xn.
At the same time that 1 is applied, the scanning side drive circuit 13
An operation is performed in which the scanning side electrode y of the book is selected and the write voltage Vw is applied to the scanning side electrode y. As a result, the five selected pixels on the scanning side electrode y are turned on or off according to each display data. Such operations are repeated for each scanning line, thereby displaying the image.

In addition, although the above embodiment describes the case of a liquid crystal display device, the present invention is not limited to this, and the same applies to other display devices such as EL display devices as long as the display device uses a display panel in which pixels are arranged in a matrix. Applicable.

Effects of the Invention As described above, according to the display device of the present invention, the transfer clock is counted by the counter for each drive circuit unit, and the display data of the corresponding pixel group is taken in based on the counter value. Therefore, there is no delay associated with the display data capture operation, and the display data can be transferred at high speed, making it possible to increase the size of the screen and improve the quality of the color screen.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal display device which is an example of the present invention, FIG. 2 is a block diagram showing a schematic configuration of a data side drive circuit, and FIG. 3 is a conventional block diagram. FIG. 4 is a block diagram showing the schematic structure of the liquid crystal display device, and FIG. 4 is a block diagram showing the schematic structure of the data side drive circuit. 11... Display panel, 12... Data side drive circuit,
13... Scanning side drive circuit, 14... Display control circuit,
15... N-ary counter, 16... Chip select decoding circuit, 17... Internal circuit, x1-xn... Data side electrode, 11-7m... Scanning side electrode, g1-gq
...Driver circuit chip agent Patent attorney Keiichi Saikyo

Claims (1)

[Claims] A plurality of pixels arranged in a matrix is divided into a plurality of pixel groups, with pixels in adjacent columns as one group, and drive circuit units are individually associated with these pixel groups. Of the display data of each row of pixels that is serially transferred according to the arrangement order, the display data of each pixel group is captured by the drive circuit unit corresponding to that pixel group, and the output corresponds to the captured display data. In a display device configured to drive pixels, each drive circuit unit is provided with a counter that counts a transfer clock synchronized with the transfer of display data, and a counter is provided for each drive circuit unit to correspond to the drive circuit unit based on the count value of this counter. A display device characterized in that the display data of each pixel group is taken into a corresponding drive circuit unit by detecting the transfer timing of the display data of the pixel group.