JPH0221773Y2 - - Google Patents
Info
- Publication number
- JPH0221773Y2 JPH0221773Y2 JP1983001273U JP127383U JPH0221773Y2 JP H0221773 Y2 JPH0221773 Y2 JP H0221773Y2 JP 1983001273 U JP1983001273 U JP 1983001273U JP 127383 U JP127383 U JP 127383U JP H0221773 Y2 JPH0221773 Y2 JP H0221773Y2
- Authority
- JP
- Japan
- Prior art keywords
- controlled oscillator
- voltage controlled
- fet
- amplifier
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000010355 oscillation Effects 0.000 claims description 6
- 230000000694 effects Effects 0.000 description 9
- 238000002955 isolation Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000002452 interceptive effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Description
【考案の詳細な説明】
（技術分野）
本考案は移動無線装置等に使用する電圧制御発
振器の改良に関するものである。[Detailed Description of the Invention] (Technical Field) The present invention relates to an improvement of a voltage controlled oscillator used in mobile radio equipment and the like.
（従来技術）
移動無線装置は、一般に送信機および受信機を
含む構成となつており、待受受信時は送信電力を
停止させる如く構成するのが一般的である。送信
電力を停止させる手段は送信機の構成の仕方で種
種の手段がとられる。近来送信機の簡素化のた
め、送信周波数を直接電圧制御発振器で発生して
送信波を作る方法が考案されている。この場合、
電圧制御発振器は広い周波数範囲（20〜30MHz
幅）をカバーするため、移動無線装置の例では制
御電圧の1V変化で発振周波数が10MHz位変化す
る感度を有するのが一般的である。また、発振周
波数は一般にバラクタ（可変容量ダイオード）で
可変するため１〜2pF変化で10MHz位変化する感
度を有する。このように高感度であるため、わず
かな妨害電圧印加や負荷変化で発振周波数が変化
してしまう。例えば10μVの妨害電圧印加で100Hz
の周波数変化となる。また、容量変化としては１
〜2pFの10-5の変化で100Hzの周波数変化となる。
ところが周波数変化としては、システムに許容さ
れている残留FM（例えば100Hz）以下におさえる
必要がある。このようにきびしい要件を満足させ
るためには、電圧制御発振部を妨害電圧印加や負
荷からほぼ完全に保護する必要がある。このため
送信電力のON／OFFによる発振周波数変化を許
容値以下におさえるためには、シールド効果を高
めるため低レベルの電圧制御発振器の外部に多段
の緩衝増幅器を設け、この緩衝増幅器の動作の一
部を停止することにより出力レベルを制御する構
成が必要であつた。この構成では電圧制御発振器
と電力増幅器の間に緩衝増幅器を必要とし、この
緩衝増幅器の入出力は同軸ケーブルで接続しなけ
ればならず、実装面積が増え、かつ高コストにな
り、また振動にも弱いと云う欠点があつた。(Prior Art) A mobile radio device is generally configured to include a transmitter and a receiver, and is generally configured to stop transmitting power during standby and reception. Various means can be used to stop the transmission power depending on the configuration of the transmitter. Recently, in order to simplify transmitters, a method has been devised in which a transmission frequency is directly generated by a voltage-controlled oscillator to create a transmission wave. in this case,
The voltage controlled oscillator has a wide frequency range (20~30MHz
In order to cover the wide range of frequency ranges, mobile radio devices typically have a sensitivity where a 1V change in control voltage changes the oscillation frequency by about 10MHz. Further, since the oscillation frequency is generally varied by a varactor (variable capacitance diode), the sensitivity changes by about 10 MHz with a change of 1 to 2 pF. Because of this high sensitivity, the oscillation frequency changes with the slightest disturbance voltage application or load change. For example, 100Hz with 10μV disturbance voltage applied
The frequency changes. Also, the capacitance change is 1
A 10 -5 change of ~2pF results in a 100Hz frequency change.
However, the frequency change must be kept below the residual FM allowed by the system (for example, 100Hz). In order to meet such stringent requirements, it is necessary to almost completely protect the voltage controlled oscillator from the application of interfering voltages and loads. Therefore, in order to suppress the oscillation frequency change due to ON/OFF of the transmission power to below the allowable value, a multi-stage buffer amplifier is installed outside the low-level voltage controlled oscillator to increase the shielding effect, and the operation of this buffer amplifier is adjusted. A configuration was required to control the output level by stopping the section. This configuration requires a buffer amplifier between the voltage controlled oscillator and the power amplifier, and the input and output of this buffer amplifier must be connected with a coaxial cable, which increases the mounting area and costs, and also reduces vibration. It had the drawback of being weak.
（考案の目的と構成）
本考案の目的は、これらの欠点を解決するため
少ない段数の緩衝増幅器で構成し、同一基板にそ
の回路を搭載し同一ケースに収容することによ
り、小形化および低コスト化を計り妨害信号に強
く、また振動にも強い電圧制御発振器を実現する
もので、以下本考案の実施例を図にしたがつて詳
細に説明する。(Purpose and structure of the invention) The purpose of the invention is to solve these drawbacks by configuring a buffer amplifier with a small number of stages, and by mounting the circuit on the same board and housing it in the same case, it is possible to reduce the size and cost. The invention is intended to realize a voltage controlled oscillator that is strong against interference signals and vibrations, and embodiments of the present invention will be described in detail below with reference to the drawings.
（実施例）
第１図は本考案の実施例を説明するための回路
構成図であり、１は電圧制御発振部、２は複数段
のFET（電界効果トランジスタ）緩衝増幅器、３
は電源をON／OFFすることにより出力レベルを
ON／OFFする出力制御用FET増幅器、４は電圧
制御発振部１の出力を電力増幅する電力増幅器、
５は電圧制御発振部１の周波数制御端子、６は出
力制御用FET増幅器の電源端子、７は電圧制御
発振器の出力端子である。(Embodiment) FIG. 1 is a circuit configuration diagram for explaining an embodiment of the present invention, in which 1 is a voltage controlled oscillator, 2 is a multi-stage FET (field effect transistor) buffer amplifier, and 3 is a circuit configuration diagram for explaining an embodiment of the present invention.
The output level can be changed by turning the power ON/OFF.
4 is a power amplifier for power amplifying the output of the voltage controlled oscillator 1;
5 is a frequency control terminal of the voltage controlled oscillator 1, 6 is a power supply terminal of an output control FET amplifier, and 7 is an output terminal of the voltage controlled oscillator.
電圧制御発振部１はバラクタ等を使用して、電
圧により発振周波数を可変させるもので、前述の
如く10MHz／Ｖおよび10MHz／１〜2pF程度の感
度を有する。FET緩衝増幅器２は１段当り40dB
程度の逆方向アイソレーシヨンを有する。出力制
御FET増幅器３は電源をOFFすることにより増
幅作用を無くし、かつFET固有の入出力間の高
絶縁特性により出力レベルを断とすることができ
るものである。 The voltage controlled oscillator 1 uses a varactor or the like to vary the oscillation frequency with a voltage, and has a sensitivity of about 10 MHz/V and 10 MHz/1 to 2 pF as described above. FET buffer amplifier 2 is 40dB per stage
It has a degree of reverse isolation. The output control FET amplifier 3 can eliminate the amplification effect by turning off the power, and can cut off the output level due to the high insulation characteristic between the input and output inherent to the FET.
第２図は本考案の実施例を説明するための実装
図であり、８は前記の電圧制御発振器の各回路を
搭載する一体化されたアルミナ等の高誘電体基
板、９はその基板８を収納しシールドするための
シールドケースである。また、１１は電圧制御発
振部１を搭載する場所、１２はFET緩衝増幅器
２を搭載する場所、１３は出力制御FET増幅器
３を搭載する場所を示し、１７は電圧制御発振器
出力端子７のための同軸コネクタである。出力制
御FET増幅器３の入出力間（ドレイン→ゲート
間）の結合容量は0.05pF程度であり一般のバイポ
ーラトランジスタに比し1/10程度であるため、電
源電圧６のON／OFFによる入力側（ゲート側）
への負荷変化の影響はバイポーラトランジスタを
使用した場合に比し1/10にできる。また、FET
緩衝増幅器２は１段当り約40dBの逆方向アイソ
レーシヨンがありバイポーラトランジスタの約
20dBに比し高アイソレーシヨンであるため、
FET緩衝増幅器２としては２〜３段でバイポー
ラトランジスタの４〜６段と同等の逆方向アイソ
レーシヨンを得ることができる。また、出力
ON／OFFによる周波数変化を規定値をおさえる
ためには、0.05pFの容量変化を前述の100Hz／
（１〜2pF）×10-5の変化に抑えれば良く、
0.05pF／1.5×10-5pF≒3000倍≒70dBの逆方向ア
イソレーシヨンを有すればよくFET緩衝増幅器
２としては２〜３段の構成で充分であり、大幅な
段数の削減が可能となる。このFET緩衝増幅器
２と出力制御用FET増幅器３を電圧制御発振部
１と同じアルミナ基板上に搭載し、同一シールド
ケースに実装することにより出力端子１７からの
影響が少ないことより振動による負荷変化が原因
のＳ／Ｎ劣化を防止することができ、同時に高ア
イソレーシヨン性により妨害電圧にも強くなると
いう大きな効果がある。 FIG. 2 is a mounting diagram for explaining an embodiment of the present invention, where 8 is an integrated high dielectric substrate made of alumina or the like on which each circuit of the voltage controlled oscillator is mounted, and 9 is the substrate 8. A shield case for storing and shielding. Further, 11 indicates a location where the voltage controlled oscillator 1 is mounted, 12 indicates a location where the FET buffer amplifier 2 is mounted, 13 indicates a location where the output controlled FET amplifier 3 is mounted, and 17 indicates a location where the voltage controlled oscillator output terminal 7 is mounted. It is a coaxial connector. The coupling capacitance between the input and output (drain → gate) of the output control FET amplifier 3 is about 0.05 pF, which is about 1/10 of that of a general bipolar transistor, so the input side ( gate side)
The effect of load changes on the transistor can be reduced to 1/10 compared to when bipolar transistors are used. Also, FET
Buffer amplifier 2 has a reverse isolation of about 40 dB per stage, which is about the same as that of a bipolar transistor.
Because it has high isolation compared to 20dB,
As the FET buffer amplifier 2, 2 to 3 stages can provide reverse isolation equivalent to 4 to 6 stages of bipolar transistors. Also, the output
In order to suppress the frequency change due to ON/OFF to the specified value, the capacitance change of 0.05pF should be reduced to 100Hz/
It is sufficient to suppress the change to (1 to 2 pF) × 10 -5 ,
It is sufficient to have a reverse isolation of 0.05pF/1.5×10 -5 pF ≒ 3000 times ≒ 70 dB, and a configuration of 2 to 3 stages is sufficient for the FET buffer amplifier 2, making it possible to significantly reduce the number of stages. Become. By mounting this FET buffer amplifier 2 and the output control FET amplifier 3 on the same alumina substrate as the voltage controlled oscillator 1 and mounting them in the same shield case, the influence from the output terminal 17 is reduced, and load changes due to vibration are reduced. This has the great effect of being able to prevent the S/N deterioration caused by this, and at the same time being resistant to interfering voltages due to its high isolation properties.
なお、第１図における説明では、送信機に用い
る電圧制御発振器の構成を述べたが、受信機の局
部発振器として電圧制御発振器を使用する場合に
おいても第１図の出力制御用FET増幅器３のか
わりに受信ミキサーを接続し同一基板、同一ケー
スに収容すればFET緩衝増幅器２の高アイソレ
ーシヨン性により、負荷変化が原因のＳ／Ｎ劣化
は防止され、また妨害電圧に強くなるという効果
には変化が無いことは明らかである。また、第２
図には電圧制御発振部１およびFET緩衝増幅器
２、出力制御FET増幅器３を直線的に配置した
例を示したが、これらを異形な配置にしても殆ん
ど同等の効果が得られる。 In the explanation of FIG. 1, the configuration of the voltage controlled oscillator used in the transmitter was described, but even when using the voltage controlled oscillator as the local oscillator of the receiver, the output control FET amplifier 3 in FIG. 1 can be replaced. If the receiving mixer is connected to the receiver mixer and housed on the same board and in the same case, the high isolation property of the FET buffer amplifier 2 will prevent S/N deterioration caused by load changes, and will also have the effect of becoming resistant to interference voltage. It is clear that there is no change. Also, the second
Although the figure shows an example in which the voltage controlled oscillator 1, the FET buffer amplifier 2, and the output controlled FET amplifier 3 are arranged linearly, almost the same effect can be obtained even if these are arranged in an irregular shape.
（考案の効果）
以上説明したように、本考案によれば少ない緩
衝増幅器で妨害電圧印加や負荷変化に強い特性が
得られ、同一基板、同一ケース収納により小形化
および経済化が容易となる。また、電圧制御発振
器の装置実装時の制約条件が緩和され経済化が可
能になるという波及効果もあり、本発明を移動無
線装置等に利用することによりその効果は極めて
大きい。(Effects of the invention) As explained above, according to the invention, characteristics that are resistant to interference voltage application and load changes can be obtained with a small number of buffer amplifiers, and miniaturization and economicalization are facilitated by storing the same board and the same case. Furthermore, there is a ripple effect in that the constraints on device mounting of the voltage controlled oscillator are relaxed and economicalization becomes possible, and this effect is extremely large when the present invention is applied to mobile radio devices and the like.
第１図は本考案の実施例を説明するための回路
構成図、第２図は本考案の実施例を説明するため
の実装図。
１……電圧制御発振部、２……FET緩衝増幅
器、３……出力制御用FET増幅器、４……電力
増幅器、５……周波数制御端子、６……電源端
子、７……出力端子、８……高誘電体基板、９…
…シールドケース。
FIG. 1 is a circuit configuration diagram for explaining an embodiment of the present invention, and FIG. 2 is a mounting diagram for explaining an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Voltage control oscillator, 2... FET buffer amplifier, 3... FET amplifier for output control, 4... Power amplifier, 5... Frequency control terminal, 6... Power supply terminal, 7... Output terminal, 8 ...High dielectric substrate, 9...
...shield case.
Claims (1)
部と、 その出力回路を有する電圧制御発振器におい
て、出力回路の終段部分に、FET増幅器の電源
をON／OFFすることにより出力レベルをON／
OFFする出力制御用FET増幅器を設け、この
FET増幅器と電圧制御発振部との間に複数段の
FET緩衝増幅器を設け、かつこれらを一体の基
板に搭載し、一体のシールドケースに収容してな
る電圧制御発振器。[Claims for Utility Model Registration] In a voltage controlled oscillator that has a voltage controlled oscillator that controls the oscillation frequency by voltage and an output circuit thereof, the power of the FET amplifier is turned on and off at the final stage of the output circuit. Turn the output level on/
A FET amplifier for output control that turns off is installed, and this
Multiple stages are installed between the FET amplifier and the voltage controlled oscillator.
A voltage controlled oscillator equipped with a FET buffer amplifier, mounted on a single board, and housed in a single shielded case.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP127383U JPS59108319U (en) | 1983-01-11 | 1983-01-11 | voltage controlled oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP127383U JPS59108319U (en) | 1983-01-11 | 1983-01-11 | voltage controlled oscillator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59108319U JPS59108319U (en) | 1984-07-21 |
| JPH0221773Y2 true JPH0221773Y2 (en) | 1990-06-12 |
Family
ID=30133003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP127383U Granted JPS59108319U (en) | 1983-01-11 | 1983-01-11 | voltage controlled oscillator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59108319U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS532967U (en) * | 1976-06-28 | 1978-01-12 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57104613U (en) * | 1980-12-19 | 1982-06-28 |
-
1983
- 1983-01-11 JP JP127383U patent/JPS59108319U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS532967U (en) * | 1976-06-28 | 1978-01-12 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59108319U (en) | 1984-07-21 |
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