JPH02214931A - Floating point arithmetic circuit - Google Patents

Abstract

PURPOSE:To shorten the computing time by sorting the interim results of arithmetic operations of a mantissa part and carrying out both normalizing and rounding processes in parallel with each other. CONSTITUTION:A mantissa part arithmetic circuit 2 performs an arithmetic operation with two mantissa parts after a digit matching process and outputs this computing result to a normalizing shift value detecting circuit 3, a shift circuit 4 and a rounding process circuit 5. The circuit 3 detects the shift value to normalize the output of the circuit 2 and decides a valid or invalid state of the rounding process. A selection circuit 11 selects the output of the circuit 4 with an invalid rounding process decided by the circuit 3 and then selects the output of the circuit 5 with a valid rounding process respectively to output these outputs as the computing results of the mantissa part. Thus it is possible to omit the rounding process with the output of the circuit 4 decided as the computing result of the mantissa part in the case the rounding process is invalid. As a result, the computing time is shortened by the necessary time and a floating point arithmetic is carried out at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to normalization processing and rounding processing in a floating point arithmetic circuit.

(Prior Art) Fig. 4 is a block diagram showing an example of a conventional floating-point arithmetic circuit (for example, ``1986 Institute of Electronics and Communication Engineers Comprehensive National Conference Proceedings nJ (1986 1-3-5) Electronic Communication Conference P2-157).

This floating point arithmetic circuit includes a preprocessing unit 101 that performs digit alignment processing by comparing the exponent parts of the first and second operands, and a mantissa arithmetic circuit 102 that performs an operation between the mantissa parts after digit alignment. , a normalization shift amount detection circuit 103 that detects a shift amount for normalizing the output of the mantissa calculation circuit 102, and a normalization shift amount detection circuit 103 that detects the shift amount for normalizing the output of the mantissa calculation circuit 102; A shift circuit 104 performs rounding processing on the output of the shift circuit 104, a rounding processing circuit 105 performs rounding processing on the output of the shift circuit 104, and the output value of the normalized shift amount detection circuit 103 or the output value of the rounding processing circuit 105 is used as the correction value of the exponent part. a selection circuit 110 that selects a preprocessor 10 based on the output of the selection circuit 110
Exponent part calculation circuit 10 that corrects the exponent part which is the output of
6, the output of the exponent calculation circuit 106 and the rounding processing circuit 10
5 and a post-processing unit 107 that synthesizes the final result from the outputs of 5.

Next, the operation of this floating point arithmetic circuit will be explained.

The floating point data format used in this explanation is (-1)s・2°-12 floating point numbers as shown in (a) in Figure 2.
7.(1+f) and O≦f<1, the data is 32 bits consisting of a sign part S of 1 pint, an exponent part e1 of 8 bits, and a mantissa part f of 23-bit absolute value representation. These two operands in 32-bit format are processed in the following order.

(2) The preprocessing unit 101 compares the exponent parts of both operands, and shifts the mantissa part with the smaller value of the exponent part to the right by the difference in the exponent parts. As shown in Figure 2 (b), the mantissa parts of both operands are 23-bit mantissa f, with a hidden pinot (1') added to the most significant digit, and a 1-bit extension bit added to the least significant digit. It is output in a 25-bit intermediate format. The least significant bit, the extension bit, stores the bit that caused the digit error during the right shift. At the same time, the value of the exponent part at this time is also output.

■ Mantissa calculation circuit) 02 calculates the mantissa parts of this intermediate format and obtains a 26-bit mantissa calculation result with an overflow bit added to the most significant digit of the intermediate format as shown in e→ in Figure 2. .

■ The normalization shift amount detection circuit 103 detects the number of consecutive '0''' from the upper digit of the mantissa calculation result,
Calculate the exponent correction amount and normalization shift amount.

(2) According to the output of the normalized shift amount detection circuit 103, the shift circuit 104 performs a shift process on the output of the mantissa calculation circuit 102.

(2) The rounding processing circuit 105 performs rounding processing on the output of the shift circuit 104. In the rounding process, if an overflow occurs as a result of addition of -1, the value obtained by shifting the addition result to the right by 1 bit becomes the output of the rounding processing circuit 105, and further outputs °+1'' as the exponent part correction amount. If no flow occurs, the +1 addition result is sent to the rounding processing circuit 10.
5, and the output of the normalization shift amount detection circuit 103 becomes effective as the exponent part correction amount.

(2) Based on the correction amount of the exponent part and j-, the selection circuit 110 selects either the output of the normalization shift amount detection circuit 103 or the output of the rounding processing circuit 1θ5.

(2) The exponent part calculation circuit 106 corrects the exponent part of the output of the preprocessing section 101 according to the output of the selection circuit 110.

(2) The post-processing unit 107 combines the output of the exponent calculation circuit 1θ6 and the output of the rounding processing circuit 105 to obtain a final result.

(Problem to be Solved by the Invention) However, the calculation time T in the floating point arithmetic circuit with the above configuration is as follows: time required for normalization processing is Tn, time required for rounding processing is Tr, and other processing time is Tm. In this case, T=Tm+Tn-h Tr, which causes a problem in that the normalization processing time and rounding processing time, as well as the floating point calculation time, are extended.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed floating-point arithmetic circuit by eliminating the problem that the floating-point arithmetic time is increased by sequentially executing the normalization processing time and the rounding processing time described above.

(Means for Solving the Problems) In order to achieve the above object, the present invention includes a mantissa calculation circuit that performs calculations between mantissa parts after digit alignment, and normalizes the output from the output of the mantissa calculation circuit. a normalization shift amount detection circuit for detecting a shift amount for the calculation, a shift circuit for normalizing the output of the mantissa calculation circuit by shifting it according to the shift amount, and a rounding circuit for rounding the output of the mantissa calculation circuit. a processing circuit, and when the shift amount is a value that disables rounding processing, selects the output of the shift circuit, and when the shift amount is not a value that disables rounding processing, selects the output of the rounding processing circuit and converts it into a mantissa operation result. It is equipped with a selection circuit for

(Operation) The mantissa calculation circuit performs calculations on the mantissa parts after digit alignment, and outputs the result to the normalized shift amount detection circuit, the shift circuit, and the rounding processing circuit.

The normalization shift amount detection circuit detects the shift amount for normalizing the output, and determines whether rounding processing is valid or invalid.

The determination can be made by noting that the rounding process becomes invalid when shifting one or more bits to the left. The shift circuit shifts the output of the mantissa calculation circuit according to the shift amount, normalizes it, and outputs the mantissa. On the other hand, the rounding processing circuit also performs rounding processing on the output of the mantissa calculation circuit in parallel and outputs the mantissa. The selection circuit selects the output of the shift circuit when the rounding process is invalid according to the determination result of the normalized shift amount detection circuit, and selects the output of the rounding process circuit when the rounding process is valid, and outputs the result as the mantissa calculation result.

In other words, when rounding is disabled, the output of the shift circuit is used as the mantissa operation result, omitting rounding, and reducing the necessary processing time to speed up floating-point operations. .

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention. That is, this embodiment includes a preprocessing unit 1 that performs digit alignment processing by comparing the magnitudes of the exponent parts of the first operand and the second operand;
Mantissa calculation circuit 2 that performs calculations between mantissa parts after digit alignment
and a normalization shift amount detection circuit 3 that detects the shift amount for normalizing the output of the mantissa calculation circuit 2 and outputs an exponent correction amount, and according to the shift amount detected by the normalization shift amount detection circuit 3. A shift circuit 4 that normalizes the output of the mantissa calculation circuit 2 and outputs the mantissa; and a rounding circuit 5 that performs rounding of the output of the mantissa calculation circuit 2 and outputs the mantissa and exponent correction amount. and normalized shift amount detection circuit 3
a selection circuit 10 that selects the exponent correction amount from the rounding processing circuit 5 or the exponent correction amount from the rounding processing circuit 5; and an exponent calculation circuit 6 that corrects the exponent part of the output of the preprocessing section 1 according to the output of the selection circuit 10. A selection circuit 11 selects the mantissa output from the shift circuit 4 or the mantissa output from the rounding circuit 5, and the output of the selection circuit 10 and the output of the selection circuit 1 are combined to produce a final result. The post-processing section 7 obtains the following information.

In this way, in this embodiment, the shift circuit 4 and the rounding circuit 5
It is characterized in that it is configured in parallel, and in this point it is greatly different from the configuration of the conventional floating point arithmetic circuit shown in FIG.

Next, the operation of this embodiment will be explained. The floating point data format used in this embodiment is the same as the format used in the explanation of the operation of the conventional floating point arithmetic circuit shown in FIG. The operation in is the same as the operation from the preprocessing section 101 to the mantissa calculation circuit 102 in FIG. 4, which has already been explained. The operation will be explained.

First, the case where the mantissa part of the final result is obtained from the mantissa calculation circuit 2 will be described. When a left shift operation is performed in the normalization process, the lower digits are supplemented with ``0'' in sequence. Therefore, in the data format of this embodiment as shown in (b) of FIG. Since the number of extension bits is 1 bit, if a left shift of 1 bit or more occurs, the value of the extension bit becomes If OIT, and rounding becomes invalid.On the other hand, if the shift amount is O bits or a 1 bit right shift In this case, rounding processing becomes effective, and the required mantissa and exponent correction amounts can be obtained by considering the pit position where +1 addition is performed in rounding processing and the presence or absence of 1-bit shift processing, so the shift circuit By determining the upper two bits (bit position: 25°24) of the output result of the mantissa calculation circuit 2, the normalization shift processing by the normalization shift circuit 4 can be invalidated. It is possible to distinguish between a case where the mantissa part of the output of the rounding circuit 5 is valid and a case where the mantissa part of the output of the rounding circuit 5 is valid, and thereby the normalization process and the rounding process can be executed in parallel. becomes possible.

The pattern of the upper 2 bits (bit positions: 25, 24) is °00゛, "01'", "io"'
11'' will be described in detail below with reference to the data format shown in FIG.

■ The upper 2 bits of the output of the mantissa calculation circuit 2 are II O
In the case of the OII pattern, as shown in FIG.
A left shift operation is performed on the bit (i is the pit position of the hidden bit). As a result of this left shift operation, the lower digits are supplemented with one or more "0" bits, so the rounding process becomes invalid υ, and the output of shift circuit 4 becomes valid. Bit 1 is shifted from bit 23 after the shift. This becomes the output of circuit 4.

■ The upper 2 bits of the output of mantissa calculation circuit 2 are 01'''
In the case of turn 9, no left shift operation is performed, so the output of the rounding processing circuit 5 is valid.

As shown in Figure 3 (b), υ rounding is performed by adding 1 to the least significant bit, and as a result, there is no digit and the most significant bit (bit position: 25) is shown in Figure 3. As shown in (), when the result is 0'', bit 23 of the addition result
bit 1 is generated, and the most significant bit (
Bit position: 25) is 1゛' as shown in Figure 3)
When , bit 2 from pinto 24 of the addition result becomes the output of the rounding processing circuit 5, respectively.

■ The upper 2 bits of the output of the mantissa arithmetic circuit are "10'"
In the case of the pattern, the left shift operation is not performed, so the output of the rounding circuit 5 is valid. Figure 3 ((E)
As shown in the figure, rounding is performed by adding 1 to the second lower bit (bit position: 1) corresponding to the extension bit, and since bit 24 is '0', regardless of whether there is a carry or not, Bits 24 to 2 of the addition result become the output of the rounding circuit 5.

■ If the upper two bits of the output of the mantissa arithmetic circuit 2 are a pattern of 11'', the left shift operation is not performed and the output of the rounding processing circuit 5 becomes valid. In this case, as shown in FIG.
As shown in ), the second lower bit (bit position: l) is always 0', so there is no need to add 1.
Therefore, the pinto 2 from bit 24 of the output of the mantissa calculation circuit 2 becomes the output of the rounding processing circuit 5 as it is.

Next, the case where the exponent part, which is the final result, is obtained from the preprocessing section 1 will be explained. For the exponent part of the final result, the selection circuit 10 selects the correction amount range from the normalized shift amount detection circuit 3 or the correction amount from the rounding processing circuit 5, and the exponent part calculation circuit 6 selects the correction amount range from the normalization shift amount detection circuit 3 or the correction amount from the rounding processing circuit 5. This is obtained by correcting the exponent part based on the value of the selected correction amount.

First, in the case of (■) above, a (1-24) bit left shift operation is performed on the output of the mantissa calculation circuit 2 and the output of the shift circuit 4 becomes valid, so the normalized shift amount detection circuit 3 The output correction values "+" and "-24++" are selected by the selection circuit 10.

In addition, in the cases of ■, ■, and ■ mentioned above, the output of the rounding processing circuit 5 is valid because the left shift operation is not performed, so the correction amount output from the rounding processing circuit 5, that is, the overflow bit ( The value of bit position: 25) is selected by the selection circuit 10. In other words, in the case of ■, as shown in (c) in Figure 3, when the value of the overflow pit after addition in rounding processing is 0'', the value is 0'';
As shown in , when the overflow bit after addition is 1", "+1" is selected as the correction amount. Also, ■,
In the case of ■, the value of the overflow bit is "1" as shown in (e) and (f) of Figure 3, so "+
1'' is selected as the correction amount.

As explained above, in this embodiment, the mantissa part of the final result is the output of the normalization shift circuit 4 in the case of (■) mentioned above, and the output of the rounding processing circuit 5 in the cases of (■, ■, ■) is selected by the selection circuit 11 and supplied to the post-processing section 7. In addition, the correction amount of the exponent part of the final result is 1-24'', which is the output value of the normalized shift amount detection circuit 3 in the case of ■.
But ■.

In the case of ■,
1”), 0゛′ or °+1′″ is the selection circuit 1
Selected by 0.

Therefore, normalization processing and rounding processing can be executed in parallel, and floating point calculation time can be shortened by omitting rounding processing when it is disabled. That is, if the normalization processing time is Tn, the rounding processing time is Tr, and the other processing time is Tm, generally Tn > Tr, so assuming that the delay time of the selection circuit can be ignored, the floating point calculation time T is Tm +
Therefore, since T(Tm + Tn + Tr), the floating point calculation time T can be shortened by the time equivalent to the rounding processing time Tr.

(Effects of the Invention) As described in detail above, according to the present invention, when normalizing the intermediate result of the mantissa operation, attention is paid to the normalization shift amount that makes rounding processing invalid, and the intermediate result is By classifying, normalization processing and rounding processing can be executed in parallel, and by adding some hardware such as a selection circuit, floating point calculation time can be reduced by the time required for rounding processing.

The present invention utilizes floating point numbers (
-1) s・2e−127・(1+f) and 0≦f<1 Not limited to the 32-bit data format with teal, but a general floating point data format with an exponent and a mantissa. It can also be applied to the case of , and similar effects can be expected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIGS. 2, 3, and 3 are diagrams showing data formats, and FIG. 4 is a block diagram of a conventional floating point arithmetic circuit. 1... Preprocessing section, 2... Mantissa calculation circuit, 3...
Normalized shift amount detection circuit, 4... Shift circuit, 5...
- Rounding processing circuit, 6... exponent part calculation circuit, 7... post-processing section, 10.11... selection circuit. Patent applicant: Oki Electric Industry Co., Ltd. Figure 3: First operand, second operand Operation result Conventional floating/multiple point calculation circuit Figure 4

Claims (1)

[Scope of Claims] A mantissa calculation circuit that performs an operation between mantissa parts after digit alignment; and a normalization shift amount detection circuit that detects a shift amount for normalizing the output from the output of the mantissa calculation circuit. a shift circuit that shifts and normalizes the output of the mantissa calculation circuit according to the shift amount; a rounding circuit that performs rounding processing of the output of the mantissa calculation circuit; and a shift circuit that performs rounding processing of the output of the mantissa calculation circuit; a selection circuit that selects the output of the shift circuit when the value is a value to be invalidated, and selects the output of the rounding circuit when the value is not an invalid value, and uses the selection circuit as the result of the mantissa operation. Decimal point calculation circuit.