JPH0221489A - Picture memory device - Google Patents

Abstract

PURPOSE:To prevent data in a non-selection area from disappearing by refreshing the non-selection area according to an address indicated by a non-selection area activation circuit. CONSTITUTION:An area set as non-selection by using the non-selection area activation circuit 2 is refreshed. In other words, in an address preset mode, a block where an A area 4 exists is selected, and no cessation of a B area 5 occurs even when the data is read out, and refresh is always performed, and even in a case where a time required for the transition from the A area 4 to the B area 5 takes a long time exceeding a data holding time like a thermal head, no disappearance of the data in the B area 5 that is the non-selection area occurs. Also, the non-selection area activation circuit 2 for that purpose is formed in simple constitution consisting of OR circuits 21 and 22. Therefore, it is not required to enlarge the scale of an internal or external control circuit or to complicate a timing, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic RAM type in which a memory cell array is divided into a plurality of regions, and these regions are used for selection and non-selection in order to reduce power consumption. Summary of the Invention] The present invention provides an image memory device in which a memory cell array is made up of a plurality of divided regions and each block in the selected region is addressed, in which an unselected region is activated by an unselected region activation circuit. By refreshing according to a designated address, data is prevented from disappearing in a non-selected area.

[Conventional technology]

As image memory devices, memory devices that enable horizontal block access are known (for example, "Nikkei Electronics J, k421. pp. 147-162, published by Nikkei McGraw-Hill (Nikkei BP) ]
reference).

This block access is performed by setting the image memory device with this function to address precent mode (APM mode), which is different from the normal usage mode, and then inputting the specified address from the required pin. be done. The block access is used, for example, when forming an image using a thermal head. This is because in the case of a thermal head, the length of the thermal head can be reduced by transferring image data for each data in the vertical direction, unlike in the case of a television signal which is read out line by line. That is, the thermal head forms an image by scanning in the vertical direction.

FIG. 5 shows a conventional image memory device. When using a thermal head, blocks are sequentially selected starting from the 0th block. For example, when selecting the jth block, the diagonal vA in the figure
The area is taken as the area for reading, and data for each line in the 0th block is sequentially output for 263 lines.

After reading this j-th block, the next j-th block
Reading of one block begins.

By the way, in general, memory cells of an image memory device have a memory cell array in a region 51 .
It is divided into a BSN area 52, and row decoders and sense amplifiers are provided independently for two systems, A and B.

For example, as shown in FIG. 5, when the j-th block of the A region 51 is selected, only the AfII region 51 requires power, and the unselected BeN region 52 requires almost no power, so the power consumption is reduced. can be reduced. The selection is made using the activation signal As, which uses the LSB of the address signal.
el+ Controlled by Bsel.

[Problem to be solved by the invention]

However, as mentioned above, in order to reduce power consumption, in an image memory device that has selected areas and non-selected areas, when addresses are sequentially assigned in address preset mode and block access is performed, some areas are not selected. Image data may disappear in the area.

That is, in the case of a thermal head, scanning starts from the 0th block, and after all data in the A area 51 has been transferred, it moves to the BeM area 52. In particular, in a thermal head, the time required to move to the B area 52 is longer than the data retention time of a DRAM memory cell. Therefore, by the time the reading of the A area 51 is completed, the data in the B%p area 52 has already disappeared, making it difficult to read the data.

On the other hand, when auto-refreshing only non-selected areas, the scale of the internal or external circuit becomes large, and at the same time, complicated timing control is also required.

SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, the present invention aims to provide an image memory device that prevents image data from disappearing in a non-selected area when blocks are accessed by sequentially specifying addresses. do.

[Means to solve the problem]

In order to achieve the above object, an image memory device of the present invention has a memory cell array consisting of a plurality of divided regions, each of the plurality of regions is composed of a plurality of blocks, and the plurality of regions are each composed of a plurality of blocks. The blocks in one of the areas are sequentially addressed and selected, and the other areas are made unselected and refreshed according to the address specified by the unselected area activation circuit.

Here, the unselected area activation circuit may function in a mode in which blocks are sequentially addressed and selected. When refreshing according to a designated address, corresponding word lines in both selected and non-selected areas of the corresponding address may be driven.

(Operation) By refreshing the unselected area using the unselected area activation circuit, data loss is prevented.At this time, by refreshing according to the specified address, the unselected area is refreshed. There is no need to increase the scale of the area activation circuit.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

The image memory device 1 of this embodiment, as shown in FIG.
It has ports for input and output, and the memory cell array is divided into two. Especially address preset mode signal A
It has a non-selected area activation circuit 2 controlled by PM and each activation signal A se l +Bsel,
In the address preset mode, non-selected areas are refreshed to prevent data from disappearing.

First, the circuit configuration will be described. As shown in FIG. 1, a memory cell array 3 is provided, and the memory cell array 3 is divided into an Ael region 4 and a Bti region 5. The memory cells arranged in a matrix in the memory cell array 3 are DRAM memory cells, and are connected to the bit line BL.
, BL, and has, for example, one transistor and one capacitor structure.

In each region 4, 5, the word line WL is divided, and the sense amplifier and row decoder are also independent. That is, the ASI area 4 includes the sense amplifier 7A and the row decoder 6.
In the B region 4, a sense amplifier 7B and a row decoder 6B are provided adjacently. These A2X area 4°B area 5 are in normal mode.
The unselected area on the side that is not accessed becomes dormant. The block selector 8 is provided adjacent to the sense amplifiers 7A and 7B, and is an input/output boat that selects a block of the memory cell array 3 and performs transfer with the input/output boat.
Data register 10.11 and serial register 9.12
Manual data is inputted via the serial register 9 and data register 10, and output data is outputted via the serial register 12 and data register 12.

The non-selected area activation circuit 2 has a circuit configuration shown within the dotted line in the figure, and consists of two OR circuits 21 and 22. These O
Each one input of the R circuits 21, 22 is an address preset mode signal APM.

Also, the other input of the OR circuit 21 is A? The other input of the OR circuit 22 is the activation signal Asel in the iI region, and the other input is B? This is the activation signal Bsel for the iJl area. These O
The outputs of the R circuits 21 and 22 are sent to the row decoder 6A.

6B, sense amplifiers 7A, 7B, etc., and serve as signals for activating each region 4, 5, respectively.

The output of the OR circuit 21 is OR to activate the AiW region 4.
The output of circuit 22 is used to activate BIN area 5. The level of the address preset mode signal APM becomes "H'" level (high level) in the address preset mode, and as a result, each output of the OR circuits 21 and 22 also becomes "H'" level (high level).
Therefore, the sense amplifiers 7A and 7B and the row decoder
A and 6B will be activated and unselected? In the +I region, the cell is refreshed simultaneously with reading, and in the normal mode, the level of the address preset mode signal APM is 'L' level (low level).Therefore, each activation signal Asel+B sel is each OR
The signal is transmitted to each region 4, 5 via the circuits 21 and 22, and in the normal mode, the effect of reducing power consumption by dividing the memory cell array 3 can be obtained.

Next, the operation in the address preset mode will be explained with reference to FIG. Here, A in Figure 1
The first row of word lines in Si region 4 is word line WLa.
Let it be i and B? The word line in the first row in 1M area 5 is assumed to be word line WLbi.

Now, as shown in Figure 2, the time is up. The level of address preset mode signal APM changes from “L°” level to “
H” level, and the image memory device 1 of this embodiment
The normal mode leads to an address preset mode in which blocks are sequentially addressed and selected. This address preset mode signal APM is OR@path 21,2
As a result, the unselected area activation circuit 2 outputs a signal for activating both areas 4.5.

LS of the specified address when subsequently accessing the block
From B, the level of the activation signal Asel changes from the °°L° level to the H° level (time 1°). In normal mode, this activation signal Asel activates A8i area 4.
However, in the address reset mode, the output from the non-selected area activation circuit 2 is not affected.

Then, in the case of a thermal head, for example, blocks are accessed in order from the 0th block according to the specified address. Each block is sequentially accessed from the 1st row to the 263rd row, and each block is made up of, for example, 60 words. In FIG. 1, the shaded area is the area of the j-th block, and the i-th row of the 0th block
At time 0 1 shown in FIG.
a+ is selected, and at the same time, the i-th row word line WLbi of Bjfff area 5 is also selected. The selection of the word line WLai is for reading the data of the memory cells of the j-th block, while the selection of the word line WLb+ is for refreshing the memory cells of the first row in the B area. Then, time. 1, A SJI region 4 i-th
+1st row word line WLa++1 is selected, and at the same time B
Word line WLbi+1 in the i+1st row of SI area 5 is selected. The word line WLa++1 is for J-selling of data, and the word line WLbi+1 is for refreshing. At the next time t, 2, the i+2th
The word yAWLa++2 in the row is selected, and at the same time, the word line WLbi+2 in the i+2nd row of the B area 5 is selected. This is also selected for the same purpose. Thereafter, each word line is selected in sequence, and reading and refreshing are similarly performed on all rows. Similar control is performed in the next block, and when reading moves to area B, the word line WLa
is used for refreshing, and word line WLb is used for reading.

As described above, in the image memory device of this embodiment, even when a certain block of A8N area 4 is selected in the address preset mode and data is being read,
BwI area 5 is not paused and is constantly refreshed. Therefore, like a thermal head, Aw
Even if the time required to move from the i-area 4 to the B-area 5 is longer than the data retention time, the data in the B-area 5, which is a non-selected area, will not disappear.
The remaining non-selected area activation circuit 2 includes an OR circuit 21 .
It has a simple configuration consisting of 22 pieces. Therefore, there is no need to increase the scale of the internal or external control circuit or to complicate the timing.

Next, other cases using the address precent mode will be explained with reference to FIGS. 3 and 4.

As shown in FIG. 3, the memory cell array 31 is set to A? IN
The area 32 and the BwI area 33 are assumed to be comprised of the area 32 and the BwI area 33. Note that the row decoder, sense amplifier, block selector, etc., and non-selected area activation circuit are the same as those in FIG. 1, and illustration thereof is omitted. This memory cell array 31 includes A
The first screen data is stored in the 8i area 32, and the B area 3
3 stores second screen data. This is controlled by vertical clear pulses CLR, horizontal clear pulses HCLR, and increment pulses INC, and after outputting the data of the first screen, the data of the second both sides are output. Here, the vertical clear pulse VCLR+t is a pulse that resets the vertical address counter, and the horizontal clear pulse HCLRR is a pulse that resets the horizontal address counter.

Further, the increment pulse INC is a pulse for incrementing the data of the vertical address counter by one and moving the data to the next line.

Even when performing such control, as shown in Figure 4,
When the address preset mode signal APM is set to "H" level, the non-selected area is not paused as usual, but is refreshed by the non-selected area activation circuit.

That is, when ADD o-1 is set to O in FIG. 4 (addressing the 0th block), the output signal is 0. , the data of the first screen is output. At this time, the BpI area 33 where the second screen is stored is refreshed according to the vertical address counter incremented by the increment pulse INC. Next, A
Conversely, when DDo~3 is set to k (first block addressing), refresh is performed in the A area 32 according to the vertical address counter. When the amount of data for each screen is equivalent to one field, refreshing the unselected area with a simple circuit that does not require complicated timing is better than not refreshing the unselected area until the vertical blanking period. will be held.

In addition, in the above-mentioned embodiment, an example was explained in which the memory cell array was divided so as to divide a word line, but the present invention is not limited to this, and a plurality of regions may be formed by dividing a bit line. Further, the number of divisions is not limited to two, and the present invention can be applied to picture-in-picture, 9 multi-pictures, and the like. Further, the image memory device of the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist thereof.

〔Effect of the invention〕

In the image memory device of the present invention, in a mode in which blocks are sequentially addressed and selected, the unselected area is refreshed according to the address specified by the unselected area activation circuit. Even if the time until access exceeds the data retention time, it is possible to prevent data from disappearing. In addition, the circuit configuration of the non-selected area activation circuit does not require complicated timing control or increase the circuit scale (it can reduce product costs and shorten the design period).

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the image memory device of the present invention, FIG. 2 is a timing chart showing an example of its operation, and FIG. 3 is a schematic diagram of another example of the image memory device of the present invention in operation. , FIG. 4 is a time chart for explaining the operation of the image memory device shown in FIG. 3, and FIG. 5 is a block diagram showing an example of a conventional image memory device. 1... Image memory device 2... Unselected area activation circuit 3... Memory cell array 4.5... Areas 6A, 6B... Row decoders 7A, 7B... Sense amplifiers 21.22. ...OR circuit APM...Address preset mode signal Patent applicant Sony Corporation patent attorney Akira Koike (and 2 others) Thailand: l:〉σ Mart No. 2 Engineering Ichi

Claims (1)

[Claims] An image memory device having a memory cell array consisting of a plurality of divided areas, each of the plurality of areas consisting of a plurality of blocks, wherein the block in one of the plurality of areas is An image memory device characterized in that areas are sequentially addressed and selected, and other areas are made unselected and refreshed according to addresses specified by an unselected area activation circuit.