JPH02214281A - Compression device for video signal - Google Patents

Abstract

PURPOSE:To efficiently compress a video signal by obtaining an interpolation block of a block not extracted with respect to a picture element position and applying orthogonal transformation coding to the sum or difference between the block not extracted and the interpolation block. CONSTITUTION:A division circuit 2 divides an input signal into plural blocks in which they have respectively a matrix picture element arrangement and then divides the plural blocks into optional blocks X and Y. Then an interpolation circuit 3 obtains an interpolation block YX from the block X with respect to the picture element position of the block Y, an adder circuit 4 obtains an arithmetic block Z being the sum of the block Y and the interpolation YX, and an orthogonal transformation coding circuit 5 applies compression processing to the block X and the arithmetic block Z through orthogonal transformation coding. Thus, an object picture number is not increased even in a video signal of nonmatrix state picture element arrangement, the sum and difference of each block form a matrix state picture element arrangement respectively and the compression of the video signal by efficient orthogonal transformation coding is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal compression device that uses a non-matrix pixel array video signal as an input signal.

2. Description of the Related Art One of the techniques for compressing video signals is dividing the video signal into blocks and performing orthogonal transform encoding.

If the input signal is a video signal with a matrix pixel array,
As shown in FIG. 7, this video signal is divided into blocks and transform encoded along coordinate axes H1 and vl that are orthogonal to each other. In the figure, ◯ marks indicate pixel positions, and broken lines indicate block boundaries for orthogonal transformation encoding, and in this conventional example, one block includes 16 pixels. Also, Hl
is a horizontal transformation coordinate axis for orthogonally transforming a video signal, and vl is also a vertical transformation coordinate axis.

The transform-encoded signal represents two-dimensional frequency information on the coordinate axis HLVI. Using the two-dimensional frequency information, the amount of information is compressed by reducing redundant information such as high-frequency components and diagonal components of the signal by utilizing the statistical properties and visual characteristics of the original video signal. Hadamard transform, discrete cosine transform (DCT), etc. are used as the orthogonal transform method.

Next, a conventional video signal compression technique using a non-matrix pixel array video signal as an input signal will be described with reference to FIGS. 8 and 9.

FIG. 8 is a diagram of a sampling pattern for explaining the first conventional video signal compression technique, in which the pixel arrangement is in a quincunx shape with an offset between lines, that is, in a non-matrix shape. The O mark represents the position of the pixel. In the figure, broken lines indicate block boundaries for orthogonal transform encoding, and in this conventional example, one block includes 16 pixels. Further, H2 is a horizontal transformation coordinate axis for orthogonally transforming the video signal, and V2 is a vertical transformation coordinate axis. However, the conversion coordinate axis v2 does not form a straight line because the sampling pattern is non-matrix.

Such a pixel arrangement is seen in the MULE signal that is scheduled to be used for satellite broadcasting of high-definition television signals. In addition, in the same pixel arrangement, the frequency band in the diagonal direction is halved compared to the frequency band in the horizontal and vertical directions, and this can also be seen in signals obtained by subsampling the original matrix video signal as a compression means by reducing the diagonal components of the video signal. It will be done.

FIG. 8 is a diagram of a sampling pattern for explaining the second conventional example of video signal compression technology, in which the pixel arrangement is similar to the first conventional example, in a quincunx shape with line-to-line offset, It has a matrix shape. In the figure, the 0 mark represents the position of a pixel, and the x mark is an interpolated pixel obtained from the value of the pixel ◯. The broken lines are block boundaries for orthogonal transform encoding, and in this conventional example, one block includes 16 pixels and 16 interpolation pixels.

Further, H3 is a horizontal transformation coordinate axis for orthogonally transforming the video signal, and V3 is a vertical transformation coordinate axis.

When performing orthogonal transformation on a video signal divided into blocks as described above, transformation coding is performed along transformation coordinate axes H3 and v3. However, the conversion coordinate axis v3 becomes a straight line because the sampling pattern changes from a non-matrix shape to a matrix shape due to the interpolation pixels.

Problems to be Solved by the Invention However, in the first conventional example, since the transformation coordinate axis v2 is not linear, the transformation coordinate axes H2 and V2 are not perpendicular to each other, and even if the transformation encoding is performed, the transformation coordinate axis V2 direction is not the transformation coordinate axis H2 direction. Frequency components will be included. In other words, the frequency information in the direction of the transformation coordinate axis H2 is added to the frequency information in the direction of the transformation coordinate axis V2, resulting in an orthogonal transformation that obtains two-dimensional frequency information, resulting in a problem that efficient compression of the video signal cannot be performed.

Further, in the second conventional example, the conversion coordinate axis v2 is linear,
Although the conversion coordinate axes H2 and v2 are orthogonal, since the interpolation pixel x is used, even if the video signal is in an area of 166 pixels,
Including the 6 interpolated pixels, conversion encoding must be performed as a video signal for 32 pixels within the block. In other words, the number of target pixels itself increases, resulting in an increase in scale and a delinquent rate of compression processing.

In view of this point, it is an object of the present invention to provide an efficient video signal compression apparatus even for video signals with non-matrix pixel arrangement.

Means for Solving the Problem: A dividing circuit that divides a video signal of a non-matrix pixel array into a plurality of blocks, each of which is a matrix pixel array, and extracts any block from the plurality of blocks that is not extracted. an interpolation circuit that obtains an interpolation block for a pixel position of a block; an arithmetic circuit that obtains the sum or difference between an unextracted block and the interpolation block; and an orthogonal transformation code that orthogonally transforms the extracted block, sum, and difference. This is a video signal compression device comprising a circuit.

Effect of the Invention With the above-described configuration, the present invention does not increase the number of target pixels even in the case of a video signal with a non-matrix pixel arrangement, and each block, difference, and sum are each arranged in a matrix pixel arrangement, resulting in efficient orthogonal processing. Video signals can be compressed by transform encoding.

Embodiment FIG. 1 is a block diagram of a video signal compression apparatus in a first embodiment of the present invention. In the same figure, 1 is non-ma)
Input terminal for receiving an IJ box-shaped video signal as an input signal, 2
3 is a dividing circuit that divides the input signal into a plurality of blocks, each of which has an IJ box-like pixel array, and divides the plurality of blocks into arbitrary blocks X and Y; An interpolation circuit 4 obtains an interpolation block Yx for the pixel position of the block Y, and 4 is an adder circuit having an addition function to obtain an arithmetic block Z that is the sum of the block Y and the interpolation block YX. Reference numeral 5 denotes an orthogonal transform encoding circuit that compresses the block X and the calculation block Z by orthogonal transform encoding, and 6 outputs the output of the orthogonal transform encoding circuit 5 as an output signal of the video signal compression apparatus. It is an output terminal.

FIG. 2 shows a sampling pattern for explaining the operation of the compression device. The pixel arrangement of the input signal to input terminal 1 is in the form of a quincunx with an offset between lines, and is not in the form of a matrix. The ◯ and * marks represent pixel devices. However, the pixel arrangement of only the pixel ○ and only the pixel ・ is in a matrix shape. Therefore, first of all, the dividing circuit 2 is
Each pixel group of pixel o1 is divided into blocks each having a nu matrix (n is a positive integer). Second
Figure X shows a block in pixel ○ extracted as the block Also, at this time, the order n of the matrix in the block is 4
The number of pixels in the block is 1G pixels.

Next, the interpolation circuit 3 uses the block
An interpolation block Yx to be interpolated for the pixel position is determined. As for the interpolation method, the amplitude information is constant for the frequency components included in block X, and the phase information is fixed for the frequency components included in block
The phase of each frequency component is shifted by the change in position from block Y to block Y. The interpolation method in the interpolation circuit 3 will be explained below.

Discrete cosine transform is a method for frequency decomposing a blocked signal. Let C be an n persimmon discrete cosine transformation matrix, and the (1, j) elements of C are Qt+, 4+ (where I, j=0.1..., (n-1) is Qx
, 1+ :dlcOs(J(1+1/2)π/n)...
-...(t). Here, d is d...((1/n)"""1"0......
...(2) (2/n)"': j≠0. Using this C and the transposed matrix CI of C,
The output matrix W obtained by performing two-dimensional discrete cosine transform on the input pixel block X (matrix X) is determined by the following equation.

W=CTXC・・・・・・・・・・・・・・・
(3) Each element W (l) of equation W (3) indicates amplitude information of horizontal and vertical two-dimensional frequency components. However, since the phase information is fixed in the transform of equation (3), a transform is performed to shift the phase for each frequency component.

The discrete cosine transformation matrix is 0CT=CTC=E (unit matrix)...(4)
Therefore, the inverse discrete cosine transform of equation (3) is x
= cwcτ・・・・・・・・・・・・・・・・・・
...It is expressed as (5). Equation (5) also represents X ” ”, X 7. :w+t,ucEuC”=
",XX2Wu+++F++"""...(G). However, the elements of EIJ are (k,
l:0.1. -, n-1) The elements of Fr1 are a column vector indicating a single frequency component whose phase advances by iπ/n per pixel in the vertical direction, and a single frequency whose phase advances by jπ/n per pixel in the horizontal direction. It is the product of the row vector representing the components. Therefore, by giving an offset to the phase of each frequency component of these column vectors and row vectors, it is possible to represent a two-dimensional frequency component in which the frequency and amplitude are equal and only the phase is shifted.

Now, let us consider the real number S as a variable and the (1
゜j) element as 1)s(1,71: dlcOs(1(j+1/2+s
)π/n)...(9), the predicted pixel block at a position moved by a pixel in the vertical direction and b pixels in the horizontal direction (asb is any real number) with respect to the input pixel block X. From formulas (6), (7), and (8), X and b are as follows:
b=P −” W P b・・・・・・・・・・・・
...It can be expressed as (10). Also, from equation (3), equation (10) is
b = (CP-)”X(CPk)”R-”X Rb・・・・・・・・・・・・・・・
...(11) can be done. Here, the real number S in equation (tt)
The IJ matrix R1 is a conversion matrix in which the amplitude information is constant and the phase information is shifted by S pixels.

From the above, the interpolation function for obtaining the interpolation block Yx (into matrix Y) from block X to block Y in FIG. 1 is as follows: a = b = 1/2...
......The above formula (11) when (12) is set, so Yx '' X+7g +z*...
It is expressed as (13).

Next, the adder circuit 4 obtains an arithmetic block Z that is the sum of the block Y and the interpolation block YX. The calculation block Z will be explained below.

FIG. 3 is a two-dimensional representation of a frequency range in which a video signal can be transmitted in the pixel arrangement shown in FIG. Third
In the figure, the entire transmittable region of the quincunx-like pixel array is represented by a triangle in which the frequency region in the diagonal direction is halved compared to the frequency region in the horizontal and vertical directions. However, the transferable area of the pixel array of only the pixel O or only the pixel . is only a rectangular range corresponding to (a) in FIG. 3. At this time the 4th
The low-frequency component (a) shown in Figure (a) and the high-frequency folded components (two) from the high-frequency component (B) shown in Figure 3 (Figure 4 (b))
There will be a mixture of

The frequency components of the block Y and interpolation block Y× will be explained. Since both blocks have the pixel arrangement shown in block Y in FIG. 2, low frequency components (a) and high frequency aliasing components (t) coexist in both blocks. However, the frequency components of interpolation block Y× are the same low frequency component (A) and high frequency aliasing component (
The interpolation process is performed by the interpolation circuit 3 from the plot X containing a mixture of Therefore, the low frequency component (
Regarding a), it is in phase with the block Y, but the high frequency aliasing component (2) is out of phase. Therefore,
The frequency components of the arithmetic block 2 summed by the adder circuit 4 are only the low frequency components (a) of the block Y.

The calculation block Z obtained by the addition circuit 4 is orthogonally transformed and encoded together with the block Outputs the signal. At this time, the calculation block Z contains only the low-frequency component (A) as described above, that is, the high-frequency aliasing component (
Since there are no high-frequency aliasing components (compared to the blower Y) during orthogonal transform encoding in the orthogonal transform/coding circuit 5, extraction of two-dimensional frequency information is efficient. As described above, according to this embodiment, even a video signal with a quincunx pixel array can be orthogonally transformed encoded with a matrix pixel array, and moreover, the orthogonal transform encoding circuit requires only five people. Since block Y and calculation block 2 have the same number of pixels as the original video signal,
Compression processing can be performed efficiently without increasing the number of target pixels. Furthermore, since the calculation block Z has no high-frequency aliasing components (one) compared to the block Y, extraction of two-dimensional frequency information by orthogonal transformation is efficient and effective compression processing can be performed.

Next, referring to FIG. 5, a video signal compression apparatus according to a second embodiment of the present invention will be described. The configuration of this embodiment is such that the addition circuit 4 in the configuration of the first embodiment (FIG. 1) is replaced with a subtraction circuit 11 that performs a subtraction function of subtracting block Yx from block Y to obtain calculation block Z. The other configurations are the same as those of the first embodiment.

From the above, the differences between this embodiment and the first embodiment are as follows:
This is a frequency component included in the calculation block Z. As described above, both the block Y and the interpolation block YX contain a mixture of the low frequency component (a) shown in FIG. 4(a) and the high frequency folded component (2) shown in FIG. 4(b). However, the low-frequency component (A) of the interpolation block Yx is in phase with the block Y, but the high-frequency folded component (X) is in reverse phase.

Therefore, in this embodiment, the frequency component of the arithmetic signal Z obtained by subtracting the difference by the subtraction circuit 11 is only the high-frequency aliasing component of the block Y. In other words, when the calculation block 2 is orthogonally transformed encoded by the orthogonal transform encoding circuit 5 in the subsequent stage,
Compared to the block Y, there is only a high-frequency aliasing component (one) and no low-frequency component (a), so extraction of two-dimensional frequency information is efficient and effective compression processing can be performed.

As explained above, according to this embodiment, even a video signal with a quincunx-like pixel array can be orthogonally transformed encoded with a matrix-like pixel array, and moreover, the orthogonal transform encoding circuit 5 can be manually operated by block Y and calculation block 2. Since the number of pixels is the same as that of the original video signal, compression processing can be performed efficiently without increasing the number of target pixels. Furthermore, compared to block Y, calculation block 2 has only high-frequency aliased components (one) and low-frequency components (one).
Since there is no a), extraction of two-dimensional frequency information by orthogonal transformation is efficient and effective compression processing can be performed.

In particular, the high frequency aliasing component (2) (or the high frequency component (A))
Compared to the low-frequency component (A), the amplitude is smaller in -boat fishing and occurs less frequently, so the calculation block 2 containing only the low-frequency component (A) is orthogonally transformed as in the first embodiment. It is advantageous in terms of compression efficiency compared to compression using

FIG. 6 is a block diagram of a video signal compression device according to a third embodiment of the present invention. In the figure, 1 is an input terminal that receives a non-matrix video signal as an input signal, and 2 is a terminal that divides the input signal into a plurality of blocks, each of which has a matrix-like pixel arrangement, and connects the input signal from the plurality of blocks. 7 is a first interpolation circuit that calculates an interpolation block (Yx) for the pixel position of block Y from the block A second interpolation circuit that calculates an interpolation block (referred to as Xy) for the pixel position of block ing. 10 is a subtraction circuit which has a subtraction function to obtain an arithmetic block Z2 by taking the difference between the block X and the interpolation block Xv. Reference numeral 5 denotes an orthogonal transform encoding circuit that compresses the arithmetic block z1 and the arithmetic block Z2 by orthogonal transform encoding, and 6 outputs the output of the orthogonal transform encoding circuit 5 as an output signal of the video signal compression device. It is an output terminal.

The operation of this embodiment will be explained below.

The input signal to input terminal 1 and the operation of dividing circuit 2 are
Alternatively, it is equivalent to the second embodiment, and the input signal of the quincunx-like pixel array and the blocks X and Y of the matrix-like pixel array are as shown in FIG. 2 above.

The interpolation function of the first interpolation circuit 7 is the same as the formula (12) in the formula (11) X a b shown in the first embodiment, where a = b = 1/2.・・・・・・
......(12), and the interpolation block Yx is also the same as equation (13), Yx '' X+/* lzQ
・・・・・・・・・・・・・・・・・・(13). However, the interpolation function of the second interpolation circuit 8 is (11
) In formulas X, b, az b is a = b
= −1/2・・・・・・・・・・・・・・・
...(I4), so the interpolation block Xv is: Xv = X-+z* -+z2...
......(15).

Since the calculation block Z, which is the output of the adder circuit 9, is the sum of the block Y and the interpolation block Y×, the calculation block Z1
is the low frequency component (of the frequency components included in block Y)
A) (see Figure 4 (a)). Furthermore, since the calculation block Z2 which is the output of the subtraction circuit 10 is the difference between the block X and the interpolation block Xv, the calculation block Z2 contains the high-frequency folded component (
(see Figure 4(b)).

As explained above, according to this embodiment, even a video signal with a quincunx-like pixel array can be orthogonally transformed encoded with a matrix-like pixel array, and moreover, the orthogonal transform encoding circuit 5 can be manually operated by the operation block Z+ and the operation block Z2. Since the number of pixels is the same as that of the original video signal, compression processing can be performed efficiently without increasing the number of target pixels. Furthermore, compared to block Y, calculation block Z has only a low-frequency component (a) and no high-frequency aliasing component (two), and calculation block Z2 has a professional frequency component.

Compared to
Therefore, extraction of two-dimensional frequency information by orthogonal transformation is efficient and effective compression processing can be performed. In particular, the calculation block zI and the calculation block z2 that are input to the orthogonal transform encoding circuit 5 both have a low frequency component (A) and a high frequency aliasing component (
This embodiment is advantageous in terms of compression efficiency compared to the first and second embodiments.

As described in detail, according to the present invention, even in a video signal with a non-matrix pixel arrangement, the number of pixels to be orthogonally transformed encoded does not increase from the number of pixels of the original video signal, and the orthogonally transformed Each block to be encoded has a matrix-like pixel array, and orthogonal transformation encoding can be performed on blocks that do not contain folded components and non-folded components, making it possible to compress video signals more efficiently. , its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video signal compression device according to a first embodiment of the present invention, FIG. 2 is a sampling pattern diagram of a video signal for explaining the operation of the device, and FIGS. 3 and 4 are FIG. 5 is a block diagram of the video signal compression device according to the second embodiment of the present invention, and FIG. A block diagram of the video signal compression device in the embodiment, FIG. 7 is a reference diagram of the sampling pattern when the input signal is a video signal with an IJ square pixel array, and FIG. 8 is a sampling pattern in the first conventional example. FIG. 9 is a diagram of a sampling pattern in the second conventional example. 2... Division circuit, 3.7.8... Interpolation circuit, 4.9... Addition circuit, 5... Orthogonal transform encoding circuit, 10 , 11... Subtraction circuit. Name of agent: Patent attorney Shigetaka Awano and one other person
J1 section diagram diagram low familiarity cloudy animal compensation slope high 1 approximate fishing 'f LA99 2 meb ei guest area diagram ○ Quincunx shape (non-matrix shape 2 strokes W:, row sump song pattern 1) − -ayt times g, Fig.

Claims (5)

[Claims] (1) A dividing circuit that takes a video signal of a non-matrix pixel array as an input signal and divides the input signal into a plurality of blocks, each of which has a matrix pixel array, and extracts an arbitrary block from the plurality of blocks. an interpolation circuit that calculates an interpolation block for the pixel position of the unextracted block; an arithmetic circuit that calculates the sum or difference between the unextracted block and the interpolation block; and an orthogonal transformation code for the extracted block and the sum or difference. 1. A video signal compression device comprising: an orthogonal transform encoding circuit that converts (2) The interpolation circuit determines that the amplitude information of the frequency component in the extracted block is constant, and the phase information is shifted by the position change between the extracted block and the non-extracted block as an interpolated block. Claim 1
The video signal compression device described above. (3) A dividing circuit that takes a video signal of a non-matrix pixel array as an input signal and divides the input signal into a plurality of blocks, each of which has a matrix pixel array, and extracts an arbitrary block from the plurality of blocks. a first interpolation circuit that obtains a first interpolation block by interpolating pixel positions of blocks that are not extracted based on the extracted blocks;
a second interpolation circuit that obtains a second interpolation block by interpolating the pixel position of the extracted block based on the unextracted block; and a sum of the unextracted block and the first interpolation block. The present invention is characterized by comprising an addition circuit for determining the difference between the extracted block and the second interpolation block, a subtraction circuit for determining the difference between the extracted block and the second interpolation block, and an orthogonal transformation encoding circuit for orthogonal transformation encoding the sum and difference. Video signal compression device. (4) The first interpolation circuit calculates that the amplitude information of the frequency component in the extracted block is constant, and the phase information is shifted by the position change between the extracted block and the unextracted block. 4. The video signal compression apparatus according to claim 3, wherein the video signal is an interpolation block. (5) The second interpolation circuit calculates that the amplitude information of the frequency component in the unextracted block is constant, and the phase information is shifted by the position change between the unextracted block and the extracted block. 4. The video signal compression apparatus according to claim 3, wherein the number of interpolation blocks is one.