JPH02214138A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a low cost and to enhance a crystalline property and an element characteristic by a method wherein elements are formed respectively on a semiconductor crystal surrounded by an insulating film formed at an inner wall of a U-shaped part and on a semiconductor substrate. CONSTITUTION:U-shaped parts 21 are patterned and formed in a semiconductor substrate 20 by etching prescribed regions on its surface. In this state, an insulating film 22 is formed on the surface of the semiconductor substrate 20; parts formed at bottom faces of the U-shaped parts 21, of the insulating film 22 are etched and removed. Then, a semiconductor single crystal 23 is formed, by a selective epitaxial growth operation, inside the U-shaped parts in which the insulating film 22 on the bottom faces has been etched and removed. In addition, the insulating film 22 outside the U-shaped parts 21 is etched and removed; elements 26, 27 such as semiconductor elements or the like are formed respectively on the semiconductor single crystal 23 isolated by the insulating film 22 formed at inside walls of the U-shaped parts 21 and on the semiconductor substrate 20. Thereby, a low cost is realized, and a crystalline property and an element characteristic are enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device.

[Conventional technology]

2. Description of the Related Art In integrated circuit devices, in order to improve their degree of integration and reduce their size, progress has been made in miniaturization of patterns for forming internal elements such as semiconductor devices. At present, semiconductor devices and the like with submicron rules have been developed, and it is thought that the pattern rules of next-generation devices will progress from submicron to half-micron to quarter-micron orders. Along with this, development of pattern forming techniques is progressing from ultraviolet lithography to X-ray phosphorography to child beam lithography.

Bipolar transistors are integrated circuit elements.

It is provided with active elements such as MO3I-transistors and PI-CMOS transistors which are a combination of bipolar transistors and MOS transistors, as well as passive elements such as resistors and capacitive elements.

Particularly in active devices, miniaturization has a significant impact on device characteristics and manufacturing processes. First, in terms of device characteristics, problems such as short channel effects and narrow channel effects occur where the dark voltage changes as the device shrinks, and punch-through, where a current constantly flows between the diffusion layers due to the proximity of the diffusion layers, occur. There is. These problems reduce the diffusion layer to L
This problem has been solved by adopting a DD (Lightly Doped Drain) structure.

On the other hand, from a manufacturing process perspective, miniaturization of interconnects causes electromigration, in which particles of the interconnect material move due to the electric field and cause disconnections, and the contact holes for connecting the interconnect materials to the elements become smaller. In order to solve the problem of increased contact resistance, the use of high melting point metal materials, silicide, etc. in place of conventionally used wiring materials is being considered. Formation, LOG O
S (Localized Oxidation of
In isolation between elements using the 5ilicon) method, it is not possible to reduce the element area; therefore, trench capacitors, in which a capacitive element is formed by digging a groove in a substrate, or a trench capacitor, in which a capacitive element is formed by digging a groove in a substrate, are used, and in a similar manner, grooves are dug in a substrate to isolate elements. Trench isolation has been proposed. However, problems remain, such as characteristics changing depending on the depth, size, and etching shape of the trench, and the trench capacitor and trench isolation are still in the development stage.

Isolation technology between elements includes pn junction isolation, buried insulation isolation,
Technologies include dielectric separation, air separation, and polycrystalline separation. Among these, buried insulation isolation and dielectric isolation are considered to be used in the formation of minute elements, especially elements below the submicron rule.

FIG. 4 is a sectional view for explaining the buried insulation isolation technique. The substrate 1 is etched to form a trench 2, into which silicon oxide 3. Silicon nitride 4 and polysilicon 5 are sequentially deposited to fill trench 2, and then capped with silicon oxide 6. In this way, the substrate 1 separated by the groove 2
Elements such as semiconductor elements formed in each region above are electrically insulated and separated.

At the Dielectric Separation Research Institute, SOS (Silicon
0nSaphare) technology, So I (Si
licon On In5ulator) technology, S
I M OX (Separat+on by 1m
pIantedOxgen) technology has been proposed. The SO3 technology is illustrated in FIG. An insulating film 8 is patterned on the sapphire substrate 7, and a silicon single crystal 10 is grown on the exposed portion 9 of the sapphire substrate 7 by selective epitaxial growth. Elements such as semiconductor elements are formed on each of the silicon single crystals 10 insulated by the insulating film 8 in this manner.

FIG. 6 is a sectional view for explaining the SOI technology. An insulating IIU 12 is deposited on the silicon substrate 11, and this insulating film 12 is etched to form a portion of the surface of the silicon substrate 11 indicated by reference numeral 13 (hereinafter referred to as "exposed portion 13").
) is exposed, after which silicon 14 is epitaxially grown, and silicon 14 is made into a single crystal over the entire surface by laser annealing using the silicon substrate 11 in the exposed portion 13 as a seed crystal. A silicon substrate 11 insulated by the insulating film 12 and single-crystal silicon 14
Elements such as semiconductor elements are formed in each.

FIG. 7 is a sectional view for explaining the SIMOX technology. As shown in FIG. 7(1), oxygen ions 16 are accelerated with high energy and implanted at a high concentration into the silicon substrate 15. As a result, as shown in FIG. 7(2), the silicon substrate 15 is divided into two regions 1 by the silicon oxide layer 17.
This results in separation into 5a and 15b. Elements such as semiconductor elements are formed in each of the separated regions 15a and 15b.

[Problems to be Solved by the Invention] In the conventional technology described above, in the buried insulation isolation technique shown in FIG. There is a problem in that voids are created and leaks occur from there. That is, for example, when silicon oxide 3 is grown inside the trench 2, a large stress is generated in the silicon oxide 3, and this causes force to act on the silicon oxide 3 inside the trench 2, leading to deterioration of the isolation voltage. Similarly, when the polysilicon 5 is buried in the groove 2, stress also acts, leading to the deterioration of the silicon oxide 3. In this way, the voids are created. Furthermore, since the relatively deep grooves 2 are formed by dry etching, crystal defects occur in the substrate l around the grooves 2.

Such problems do not occur with dielectric isolation techniques that do not require the formation of trenches and use relatively thin oxide films (which do not create stress). However, the S shown in FIG.
The O3 technology has the problem of high costs because sapphire is expensive, so this SO3 technology is not suitable for practical use.

Furthermore, in the Sol technology shown in FIG. 6, a single crystal film (silicon 14) is grown on a dielectric film 12 deposited on a silicon substrate 11 on which elements are formed by a planar process, and elements are also formed on this single crystal film. However, when the single crystal film covers a large area, it is difficult to grow a single crystal and the crystallinity is poor.Also, since it has a multilayer structure, it is difficult to dissipate heat, which deteriorates device characteristics. There is a problem with doing so.

Furthermore, in the SIMOX technology shown in FIG. 7, oxygen ions exist within the silicon substrate 15 with a distribution depending on the distance from the surface of the silicon substrate 15, as shown in FIG. Therefore, when an element is formed in a region where the oxygen ions are present, there is a problem that the element characteristics deteriorate. Furthermore, since the implanted oxygen ions 16 disrupt the crystal order on the surface of the silicon substrate 15, it is necessary to activate the surface by a method such as annealing after forming the silicon oxide layer 17, which is unnecessarily time-consuming.

An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-mentioned technical problems, is advantageous for cost reduction, and further improves crystallinity and device characteristics.

(Means for Solving the Problems) A method for manufacturing a semiconductor device of the present invention includes etching a predetermined region on the surface of a semiconductor substrate to form a recess on the surface of the semiconductor substrate, and a surface of the semiconductor substrate in which the recess is formed. an insulating film is deposited on the recess, a portion of the insulating film formed on the bottom surface of the recess is removed by etching, a semiconductor single crystal is formed within the recess by selective epitaxial growth, and an insulating film is formed outside the recess. is removed by etching, and elements are formed on the semiconductor single crystal surrounded by an insulating film formed on the inner wall of the recess and on the semiconductor substrate, respectively.

(Operation) According to the configuration of the present invention, a pattern of recesses is formed in the semiconductor substrate by etching a predetermined region on the surface of the semiconductor substrate.In this state, an insulating film is formed on the surface of the semiconductor substrate, and the insulating film is formed on the surface of the semiconductor substrate. A portion of the film formed on the bottom surface of the recess is etched away. Then, a semiconductor single crystal is formed by selective epitaxial growth in the recess from which the insulating film on the bottom surface has been etched away. At this time, the bottom surface of the recess Since the surface of the semiconductor substrate is exposed, the semiconductor single crystal formed in the recess can have the same plane orientation as the semiconductor substrate and have good crystallinity.

The insulating film outside the recess is removed by etching, and an element such as a semiconductor element is formed on the semiconductor single crystal and the semiconductor substrate, which are separated by the insulating film formed on the inner wall of the recess. It is formed.

As described above, the present invention does not require the use of expensive materials such as sapphire as in the conventional SO3 technology, and the formation of the semiconductor single crystal in the recess can be easily and easily performed without using laser annealing or the like. Therefore, the semiconductors (semiconductor single crystal and semiconductor substrate) on which devices are to be formed can both have good crystallinity, and productivity can also be improved.

Furthermore, since the semiconductor single crystal and the semiconductor substrate are formed on the same plane, the element does not have a multilayer structure unlike the conventional Sol technology, and therefore heat dissipation is performed well.

Furthermore, unlike conventional SIMOX technology, ion implantation is not performed, so the interface between the insulating film, the semiconductor substrate, and the semiconductor single crystal is clear, and therefore elements are formed in the areas where the insulating film is formed. This can definitely be prevented. Furthermore, surface activation treatment such as laser annealing is not required.

〔Example〕

FIG. 1 is a sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. As a semiconductor substrate, (1
00), P type, and a 3-inch silicon substrate 20 with a specific resistance of 10 ohm-cm, a predetermined area of this silicon substrate 20 is exposed to light according to existing photolithography to form a resist pattern, and then the silicon substrate 20 is etched by dry etching. A recess 21 having a depth of 3 μm is formed in a pattern. Thereafter, a silicon oxide film 22 serving as an insulating film is deposited to a thickness of 0.5 μm over the entire surface of the substrate 20 by plasma CVD. This state is shown in FIG. 1(1).

Note that the photomask shown in FIG. 2 is used in the photolithography. In FIG. 2, the shaded area is a light-shielding area where photoresist remains, and the remaining area is a light-transmitting area, and no photoresist remains on the surface of the silicon substrate 20 corresponding to this area. For example, one light-shielding portion and one light-transmitting portion have a square shape with one side of 11 tm.

The silicon substrate 20 is etched by reactive ion etching using a mixed gas of SF and CCP as an etching gas. The etching conditions at this time are as follows.

Gas flow rate SF, gas: 20sccmCCF! 4 gas: 5 sec Gas pressure: 10 mTorr RF power: 150 W Etching time: 6 min After etching, the photoresist is removed by dry etching using 02 gas under the following conditions.

Gas flow rate 50sec*Gas pressure
100 mTorrRFiii force
100W etching time 10a+
In addition, the formation of the silicon oxide film 22 by plasma CVD uses a mixed gas of 5% silane (SiH4) gas and nitrogen dioxide (NO) gas with argon (A') as the base gas, as described below. Do it with conditions.

Gas flow rate 5it-14 gas: 200secNOx gas: 10 sccm RF power 150 W Deposition time 11 Rice in the plasma C
The silicon oxide film 22 is deposited by VD on the side wall 21a of the recess 21 and the bottom surface 21b thereof.

And, it is applied uniformly over the entire surface of the silicon plate 20 outside the recess 21.

Next, from the state shown in FIG. 1(1), a photoresist is formed on the surface of the silicon oxide film 22 by conventional photography, and a window is formed in the bottom surface 21b7 of the recess 21 in this photoresist. Then, anisotropic etching is performed by dry etching to remove the silicon oxide film 22 on the bottom surface 21b of the recess 21. After this, silicon substrate 2
The photoresist remaining on the 0 surface is removed by dry etching under the same etching conditions as described above. This state is shown in FIG. 1(2).

Etching of the silicon oxide film 22 is performed using CHFy gas, and the etching conditions at this time are as follows.

Gas flow rate 20sccvA gas pressure
5 mTorrRF power
120 W Etching time 25+nin From the state shown in FIG. 1 (2), the silicon oxide film 2 on the bottom surface 21b is
Silicon 23, which is a semiconductor single crystal, is epitaxially grown in the recess 21 from which silicon 2 is removed by selective epitaxial growth.

This state is shown in FIG. 1(3). At this time, since the silicon substrate 20 is exposed at the bottom surface 21b of the recess 21, the silicon 23 formed in the recess 21 has the same plane orientation as the silicon substrate 20 and has good crystallinity. It can be formed by The selective epitaxial growth of the silicon 23 is performed using 100% silane (SiH4
) gas as the raw material gas under the following conditions.

Gas pressure 350 5Torr substrate temperature
600° C. RF power 150 W Growth time 60 m1n Under these conditions, the film thickness of the silicon 23 is 4.2 μm. Low gas pressure region below 180 mTorr.

In a high region of 350a+Torr or more, silicon is also deposited on the silicon oxide film 22. Therefore, the gas pressure is 180mTorr<(gas pressure)<350mTorr
It is necessary to set it to Torr.

FIG. 3 shows the temperature dependence of the selective epitaxial growth. That is, depending on the substrate temperature, the silicon deposited is either amorphous or polycrystalline.

It becomes a single crystal, becomes amorphous when the substrate temperature is below 300'C, becomes polycrystalline when the substrate temperature is 300 to 550°C, and becomes single crystal when it is above 550°C. Therefore, it is understood that the substrate temperature during the selective epitaxial growth of the silicon 23 satisfies the temperature conditions for forming a single crystal.

Next, from the state shown in FIG. 1(3), the silicon oxide film 22 on the surface of the silicon substrate 20 outside the recess 21 is removed by reactive ion etching. And Figure 1 (4)
As shown in FIG. 2, semiconductor elements 26 and 27 are formed on the silicon substrate 20 and the silicon 23 separated by the silicon oxide film 22 on the side wall 21a of the recess 21 by the existing planar technology.

Removal of the silicon oxide film 22 by reactive ion etching is performed using CH and gas under the following conditions.

Gas flow rate 15sec Gas pressure
100 5TorrRF power 1
20 W Etching time 5 sin Under these conditions, the etching rate of the silicon oxide film 22 is 1
On the other hand, the etching rate of silicon 23 formed by selective epitaxial growth is 2500 etching/+nin.

Therefore, as mentioned above, the film thickness of the silicon 23 is 4.2 μm.
In this case, after the silicon oxide film 22 is etched away, the surface of the silicon substrate 20 can be almost completely flattened.

In FIG. 1 (4), the parts indicated by reference numerals 26a and 27a of the semiconductor elements 26 and 27 are, for example, MOS).
This is the gate electrode portion of the transistor, and these portions and the silicon 23. For example, a gate insulating film (not shown) is formed between the silicon substrate 20 and the silicon substrate 20.

When the rocking curve of the silicon 23 formed in the recess 21 and the silicon substrate 20 in the semiconductor device fabricated as described above was measured using an X-ray diffraction method, the half-value width of the rocking curve was determined by the silicon substrate 20. It was confirmed that the values were approximately 1# to 2# for silicon 23 and approximately 1# to 2# for silicon 23, and that they had approximately the same degree of long-range order. Furthermore, when short-range ordering was examined using a transmission electron microscope (TEM), it was found that there was no difference in spot position, and short-range ordering was also good.

Furthermore, M was formed on a silicon substrate using normal planar technology.
OS) transistor elements and transistor elements fabricated according to this example were subjected to element life acceleration tests such as temperature rise and pressure tests, voltage-current characteristics, and capacitance-voltage characteristics r stress tests, and there was no difference at all. No deterioration of device characteristics due to chemical reaction was observed.

As described above, according to this embodiment, unlike the conventional SO3 technology shown in FIG. 5, an expensive material such as sapphire is not used, so that a semiconductor device can be manufactured at a low cost. Further, in the recess 21, the silicon 23 is placed on the silicon substrate 20.
Since epitaxial growth can be performed in contact with the silicon 23, a single crystal of silicon 23 can be easily and favorably formed in the recess 21 without performing laser annealing or the like.

Further, as shown in FIG. 1(4), the semiconductor elements 26 and 27 are formed substantially on the same plane, and the conventional Sol shown in FIG.
It does not have a multi-layer structure like other technologies, and therefore has excellent heat dissipation. Furthermore, as the elements are formed on substantially the same plane, the elements will not deteriorate even if the shape of the silicon substrate 20 is somewhat bad. Furthermore, since the interface between the silicon oxide film 22 and the silicon substrate 20 and silicon 23 is clear, it is possible to reliably prevent elements from being formed in an insulator as in the conventional SIMOX technology.

Furthermore, in this embodiment, since the silicon oxide film 22 is formed by the plasma CVD method, the stress can be easily controlled, so that the silicon oxide film 22 does not deteriorate.

〔Effect of the invention〕

As described above, according to the method for manufacturing a semiconductor device of the present invention, there is no need to use expensive materials such as sapphire as in the conventional SO3 technology, so it can be manufactured at low cost and is advantageous in reducing costs. be.

Furthermore, the semiconductors (semiconductor single crystal and semiconductor substrate surrounded by an insulating film in the recess) on which the device is to be formed can both have good crystallinity.

Furthermore, since the element is formed substantially coplanar near the surfaces of the semiconductor single crystal and the semiconductor substrate, it does not have a multilayer structure unlike the conventional SOI technology, and therefore heat dissipation is performed well. Furthermore, unlike conventional SIMOX technology, ion implantation is not performed, so the interface between the insulating film, the semiconductor substrate, and the semiconductor single crystal is clear, and therefore elements are formed in the areas where the insulating film is formed. This can definitely be prevented. In this way, device characteristics are significantly improved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a simplified plan view of a photomask used for forming a recess 21, and FIG. An explanatory diagram showing the crystal characteristics of silicon with respect to substrate temperature during selective epitaxial growth, Fig. 4 is a cross-sectional view to explain buried insulation isolation technology, Fig. 5 is a cross-sectional view showing SO3 technology, and Fig. 6 is S○! Cross-sectional view showing the technology, Figure 7 is SIM
FIG. 8, which is a cross-sectional view showing the OX technique, is a graph showing the oxygen ion concentration distribution within the silicon substrate 15 in the configuration shown in FIG. 20... Silicon substrate (semiconductor substrate), 21... Recess, 22... Silicon oxide film (insulating film), 23...
Silicon (semiconductor crystal), 26.27... Semiconductor element Figure 1 O Het q Fu Rumor Stomach 6-6 Decoy Ken ε. This

Claims (1)

[Claims] A recess is formed on the surface of the semiconductor substrate by etching a predetermined region on the surface of the semiconductor substrate, an insulating film is deposited on the surface of the semiconductor substrate in which the recess is formed, and the recess of the insulating film is a portion formed on the bottom of the recess is etched away, a semiconductor single crystal is formed within the recess by selective epitaxial growth, an insulating film formed outside the recess is etched away, and a semiconductor single crystal is formed on the inner wall of the recess. A method for manufacturing a semiconductor device, comprising forming elements on the semiconductor single crystal surrounded by an insulating film and on the semiconductor substrate.