JPH02214100A - Inspecting device for semiconductor memory - Google Patents

Abstract

PURPOSE:To easily perform blank inspection with high accuracy by inspecting an erasing state by switching a discrimination level from a level switching means. CONSTITUTION:When the voltage of the input terminal CT of a reference bit line voltage switching circuit 6 in a reference bit line voltage switching means is set at a prescribed voltage, the gate voltage of the FET 13 of a reference storage cell from the reference bit line voltage selection circuit 25 of the circuit 6 is switched to the voltage in inspection lower than the voltage in ordinary data readout. Therefore, a detecting signal for reference supplied to a sense amplifier is decreased comparatively than the one is readout, and the blank inspection whether or not a storage content by the FET of each memory cell is erased can easily be performed with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an electronic device capable of writing and erasing memory contents.
P ROM (Erasable and
ProgrammableReact 0nly Me
More specifically, the present invention relates to a semiconductor memory device testing device that is suitably used to test whether the memory contents of an EPROM have been erased by, for example, ultraviolet irradiation.

In some prior art EPROMs, the memory cells are constructed from floating gate MOS transistors. M
OS (Metal Oxide Sem1eond
In a field-effect transistor with a floating gate structure in which Si is embedded as a floating gate in an insulating layer made of, for example, 5iOz, the threshold voltage rises when charge above a certain level is accumulated in the floating gate, and the source-drain voltage of the transistor increases. During this period, even if a normal control gate voltage is applied to the control gate electrode, the control gate electrode is in a non-conducting state, that is, it is in an off state.

On the other hand, the charges accumulated in the floating gate can be discharged by irradiating the gate with ultraviolet light of a certain energy level or higher.

When a voltage is applied to the control gate electrode in this state, the source-drain becomes conductive, that is, turned on. In this way, above a certain level to the floating gate! Data can be stored in the floating gate MO3) transistor depending on whether it is in an accumulation state (also called a program state) in which a load is accumulated or in an erase state in which it is discharged.

In conventional EPROMs, memory cells are arranged in rows and columns, and row addressing lines and column addressing lines wired correspondingly are used to specify memory cells based on input address signals. The detected signal from the memory cell is output to the bit line.

The input address signal also specifies, for example, a reference cell commonly connected to each row addressing line, and derives a reference detection signal to the reference bit line. The detection signal and reference detection signal from these designated memory cells are input to a differential amplifier called a sense amplifier, which outputs data according to the high level or low level of the detection signal with the reference detection signal as the reference level. .

Typically, EPROMs are manufactured by irradiating all memory cells with ultraviolet rays to remove the floating gates that make up the memory cells.
The S transistor is shipped in an erased state with no charge accumulated on its floating gate.

Therefore, in the manufacture of EPROM, the manufactured E
An erasure process in which the PROM is irradiated with ultraviolet rays and an inspection process called a blank check in which it is inspected to see if the EFROM is in an erased state are sequentially performed before shipment. Furthermore, final products are subjected to sampling inspections, and the defective rate of the products is investigated for quality control.

The inspection in the blank check process basically performs the same operation on the EPROM as when reading data, and the output data is a logic "1" corresponding to the state where no charge is accumulated in the memory cell. This is done by checking whether it exists or not.

In other words, the characteristics of the detection signal and reference detection signal input to the sense amplifier are the power supply voltage ■. . In FIG. 4, when the power supply voltage V0°=5 [V], the reference detection signal level (characteristics are shown by line 12) is IV
It is set in advance so that On the other hand, when the memory cell specified by the address signal is in the erased state,
A detection signal of approximately 0.2■ (characteristics shown by line 13) is input to the sense amplifier, and in the program state, the detection signal of approximately 2
■<Characteristics shown in line 11> is input. The sense amplifier determines the programmed state and erased state of the memory cells indicated by lines l1' and 13 based on the reference detection signal level indicated by line 12, and outputs data to a designated address.

Problems to be Solved by the Invention If the ultraviolet irradiation time for EPROM is too short,
Some charge remains in the floating gate of the floating gate MoS transistor that constitutes the memory cell, and when some or all of the memory cell becomes under-erased, the detection signal input to the sense amplifier is as follows:
For example, as shown by line 14 in FIG.
The overall detection signal level is higher than line 13, which indicates that the memory cell is in a sufficiently erased state.

However, due to this insufficient erasure, the signal level is different from the detection signal level (13) in the erased state and the reference comparison signal level (13).
12), even if the reference detection signal level rises to the <12) side, the reference detection signal level (12) by the sense amplifier
As long as it is not difficult to make a comparison with 2), the EPROM outputs data corresponding to the erased state of the memory cell. Therefore, even in an EFROM in which the detection signal level has increased due to insufficient erasure of memory cells, in the blank check process, it is
Like ROM, it is shipped as a product that has been completely erased.

The lack of erasing of memory cells in the EFROM described above is due to
This causes deterioration of data read response time including access time. That is, since charge remains in the floating gate of the floating gate MO3 transistor constituting the memory cell, the resistance between the source and the train increases when a voltage is applied to the control gate electrode and the transistor is in a conductive state. In addition, there is a line capacitance in the bit line from which the detection signal from the memory cell is derived.
Due to an increase in the time constant consisting of the product of the source-drain resistance of these transistors and the line capacitance of the bit line, the data read response time until the data corresponding to the address specified by the address signal is actually output is will increase.

In this way, EPROMs that are insufficiently erased but are determined to be in an erased state in the blank check process will be shipped as final products, unless they are selected as inspection targets in the sampling inspection performed after the blank check process, and will be shipped as final products. Decrease the quality of the product. Therefore, conventionally, it has not been possible to unnecessarily shorten the irradiation time of the EPROM with ultraviolet rays in the erasing process.

In addition, in the sampling inspection performed after the blank check process, in addition to writing and reading data to and from all addresses in the EPROM, and checking the level of the detection signal and reference detection signal actually input to the sense amplifier, the blank check It was necessary to carry out inspections in the process again. This increased the cost of the inspection process and made it impossible to improve productivity.

An object of the present invention is to provide a testing device for a semiconductor memory device that can sufficiently and easily test whether the data storage state of a semiconductor memory element in a semiconductor memory device is in a predefined storage state. It is to provide.

Means for Solving the Problems The present invention provides a plurality of semiconductor memories arranged in a matrix that stores data depending on whether it is in an erased state in which charges are discharged or in an accumulated state in which charges at a predetermined level or higher are accumulated. a plurality of row addressing lines and column addressing lines that individually designate each semiconductor storage element, and from which a detection signal of a level corresponding to the presence or absence of charge accumulation is derived from the designated semiconductor storage element; , are respectively provided on either the row addressing line or the column addressing line, and are commonly connected to a predetermined specific addressing line on the other of the row addressing line or the column addressing line, and are in the erased state or a plurality of reference memory elements fixed in one of the storage states; a detection signal from the designated semiconductor memory element; and a reference from the reference memory element commonly connected to the designated semiconductor memory element. level comparison means for comparing the level with a detection signal for the semiconductor memory element, and the specific address designation line includes a first discrimination level for determining the presence or absence of charge accumulation in the semiconductor memory element, and a level comparison means for comparing the level with a detection signal for the semiconductor memory element. A second level close to a predetermined level corresponding to either the erased state or the accumulated state in the storage element.
The present invention is a semiconductor memory device testing device characterized in that a level switching means is connected to switch and output a discrimination level.

Operation According to the present invention, a level switching means is connected to a specific addressing line to which reference storage elements are commonly connected. This level switching means switches and outputs two types of levels, a first discrimination level and a second discrimination level, to the specific address designation line in order to discriminate whether or not charge is accumulated in the semiconductor memory element. In particular, the second discrimination level is set closer to a level corresponding to a predetermined one of the erased state and the accumulation state in the semiconductor memory element than the first discrimination level.

If the second discrimination level is used as a reference level and the level of either the erased state or the accumulated state, which is set close to the second discrimination level, is compared by the level comparison means, the first discrimination level is used as the reference level. The accuracy of the comparison is improved compared to when

Example FIG. 1 is a circuit diagram of an EPROMI according to the present invention.

The EPROMI includes a memory cell array 11 in which memory cells are arranged in a matrix and derives a detection signal corresponding to a designated address, and a reference cell 13 that is designated in common with the memory cell array 11 and derives a reference detection signal. , and a sense amplifier 5 that compares the levels of detection signals derived from the memory cell array 11 and the reference cell 13.

For each memory cell constituting the memory cell array 11 and the reference cell 13, an n-type channel floating gate MO3) transistor can be used, for example. In the memory cell array 11, a row addressing line extending in the horizontal direction of the drawing and to which the control gate electrodes of floating gate MOS transistors constituting the memory cells are connected for each row is connected to the row address decoder 2 at one end. Further, this row addressing line is connected at the other end to a control gate electrode of a floating gate MOS transistor constituting the reference cell 13.

In the memory cell array 11, the bit line BL, which extends in the vertical direction in the drawing and to which the drain electrodes of floating gate MOS transistors are connected in each column, is connected to the bit line selector 12 at one end, and is connected to the bit line B.
Each L is commonly connected to the sense amplifier 5 via a field effect transistor FET12.

Further, the sense amplifier 5 is connected to a reference bit line B to which train electrodes of a plurality of floating gate transistors (MO3) constituting the reference cell 13 are commonly connected.
One end of R is connected via a field effect transistor FET14.

The transistor FET14 is connected to the bit line selector 12.
A transistor having the same characteristics as the transistor FET12 constituting the is selected. At the gate electrode of the transistor FET14,
For example, a power supply voltage VDD of +5■ is applied to keep it in a conductive state. Each gate electrode of the transistor FET12 of the bit line selector 12 is connected to one column address decoder 4.

A bit line voltage setting means 9 is connected to the other end of the bit line BL extending from the memory cell array 11, and a bit line voltage VBI of, for example, 2 to 3 cm is applied thereto. A reference bit line voltage switching means 10 is connected to the other end of the reference bit line BR of the reference cell 13, and as described later, there are two different types of voltage switching means for normal data read operation and data storage state inspection. Reference bit line voltage VB2. VB3 is applied.

In an EPROMI, when the memory cell array 11 is configured with, for example, 2" = 256 transistors and outputs 1-bit data, the input buffer circuit 7 selects, for example, the upper 4 bits of the 8-bit address signal that are input as rows. The lower 4 bits are applied to the column address decoder 4.The row address decoder 2 applies a predetermined voltage to a specific row address designation line in response to the applied upper 4 bits of the address signal. On the other hand, the column address decoder 4 applies a voltage to a specific gate electrode of the transistor FET12 constituting the bit line selector 12 in response to the applied address signal of the lower 4 bits, so that only the specific transistor FE712 becomes conductive. state and the remaining transistor FE
T12 is in a non-conductive state.

The row address decoder 2 specifies a memory cell for each row address designation line, and the column address decoder 4 determines the conduction/cutoff state of the leap between the memory cell connected to the bit line BL and the sense amplifier 5 by using the bit line BL%. Switch to

As a result, in the memory cell array 11, memory cells corresponding to the input address signals are individually designated.

When the address signal is input to the input buffer circuit 7, the bit line voltage setting means 9
A bit line voltage VBI is applied to each bit line BL from . Further, the reference bit line voltage switching means 1o selectively changes either the read reference bit line voltage VB2 or the test reference bit line voltage VB3 during normal data read operation and during data storage state inspection. Applied to reference bit line BR.

A detection signal from the transistors of the memory cell is input to the sense amplifier 5 in accordance with the address specified by the input address signal. When a designated memory cell is in an erased state, that is, when there is no charge accumulated in its 70-ting gate, the transistor of the memory cell is in a conductive state;
A low level detection signal is derived to the sense amplifier 5. Further, when the designated memory cell is in a programmed state, that is, a state in which charge is accumulated in its floating gate, the transistor of the memory cell is in a non-conductive state, and a high-level detection signal is output to the sense amplifier 5.

On the other hand, the transistor of the reference cell 13 that is commonly connected to the designated memory cell on the row addressing line is in an erased state in which the charge at its floating gate has been discharged, and the transistor in the conductive state is connected to the sense amplifier 5. A reference detection signal of a predetermined level is derived via the FET 14. The sense amplifier 5 compares the detection signal from the designated memory cell of the memory cell array 11 with the reference detection signal derived from the reference cell 13, and sets it to a high level or a low level depending on the comparison result. The signal is sent to the output buffer circuit 8. In this way, the output buffer circuit 8 outputs data at the address specified by the address signal input to EPROMI.

2 is a circuit diagram of the reference bit line voltage switching circuit 6 constituting the reference bit line voltage switching means 10, and FIG. 3 is a circuit diagram of the bit line voltage setting circuit 3 constituting the bit line voltage setting means 9. be. Both FIGS. 2 and 3 isometrically show the circuit configuration at the time of testing the data storage state.

As shown in FIG. 1, the bit line voltage setting circuit 3 is commonly connected to each gate electrode of, for example, an n-type channel field effect transistor FET11, and its source electrode is connected to each bit line BL. The drain electrode is connected to the power supply voltage■. . is given.

Furthermore, each source electrode of the transistor FETII has
The source electrodes of the n-type channel field effect transistor FET15 are connected to each other. The drain electrode of each transistor FET15 is commonly connected to the drain electrode and the gate electrode of an n-type channel field effect transistor FET16, respectively, and the gate electrode is grounded to make all transistors FET15 conductive. The source electrode of the transistor FET16 is grounded.

Referring to FIG. 3, the bit line voltage setting circuit 3 includes, for example, an n-type channel field effect transistor FET.
1 and an n-type channel field effect transistor FET
2, transistors FETI, PET
2 and the gate electrode of the transistor FETI are commonly connected at a connection point 20. Source electrode of transistor FET1 and transistor FET2
The gate electrodes of each have a power supply voltage ■. . is given, and the source electrode of the transistor FET2 is grounded. With such a configuration, the voltage at the connection point 20 is
It is applied to the gate electrode of the transistor FETI, controls the source-drain current of the transistor FETI, and stabilizes the voltage level led out to the connection point 20.

When data is read from the EPROMI, the bit line voltage setting circuit 3 has the circuit configuration shown isometrically in FIG. 3
A gate voltage VGI of ~4■ is applied. As a result, each transistor FET11 becomes conductive, and the power supply voltage V applied to the source electrode. 0 conducts a constant source-drain current to each bit line BL.

As is clear from the configuration of the bit line voltage setting circuit 3 in FIG. 3, each gate of the transistor FET11 connected to the bit line BL can be The gate voltage VGI applied to the electrode can be varied.

As a result, the bit line voltage setting means 9 sets the bit line voltage VBI to the bit line BL, which varies depending on the on/off state of the transistor at the specified address.
Derived as follows.

Here, in the bit line voltage setting means 9, the transistor FET connected to each bit line BL,
15 and transistor FET16 are connected to the bit line BL when the bit line voltage VBI is applied to the memory cell in the programmed state via the bit line BL.
In other words, when a memory cell in a programmed state is selected by an input address signal, all transistors of the memory cells constituting the memory cell array 11 are in an off state. When the bit line voltage VB1 is applied to the bit line BL in this off state, the potential of the bit line BL rises and the transistor F
The potential difference between the gate and source of ET11 approaches the threshold value.

This bit line voltage VB1 is applied to the drain electrode and gate electrode of the transistor FET16 via the conductive transistor FET15, thereby controlling the source-drain leap current of the transistor FET16 and stabilizing the voltage level of the bit line BL. be done.

This increases the source-drain resistance of the transistor FET11, thereby preventing an unstable state in which the potential of the bit line BL transiently changes due to the influence of external noise.

Referring again to FIG. 2, the reference bit line voltage switching circuit 6 includes a reference bit line voltage selection circuit 25 and constant voltage supply means 26 and 27. For example, p-type and n-type channel field effect transistors FET3, FET5, FET4, . The constant voltage supply means 26.27, which includes each pair of FETs 6, supplies a constant voltage V2. V3 respectively. The voltage V2. applied to this reference bit line voltage selection circuit 25. V
3 is each pair of transistors FET3゜FET4, F
ET5. By appropriately selecting each saturation current ratio (β ratio) of the FET 6, the optimum voltage value can be set.

The reference bit line voltage selection circuit 25 includes n-type and p-type channel field effect transistors FET7., which are connected in parallel, respectively. FET8 and n-type and p-type channel field effect transistors FET9
．． It is configured including FET10. transistor FET
7. A read mode selection signal R9 (TS), which will be described later, is applied to the gate electrodes of the transistors FET10, respectively, and the transistors FET8. A test mode selection signal TS (R3), which will be described later, is applied to the gate electrodes of the FETs 9, respectively. Also, a pair of transistors FE connected in parallel
T7. FET8, FET9. At one end of the source and drain electrodes of FET 10 there is a line l6.17
A constant voltage V2. V3 is applied to each terminal, and in response to the above-mentioned mode selection signals R8 and TS from the other end,
Gate voltage VG2. input to the gate electrode of transistor FET13. For example, a voltage of 5 V is applied to a specific input terminal CT of the EPROMI, for example, an address signal, which is derived by switching VG3, during normal data reading, and a voltage of 8 to 9V is applied, for example, when inspecting the data storage state. be done. The voltage detection circuit 21 derives a low level signal when the input voltage is 5V, and derives a high level signal when the input voltage is 8 to 9V. The signals derived from the voltage detection circuit 21 are input to the reference bit line voltage switching circuit 25 as a test mode selection signal TS (R3) and a read mode selection signal R3 (TS) which is inverted by the inversion circuit 24, respectively.

When the test mode selection signal TS (R3) is at a high level and therefore the read mode selection signal R3 (TS) is at a low level, transistors FET7 and FET8 are rendered non-conductive, and transistors FET9 and FET8 are rendered non-conductive. FET 10 becomes conductive. Therefore, by applying the voltage V3 from the constant voltage supply means 27 via the line 17, the gate electrode of the transistor FET13 constituting the reference bit line voltage switching means 10 is supplied with the gate voltage VG.
3 is applied.

On the other hand, when the test mode selection signal TS (R8) is at a low level and the read mode selection signal R3 (TS) is at a high level, the transistors FET7. FET8
becomes conductive, and transistors FET9. FF, T.I.
O becomes non-conductive.

Therefore, by applying the voltage 2 from the constant voltage supply means 26 via the line 16, the transistor FE constituting the reference bit line voltage switching means 10
Gate voltage VG2 is applied to the gate electrode 713.

Referring again to FIG. 1, the transistor FET 13 of the reference bit line voltage switching means 10 is controlled by the voltages V G 2 and V GB applied to the gate electrode, and is controlled by the power supply voltage VDD applied to the drain electrode. The reading reference bit line voltage VB2 and the testing reference bit line voltage VB3 are respectively switched and outputted to the reference bit line BR. Therefore, this read reference bit line voltage V
B2 and reference bit line voltage for inspection VB3
Accordingly, the voltage level of the reference detection signal input to the sense amplifier 5 via the reference bit line BR also changes.

Further, the source electrode of the transistor FET13 is connected to the source electrode of a p-type channel field effect transistor FET16 whose gate electrode is grounded and is in a conductive state, and the drain electrode of the transistor FET16 is connected to an n-type channel field effect transistor FET16. It is connected to the train electrode and gate electrode of transistor FET17. The source electrode of the transistor FET17 is grounded. Such a configuration includes transistors FF, T11, FET15 . It is similar to FET16, and thereby stabilizes the potential of the reference bit line BR.

FIG. 4 shows the voltage level of the detection signal input to the sense amplifier 5 at the power supply voltage ■. . This is a graph shown for.

The voltage level of the reference detection signal applied to the sense amplifier 5 via the reference bit line BR is the power supply voltage ■. . =5 [V] and is represented by a line 12 passing through the voltage 1■. The detection signal derived from the memory cell in the programmed state is at the power supply voltage ■. . =5 [V] A line passing through a voltage of 2V! On the other hand, the detection signal derived from a fully erased memory cell exhibits the characteristic of line 13 passing through a voltage of 0.2V at power supply voltage D=5 [V].

During a normal data read operation, the sense amplifier 5 uses the reference detection signal indicated by line 12 as a reference voltage level, and determines whether the detection signal applied from the bit line BL is at a high level with respect to the reference detection signal, or The detection signal derived from the memory cell specified by the input address signal exhibits the characteristic indicated by line 14 when comparing whether the data is at a low level and sending the corresponding data to the output buffer circuit 8. In this case, the same data as in the case of the line 13 is sent from the sense amplifier 5 to the output buffer circuit 8 because the voltage is at a lower level than the voltage level 12 of the reference detection signal serving as the reference.

On the other hand, in the blank check process to check whether all memories have been erased by ultraviolet irradiation before the EPROMI is shipped, the input voltage of the input terminal CT shown in FIG. 2 is 8 to 9 V. be done. Accordingly, the voltage applied to the gate electrode of the transistor FET13 by the reference bit line voltage switching circuit 6 is switched from the gate voltage VG2 during normal data reading to the gate voltage VG3 during memory state testing. As a result, the reference detection signal input from the reference bit line BR to the sense amplifier 5 is at the level 12 of the reference detection signal set when reading data from EPROMI, as shown by line 15 in FIG. Overall lower than
It is set close to line 13. That is, in this embodiment, the power supply voltage V. , =5 [V], the reference detection signal shifts to the characteristic of the line 15 passing through the voltages 0, 4, for example.

As described above, the reference detection signal used when checking the erased state of EPROMI is set to the voltage level shown by line 15. Therefore, when checking the erase state, the sense amplifier 5 receives a program state detection signal shown on line 11, and a signal shown on line 15 because the memory cell is insufficiently erased.
The memory cell is determined to be in the programmed state when a detection signal represented by line 14 higher than The memory cell is determined to be in the erased state only when the signal, for example, line 13, has a voltage level below the voltage level of line I15 indicating the reference detection signal, and the output data indicates the erased state.

In this way, when inspecting the memory state of a memory cell during a blank check process, by switching the reference bit line voltage to VB2 and shifting the voltage level of the reference detection signal to, for example, line 15, it is possible to detect an insufficiently erased memory. Data corresponding to the erased state is no longer output as in the conventional case with respect to the detection signal derived from the cell and represented by line 14, for example. Therefore, if EPROMs containing insufficiently erased memory cells are included in shipped products, inferior products are shipped whose data read response time is longer than the data read response time of fully erased memory cells. It is possible to prevent an undesirable situation that would lead to a decrease in performance.

As described above, according to the present invention, the erased state of an EPROM can be reliably inspected in a blank check process or the like. Therefore, even if the erase time of the memory cell in which the EFROM is irradiated with ultraviolet rays is shortened, the erased state can be reliably confirmed in the blank check process, and the optimum erase time can be easily set. Furthermore, since the erased state of the product is reliably inspected in the blank check process, there is no need to perform the blank check again in the sampling inspection performed after the blank check process, and the cost of the inspection process is reduced.

Effects of the Invention According to the present invention, when inspecting the storage state of data in each semiconductor memory element, the discrimination level output from the level switching means is switched from the first discrimination level to the second discrimination level, thereby improving the accuracy of level comparison. 6 Therefore, the data storage state of each semiconductor memory element can be accurately inspected, and undesirable situations such as a data read response time becoming longer due to an insufficient storage state can be avoided. It can be prevented. Further, since the means for inspecting the storage state of data in each memory element is built into the semiconductor memory device as a level switching means, the inspection process is simplified and the inspection cost is reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the EPROMI according to the present invention, FIG. 2 is a circuit diagram of the reference bit line voltage switching circuit 6, FIG. 3 is a circuit diagram of the bit line voltage setting circuit 3, and FIG. 4 is the input to the sense amplifier 5. 3 is a graph showing the characteristics of a detected signal. DESCRIPTION OF SYMBOLS 1... EPROM, 3... Bit line voltage setting circuit, 5... Sense amplifier, 6... Reference bit line voltage switching circuit, 9... Bit line voltage setting means, 10... Reference bit Line voltage switching means, 11... memory cell array, 13... reference cell

Claims (1)

[Scope of Claims] A plurality of semiconductor memory elements arranged in a matrix that store data depending on whether they are in an erased state in which charges are discharged or in an accumulated state in which charges at a predetermined level or higher are accumulated; A plurality of row addressing lines and column addressing lines for individually specifying each semiconductor memory element and from which a detection signal of a level corresponding to the presence or absence of charge accumulation is derived from the specified semiconductor memory element; provided on either the addressing line or the column addressing line, and commonly connected to a predetermined specific addressing line on the other of the row addressing line or the column addressing line, in the erased or accumulated state. a plurality of reference memory elements fixed to either one; a detection signal from the designated semiconductor memory element; and a reference detection signal from a reference memory element commonly connected to the designated semiconductor memory element. and a level comparing means for comparing the level of the semiconductor memory element with respect to the first discrimination level, and the specific addressing line includes a first discrimination level for determining the presence or absence of charge accumulation in the semiconductor memory element, and a level comparison means for comparing the level of the semiconductor memory element with respect to the first discrimination level. A testing device for a semiconductor memory device, characterized in that a level switching means is connected to switch and output a second discrimination level close to a level corresponding to a predetermined one of an erased state or an accumulated state.