JPH02211718A - Pll circuit - Google Patents

Abstract

PURPOSE:To always operate a circuit with an optimum loop band width by providing a loop filter with plural loop constant circuits different from one another and arbitrarily selecting them. CONSTITUTION:Analog switches 101 to 104 are connected to first to fourth resistors 61 to 64 and are connected to an operational amplifier 5, and analog switches 111 to 114 are connected to first to fourth resistors 71 to 74 and capacitors 81 to 84 and are connected to the operational amplifier 5. One of analog switches 101 to 104 and corresponding one of 111 to 114 are selectively and simultaneously turned on by a selector 13 operated by a controller 12. Since one loop constant circuit is selected to arbitrarily set the loop constant in this manner, the circuit is operated with an optimum loop band width independently of the change of frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PLL (phase control loop) circuit, and particularly to a PLL circuit that can be set to an optimal loop bandwidth in response to a plurality of different frequencies.

[Conventional technology]

Generally, in a digital satellite communication device, the purpose of the transmitting side is to absorb jitter in the transmitted data and clock, and the receiving side has the function of absorbing fluctuations in the reception timing of the received data and retiming to ideal timing using a reference clock. , a digital PLL circuit is used for each elastic buffer.

That is, as shown in FIG. 2, the phase of the input signal is compared in the phase comparator 1 with the phase of the voltage controlled oscillator 3 whose frequency has been divided by the frequency divider 4, and the phase comparison result signal is sent to the loop filter 2. The input signal and the variable oscillator are synchronized by feeding back to the voltage controlled oscillator 3 through the input signal and controlling it.

Further, as a circuit of the loop filter 2 in this type of digital PLL circuit, as shown in FIG.
．． Resistor 6. Resistor 7. An active filter composed of a capacitor 8 and a capacitor 8 is used.

[Problem to be solved by the invention]

By the way, in such a digital PLL circuit,
In order to reduce jitter due to external noise, it is necessary to narrow the loop bandwidth. On the other hand, in order to minimize temporary phase errors caused by internal noise of the variable oscillator and obtain good tracking characteristics, it is necessary to widen the loop bandwidth.

Therefore, this type of PLL circuit needs to be designed to have an optimum loop bandwidth depending on the conditions of use. Therefore, when it is necessary to switch and use several transmission rates in a digital satellite communication network, it is necessary to design a PLL circuit with optimal characteristics for all the transmission rates to be used. The problem is that it is extremely difficult to design such a circuit.

The present invention is a PLL that can operate at an optimal loop bandwidth even when the frequency is changed depending on usage conditions.
The purpose is to provide circuits.

[Means to solve the problem]

In the PLL circuit of the present invention, a plurality of different loop constant circuits are provided in a loop filter that feeds back a result of phase comparison between an input signal and a variable oscillator to the variable oscillator, and a selector operates these loop constant circuits based on a signal from a control device. It is configured so that it can be selected by

[Effect]

In the above configuration, by selecting one of the loop constant circuits, the loop constant can be arbitrarily set, and the PLL circuit can be set to the optimum loop bandwidth regardless of changes in frequency.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

First, the characteristics of the digital PLL circuit of the present invention will be considered. When the circuit shown in FIG. 3 is adopted as a loop filter that determines the loop bandwidth of the digital PLL circuit, the loop bandwidth BL is expressed by the following equation.

BL=ω7/2(ζ+1/4ζ)...(1) Here,
ω7 is the natural frequency, and ω is the damping coefficient.

The damping coefficient ζ is the first time constant τ of the active filter,
Using , it can be expressed as ζ=τz/2ω0 (2).

Using equation (2), equation (1) can be rewritten as follows.

BL = ω11 /2 (rz/2 ω, +1/4(
rz/2 ω,, ))=τ, ω11 ”/4 +1/
4τg・” (3) The natural frequency ω7 can be expressed as ω.=(K/τ ) I/2 (4) using the second time constant τ1 of the active filter. Here, K is It is the total gain of the digital PLL circuit,
When the conversion gain of the phase comparator is Ka, the voltage gain of the loop filter is KA, and the conversion gain of the voltage controlled oscillator is Kv, it can be expressed as K=, KA -, (5).

Equation (3) can be rewritten as follows using equation (4).

= 1/4 (τ2/τl K+1/τt) (6) The first time constant τ2 and the second time constant τ1 of the active filter are the resistance values of the resistor 6 and the resistor 7, respectively, R+
, and the capacitance of the Rz capacitor 8 is C, then τz=cRt...(7) τr=CR+...(8) Therefore, equation (6) can be rewritten as follows.

BL =1/4 (R2/R1・K+1/CRZ)
(9) Therefore, as can be seen from equation (9), BL in the loop band is determined by the resistance values R+ and R1 of the resistors 6 and 7 that constitute the loop filter, and the capacitance value C of the capacitor 8. .

From the above, if only R+, Rz and C that constitute the loop filter are changed by some means,
One digital PLL circuit provides the optimum loop bandwidth for all desired transmission rates in a digital satellite communication network.

FIG. 1 is a block diagram of an embodiment of the present invention based on the above consideration. In the figure, l is a phase comparator, 2 is a loop filter, 3 is a voltage controlled oscillator, and 4 is a frequency divider. The loop filter 2 is configured so that a plurality of types, here four types, of resistance-capacitance circuits can be selected and connected to one operational amplifier 5.

That is, the analog switches 101 to 104 are connected to the first to fourth resistors 61 to 64, respectively, and connected to the operational amplifier 5, and the first to fourth resistors 7. ~7. and capacitor8. -84 respectively analog switches 111-1
14 is connected to the operational amplifier 5. and,
The analog switch 10. ~104. I1. ~114
are the selectors 13 operated by the control device 12, respectively.
Accordingly, any one of the first to fourth elements is selectively and simultaneously turned on.

Note that the control device 12 is configured to be able to also control the frequency division ratio of the frequency divider 4.

According to this configuration, the first analog switch 10.
．． 11. resistor 6I, resistor 7. .

Capacitor 8. Let us consider the case where .

Control device 12 transmits control information to selector 13 . The selector 13 selects the analog switch 10. based on the transmitted control information. and 111 are turned on. At this time, analog switches 10z to 104 and analog switches 11□ to 11. is turned off, and constants that are not needed are not selected.

Analog switch 10. and 11. When resistor 61. is turned on, resistor 61. Resistor 7. and capacitor8. is connected to the operational amplifier 5 and incorporated into the loop filter circuit, and the loop filter operates with the optimum loop constant, and the PL
The L circuit is operated with a loop bandwidth suitable for the operating frequency.

Note that the control device 12 not only transmits information on opening and closing of the analog switch, but also transmits information to the frequency divider 4 to select the optimum frequency division ratio.

When the transmission rate changes, the control device 12 changes the selector 1 so that the optimum constant is obtained at that transmission rate.
3 selects the corresponding analog switch, incorporates the corresponding resistor and capacitor into the loop filter circuit, and sets different loop constants depending on the different resistance and capacitance values.

This series of operations allows the digital PLL circuit to operate at an optimal loop bandwidth despite changes in operating frequency.

Here, although the above embodiment shows an example in which four types of loop constants are selected, it goes without saying that even more loop constants can be selected by adding the number of circuits consisting of resistors, capacitors, and analog switches. .

〔Effect of the invention〕

As explained above, according to the present invention, the loop filter is provided with a plurality of different loop constant circuits and is configured to be able to arbitrarily select these circuits, so that the operating frequency can be changed as the PLL circuit is used. It is possible to realize a PLL circuit that always operates at the optimum loop bandwidth even when the loop bandwidth is changed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the PLL circuit of the present invention, and FIG.
The figure is a configuration diagram of a digital PLL circuit targeted by the present invention.
FIG. 3 is a circuit diagram of a loop filter used in the PLL circuit of FIG. 1. 1... Phase comparator, 2... Loop filter, 3...
- Voltage controlled oscillator, 4... Frequency divider, 5... Operational amplifier, 6.6. ~64...Resistance, 7,71~74...
Resistor, 88, ~84... Capacitor, 101~io. 11, ~1・14...analog switch, 12...
Control device, 13... selector.

Claims (1)

[Claims] 1. In a PLL circuit that compares the phase of an input signal and a variable oscillator and controls the frequency of the variable oscillator by feeding back the phase comparison result to the variable oscillator through a loop filter, the loop filter has a plurality of different loop constants. 1. A PLL circuit comprising a circuit, and the loop constant circuit is configured to be selectable by a selector operating based on a signal from a control device.