JPH022116A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable impurities to be introduced uniformly over the entire side wall by impregnating an ion of atom constituting a substrate simultaneously with the impurities ion or alternately after forming a groove on the semiconductor substrate by anisotropy etching in manufacture of a trench capacitor. CONSTITUTION:When impregnating impurities ion on the surface of a substrate 1 within a groove 7 using the formed groove 7 after performing anisotropy reaction etching to an Si semiconductor substrate 1 with a laminated film 5 as a mask, an accelerated parallel high energy impurities ion beam and a silicon ion beam are allowed to incide alternately and repeatedly. First of all, the incided impurities ion mainly incide the side wall part of the groove 7 where part of it scatters into atomic nucleus within the silicon substrate 1, jumps out of the surface of the substrate 1, and is impregnated into other side wall part or bottom part again. Then, when silicon ion is allowed to side from the same direction, silicon within the silicon substrate begins to move and several ions begin to jump out of the surface on the side wall part so that the impurities ion struck into the inside of the surface jumps out of the surface simultaneously to be impregnated into other side wall part or bottom part again.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Employee Use) The present invention relates to a method of manufacturing a semiconductor device, such as a trench capacitor for a memory cell.

(Prior Art) In recent years, LSIs in which submicron-sized elements are mounted at high density have been developed. In such LSIs, the area of each element such as the huge number of transistors and capacitors mounted on it is reduced.

For example, in the case of capacitors, the trench capacitor technology that uses the semiconductor substrate three-dimensionally has been proposed and put into practical use in devices. Trench capacitor technology IU is used to create trenches (J) several μm deep with approximately straight side pipes in one semiconductor board using an anisotropic reactive etching mask, and to remove the sidewalls (
This is a technique for forming a capacitor to obtain a required thick fcgll.

In this case, a trench capacitor (well, Mizoriguki 1111
Since the wall is 41ffi on one side, 1 usually that 1111I
A highly impurity r'71J layer is formed on the entire surface. Figure 2 (Well, such a hand conductor is played (9) A pot is formed (10)
5 shows how to introduce impurities into the tilH&
High-energy ions (11) are directed diagonally upward into the groove (
10) A method of injecting the inside of the tank is adopted. The ion beam (11) sped up by 7J is placed in the + line at the ft! #(1
0), and injection into the side wall portion of a groove (10) formed perpendicularly to the grain is performed.

The high-energy cations incident on the side wall part are in the one-handed conductor and are changed in wave number while repeating nuclear scattering and quadruplets scattering, and finally come to rest at r&. However, when ions are incident at a large angle of incidence on a side wall formed approximately perpendicular to the ribs, ions are scattered by the atomic nucleus from the side wall, as shown in the analytical surface diagram in Figure 3. is subjected to wide-angle scattering, and a part of the incident ions (lla) jumps out of the measurement layer and re-enters the bottom of Itou (10)')) and the opposite 1i1i part of B111 facing the other side. The wave number will be changed.

(Problem to be solved by the invention!A) From the conventional 5 methods (Anisotropic reaction etching)
For example, when forming a trench capacitor, if an ion beam is introduced into the trench from diagonally above at a large angle of incidence to introduce impurities into the sidewalls, the atomic nuclei will form. The scattered ions undergo wide-angle scattering, so they are distributed uniformly and unevenly across the sidewall.
It's difficult to get 5 people to do N things.

It has been difficult to manufacture high-performance trench capacitors and the like.

The present invention has been made based on the above circumstances, and provides a method for fabricating a semiconductor device that makes it easy to uniformly introduce impurities into the entire sidewall, thereby making it possible to fabricate high-performance trench capacitors, etc. The purpose is to

[Structure of the invention]

(Hands to Solve the Problems!) In order to solve the above problems, the present invention includes a step of forming an etching mask having a required opening on the main surface of a semiconductor substrate, and a step of forming an etching mask from the opening of the mask to Anisotropic etching is performed in a direction perpendicular to the main surface of the semiconductor substrate to form the etching surface 4.
Step 5: Then, desired impurity ions and ions of atoms constituting the semiconductor substrate are simultaneously or alternately added.
f4'J) It is safe to skip the step of injecting from the top.

(Function) By implanting ions of atoms constituting the semiconductor substrate simultaneously or alternately with impurity ions, the inside of the trench 11t! I
Sputtering of the wall portion is promoted, and not only the atoms constituting the substrate, but also the stationary ions are knocked out from the layer surface and reinjected into the surface. This re-implantation realizes a uniform ratio of the impurity concentration within the trench.

(Continued) A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS.

First, as shown in Fig. 1 1bl, the main surface of the conductor (1) was heated with hot acid for about 1000 A (7
The first silicon oxide film (2) of J iQ size is formed.
Silicon chamber ratio of OA thickness (3) and 6000 A
')) thick second silicon oxide film (4) by CVD;
From this: +lF': Next deposited, silicon oxide 1 (2
), a silicon nitride film (3), and a silicon oxide film (4) are formed on the resist film (5).
) to an appropriate thickness. The atl pattern (5) serves as an etching mask for the p bale for etching the substrate (1).

Next, as shown in FIG. 11bl, an opening of 1 μm 1 Tl is formed in the resist film (6) by a photolithography method, and using the resist film 16) having this opening as a mask, a first step is performed by diagonal anti-16 etching. 2. Open the silicone acid pattern (4). After removing the resist film (6), the second σ) silicon acid rts @ +
Using 41 as a mask, the silicon nitride film (3) and the first silicon oxide layer (2) are sequentially opened by etching to form an etching mask consisting of a square pattern (5) having an opening (5a).

Next, apply the mask (5).

Anisotropic reaction etching in the direction perpendicular to the main surface of Si 1,000 degrees is applied to the main surface of Si (1) to form a vertical etching region (7) with a depth of about 3 μm. do.

Using a(7) thus formed, the groove (7) is
11) Fabricating a trench capacitor with impurity ions implanted into the plane of Silicon ion beams with extremely high energy are alternately injected here.

First, the incident impurity ions are mainly incident on the side walls of the groove (7). A part of this force is scattered by the atomic nuclei in the silicon substrate (1) and ejects from the surface of Gokari (1), causing b
The outside of the side wall and the bottom part are press-fitted again. However, most of the impurity ions remain stationary inside the side tube portion into which they are incident.

Therefore, firstly, silicon ions are tilted many times from the same direction.
This is incident. The injected silicon ions scatter with the atomic nuclei within the silicon hydroxide, giving them energy. Therefore, due to the energy of Silicon Store Temporary Silicon I and Mako, we begin to recommend J1. Some of these ions fly out from the surface of the side rock, so they retreat by implanting caged silicon ions. At the same time, impurity ions/ions implanted inside the immersion surface also fly out from the surface and are re-injected into the side walls and bottom of the pond. In this way, by repeating the implantation of impurity ions and silicon ions, i
Impurity ions are implanted even into the parts where the impurity ions are not incident, so that the desired force of impurity is uniformly introduced throughout the side podium σ), and the high performance trench capacitor can be restored.

Note that the vertical etching region consisting of a groove or the like that can uniformly introduce impurities into the inner wall is useful not only for trench capacitors but also for the process of performing ion injection into the sidewall of the groove.
J O) This is also used in the manufacturing of semiconductor devices.

〔Effect of the invention〕

As explained above, according to the present invention, impurity ions and silicon ions are alternately mixed, so that impurities are uniformly introduced into the trench groove.

There is an advantage that a high performance D trench capacitor can be manufactured exclusively.

4. Explanation of drawing V @ Figure 1 is a process cross-sectional diagram showing how to attach the top of a semiconductor device according to this invention. Figure 3 is a diagram used to explain the trajectory of ions ejected from the side ribs after being scattered at a wide angle.

1...Si#-conductor ratio, 5...Silicon acid ratio @/
Etching mask consisting of a silicon nitride ratio pattern/silicon oxide film with a product of 1 m@, 6... Resist pattern, 7... Groove, 8
...Ion beam.

Claims (1)

[Claims] forming an etching mask having a required opening on the main surface of the semiconductor substrate; performing anisotropic etching from the opening of the mask in a direction perpendicular to the main surface of the semiconductor substrate to form a groove in the substrate; A method for manufacturing a semiconductor device, comprising a step of forming a semiconductor substrate, and a step of simultaneously or alternately press-fitting a predetermined number of impurity ions and ions of atoms constituting the semiconductor substrate from above the groove.