JPH02210997A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To provide lots of functions to a memory system and to make the scale of a signal processing circuit small by combining 2-system of frame memories and a switching circuit for each channel. CONSTITUTION:A switching circuit and a frame memory are combined to recording and reproducing systems 20, 80 respectively. Thus, a video signal is divided to each channel at recording to apply channel division and a luminance signal and a color signal are written in the same memory or read out succeedingly to realize time division multiplex. The write to the memory is implemented in a form of time division multiplex at reproduction and the readout from the memory is implemented by using a switching circuit to apply channel synthesis and decoding of a luminance signal and a color signal, and the write to the memory is implemented by using a clock having a time base error and the readout is implemented by using a clock without time base error.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a magnetic recording/reproducing device, and in particular to a magnetic recording/reproducing device that time-division multiplexes signals with different bands, such as a luminance signal and nine color signals, and records the signals by dividing the channels. The present invention relates to a recording/reproducing device.

[Conventional technology]

Conventionally, there have been examples, such as the video signal recording and reproducing apparatus described in Japanese Patent Application Laid-Open No. 62-252281, in which a frame memory is used to compress and record video signals, and time expansion is performed during playback. , no consideration is given to channel division or time-division multiplexing of luminance signals and color signals.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into consideration the fact that after signal processing is performed separately for luminance signals and color signals, time-division multiplexing is performed, and further channel division is performed for recording and reproducing. was there.

An object of the present invention is to realize the above-mentioned recording/reproducing signal processing in a small-scale circuit in a magnetic recording/reproducing device that processes signals separately into luminance signals and color signals, performs time division multiplexing, and further divides channels for recording/reproducing. The purpose is to provide a circuit configuration.

[Means to solve the problem]

The above objective is achieved as follows. record.

Also during reproduction, this is achieved by providing two systems of frame memories for each channel and combining the above memories with appropriate switching circuits.

[Effect]

By combining the above switching circuit and frame memory,
During recording, the video signal is distributed to each channel for channel division, and the luminance and two-color signals are written in the same memory, and read out successively to achieve time-division multiplexing. During playback, time-division multiplexing is achieved. Channel synthesis is performed by writing to memory in the same format, reading it, and using a switching circuit.

In addition to restoring the luminance signal and two-color signal, the time axis error is also corrected at the same time by writing to the memory using a clock that has a time axis error during playback, and reading out using a stable clock that does not have a time axis error. This allows the same memory to have various functions, making it possible to realize a tJX scale circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows an example of a magnetic recording and reproducing apparatus for recording and reproducing high-definition television signals (hereinafter abbreviated as HDTV signals) as shown in FIG. , 2.3 are red (R), which are the three primary color signals of the HDTV signal.

Green (G), Blue (B) (7) Input terminal, 4 is input terminal for composite synchronization signal of HDTV signal, 10 is three primary color signal R2G
, B as a luminance signal Y and two color signals P l + P 11
20 is a recording system signal processing circuit, 30.31 is an FM modulation circuit, and 40.41 is a recording amplifier.

50 is a cylinder, and 51.51' and 52.52' are magnetic heads.

53 is a magnetic tape, 60.61 is a reproduction amplifier, 70.7
1 is an FM demodulation circuit, 80 is a reproduction system signal processing circuit, 90 is a luminance signal Y and two color signals PB, and Pa is a three primary color signal R.
, G, H inverse matrix circuit, 101゜102
, 103 are output terminals for the three primary color signals R, G, and H, respectively;
104 is an output terminal for a composite synchronization signal of the HDTV signal.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

The HDVT signal is supplied to input terminals 1, 2.3 in the form of three primary color signals R, G, and B, respectively. Further, a composite synchronization signal of the HDTV signal is inputted from the input terminal 4. Next, the three primary color signals R, G, and B are converted by the matrix circuit 10 into a luminance signal Y and two color signals P11°PR, and sent to the recording system signal processing circuit 20. A recording signal processing circuit 20 generates a recording signal according to a predetermined format. The above format will be described in detail later with reference to FIG. 3, and the configuration and operation of the recording system signal processing circuit 20 with reference to FIGS. 4 and 5. Basically, the input signal is time-compressed or expanded, and the synchronization information two-color signal and R-degree signal are time-division multiplexed to generate a two-channel recording signal. After that, the 2-channel recording signal is transferred to the FM modulation circuit 30.31.
The signals are FM-modulated by , and supplied to magnetic heads 51 and 52 (51' and 52') via recording amplifiers 40 and 41. The magnetic heads are arranged in two sets (51
and 51', 52 and 52'), a total of four cylinders 50
mounted on. In order to widen the band of the tape head system, in this embodiment, the cylinder 50 is
The relative speed of the head is increased by rotating it at 5.40 rpm, which is twice as fast. The magnetic tape 53 is wound around the cylinder 50 by more than 180 degrees, and the recorded signals divided into the two channels are sequentially magnetically processed by magnetic heads 50, 51 (so', si') for each channel. It is recorded on tape 53. As mentioned above,
Since the cylinder 50 is rotated at 5.40 rpm, one field signal requires three head scans and two more.
Because of the channel division, data is recorded over six tracks on the tape (two-channel division, three-segment recording).

Next, during reproduction, the magnetic heads 51, 52 (51'
The two-channel reproduction signal reproduced by the FM demodulation circuit 70,
The signal is inputted to 71, subjected to FM demodulation, and then sent to a reproduction system signal processing circuit 80. The reproduction system signal processing circuit 80 performs processing opposite to that during recording, and reproduces the original luminance signal Y and two color signals PR,
Output Pa. The configuration and operation of the reproduction signal processing circuit 80 will be described in detail later with reference to FIGS. 7 and 8. Basically, the playback signal is time-compressed or time-expanded, synchronization information added during recording is removed, channels are combined, and time axis errors in the playback signal are corrected to restore the original signal shape. ing. Then, the luminance signal Y and the two color signals Pm and Ps* are converted into the HDTV signal (7) E primary color signals R, G, and B by the inverse matrix circuit 90, and are outputted from the output terminals 101, 102, and 103, respectively. Ru.

Next, an example of the recording signal format of this embodiment will be explained using FIG. In order to record a wideband signal as shown in Figure 2, it is divided into two channels, and redundant periods such as the vertical blanking period of the video signal are minimized to reduce the signal band per channel. There is. Generally, for the signal band of the luminance signal Y, the chrominance signal P R + P
Since the signal band of R is narrow, the luminance signal Y has an effective period τ of one horizontal scanning period of the original signal. (period shown in τ in Figure 3 (mountain)) - C (period shown in τ in Figure 3 (c), τ, >
τ. )τO times the time value, and the two color signals Pg and Pa are converted into a line-sequential color signal CLS in which Pn and Pn are transmitted alternately for each line.
After converting to , the validity period τ. - (the period shown in τ2 in Fig. 3(c), τ□〈τo) times the above-mentioned time-expanded luminance signal Y, and the period τm (τB in Fig. 3(C)). Synchronization information S for the period shown in
are time-division multiplexed to generate two-channel recording signals shown in FIGS. 3(C) and 3(d). The synchronization information S consists of a negative polarity synchronization signal and a time-base reference signal such as a burst signal to ensure synchronization separation during reproduction and to process the reproduced signal without time-base errors. Here, the luminance signal Y is time-expanded and the band is reduced to 1/(-L), and the color signal CLa is time-compressed and the band is reduced to 1/(-L). Of these, the higher one is, so in order to improve efficiency, both the luminance signal and the two color signals should have similar bands.

It is necessary to determine τ2.

FIG. 4 shows an example of the configuration of the recording system signal processing circuit 20 in FIG. 1. In FIG. 4, 200.
201 and 202 are a luminance signal Y and two color signals P, respectively.
g, Pa input terminals, 203 is a composite synchronization signal input terminal, 210.211.212.213.214 is a low pass filter (hereinafter abbreviated as LPF), 220.221°222 is an A/D converter, 230 , 231 are vertical filters that limit the vertical band; 232 are two color signals PI;
A line sequential conversion circuit converts FPR into a line sequential color signal CI,s, 240 and 241 are serial/parallel conversion circuits,
250° 251 is a timing adjustment circuit, 260 to 266
is a switching circuit, 270-273H:7 L/-A Me-1=IJ, 280.281 is a parallel-to-serial conversion circuit, 290.291 is a D/A converter, 292.29
3 is the northern terminal of the recording signal of 2 channels, 30
0 is a clock generation circuit, 310 is a servo control circuit, 31
1 is an output terminal for a servo reference signal, 320 is a write address generation circuit, 330 is a read address generation circuit, 340
is a synchronization information generation circuit.

Further, FIG. 5 is a signal waveform diagram showing the process of recording signal generation in the signal circuit of FIG. 4.

The operation of the recording system signal processing circuit 20 that generates the recording signal described above will be explained below with reference to FIGS. 4 and 5. The luminance signal Y and the two color signals Pl and PR input from the input terminals 200, 201, and 202 are L P F210.
．． The band is limited by 211 and 212. Generally, compared to the luminance signal Y, the color signals PI and PR are about 173 to
The band is 1/4, and LPF210 and L are adjusted accordingly.
The restricted bands of PF211 and PF212 are different.

Thereafter, the luminance signal Y and the two color signals Pa and Pn are converted into digital signals by A/D converters 220, 221, and 222, respectively. At this time, the clock generation circuit 300 generates a sampling clock synchronized with the composite synchronization signal inputted from the input terminal 203, that is, synchronized with the video signal.The luminance signal Y is the clock Sy, and the two color signals PR and PR are the clocks. Use Sc. After the vertical bands of the two color signals P and PR are limited by vertical filters 230 and 231, the line sequential conversion circuit 232 converts them into a line sequential color signal cbs in which pH and PR are transmitted alternately for each line. converted. The line sequential color signal Ct,s is
After the timing adjustment circuit 251 matches the timing with the luminance signal Y, the serial/parallel conversion circuit 241 converts the signal into a parallel signal. On the other hand, the luminance signal Y is converted into a parallel signal by a serial/parallel conversion circuit 240, and then subjected to timing adjustment by a timing adjustment circuit 250.

Here, timing adjustment will be explained.

As mentioned earlier, the luminance signal Y and the two color signals PBpPR have different signal bands, so the LPF210 and the LPF21
1.212 has a different limited band. For this reason, LPF210
Since a time lag occurs due to the difference in the delay time between L P Fall and L P Fall 212, the timing adjustment circuit adjusts the time lag between the luminance signal and the color signal. The timing adjustment circuit is composed of digital delay circuits such as shift registers and line memories. In addition, serial
Parallel conversion will be detailed later.

The luminance signal Y and line sequential color signal CLB that have undergone the above processing are input to switching circuits 260 and 261, respectively, and are switched line by line to produce one line as shown in FIGS. 5(Q) and (d). Each signal is converted into a two-channel signal that transmits a luminance signal Y and a line-sequential color signal CLs. Here, the recording system signal processing circuit has two frame memories for each channel.
System (frame memories 270 and 271, 272 and 273
), and writing and reading are performed alternately for each frame.

That is, while writing to the frame memory 270.272, data is read from the frame memory 271.273, and in the first frame, data is written to the frame memory 271.273 and read from the frame memory 270.272. The signals of the above two channels are appropriately switched by switching circuits 262 and 263 in units of one frame, and are sent to the frame memory 270.
．． 272 (or frame memories 271 and 273), and according to the write clock 2 write address and other control signals, the luminance signals Y,
Line sequential color signals CLs are written. The write clock is
Switch the clocks Sy and Sc synchronized with the video signal in synchronization with the switching circuits 260 and 261 (switching circuit 266)
, R-WCK-A as shown in FIGS. 5(8) and (f).

Generate B. Furthermore, the data is written onto the memory according to the write address output from the write address generation circuit 320.

On the other hand, time division multiplexing can be performed by reading out the color signal and the luminance signal successively during readout.

Here, the relationship between the read clocks R-RCK-A, B and the sampling clocks Sy, Sc of the luminance signal two-color signal is synchronized with R-RCK-A, B=-・Sy=τl B, and the read address is generated. The read address is generated by the circuit 330.

Figure 6 shows frame memory 270.272 (271,2
73) is a memory map showing an example of how to write the luminance signal Y and line sequential color signals Ct, s. Now, the valid period is one horizontal scanning period of the video signal. (period of τ shown in FIG. 3 (tL)), the number of samples of the color signal is nc (period of τ).

・Sc), and the number of luminance signals is 37 (τ.・Sy). The memory stores a time-division multiplexed luminance signal Y and a line-sequential color signal C.
Write Ls to a continuous area in memory. That is, C.L.
When the s signal is written by giving the write start address A0, the Y signal to be time-division multiplexed is the write start address Ao+7.
Give Z and c and write.

When reading from address 80 to address A, +7Lc+n
By sequentially reading up to y-1, the CLm signal and! Time-division multiplexing of mourning notes can be realized.

Here, signal processing using frame memory can be performed. For example, the rearranging process for each line within a field as described in Japanese Patent Application Laid-Open No. 61-39915 can be easily realized by controlling write addresses or read addresses.

The two-channel signals read out as described above are input to switching circuits 264 and 265, respectively.

The switching circuits 264 and 265 select the memory to be read, and also appropriately switch the synchronization information S output from the synchronization information generation circuit 340 and the read data.
1) Synchronization information S and color signal as shown in l (J),
A two-channel recording signal in which the W degree signal is time-division multiplexed is output. The two-channel recording signals generated in this way are processed by the parallel/serial converter circuits 280 and 281.
is converted into a serial signal.

Here, serial-to-parallel and parallel-to-serial conversion will be explained. Generally, the sampling clock frequency when converting an analog signal into a digital signal needs to be at least twice the band of the signal to be converted, according to the sampling theorem.

Therefore, in order to sample a wideband signal as shown in FIG.
Since it is about 4, the sampling clock Sc is 10 to 20M.
) become Iz. If the operating speed of the digital element can support the above clock rate, serial/parallel converter circuit 240.241, parallel/serial converter circuit 2
80.281 is not necessary. However, if this is not the case, it is necessary to perform phase division and parallel processing. At that time, the number of phase divisions is determined by the element with the slowest operation speed, but when processing is performed using one memory as in this system, the phase division must be performed according to the fastest signal. If a luminance signal cannot be written to a frame memory without dividing it into four phases, for example, a color signal must be written into a frame memory by dividing it into four phases, even if it is okay without phase division. should not. However, phase division increases the circuit scale due to parallel processing. Therefore, by phase division, the color signal is
By performing A/D conversion, vertical filtering, line-sequential conversion, and timing adjustment, only the minimum necessary portions are processed in parallel, and the increase in the scale of one circuit can be minimized.

After being removed, unnecessary components are removed by LPFs 213 and 214, and the signals are output from output terminals 292 and 293, respectively. Further, the servo control circuit 310 generates a servo reference signal synchronized with the input composite synchronization signal, that is, synchronized with the video signal, and outputs it from the output terminal 311.
The cylinder 50 is servo controlled.

Next, reproduction-related signal processing will be explained. In reproduction-related signal processing, signal processing opposite to that during recording is performed in order to convert to the original HDTV signal. That is, if rearranged, the original order is restored, the synchronization information S added at the time of recording is removed, the luminance signal Y is time-compressed, and the line-sequential color signal CL! expands the time and further combines the channels. It is also necessary to correct the time axis error (jitter) of the reproduced signal.

FIG. 7 shows a configuration example of the reproduction system signal processing circuit 80 in FIG. 1, where 400 and 401 are input terminals for two-channel reproduction signals, and 410 and 411 are LPFs.

420 and 421 are A/D converters, 430 and 431 are serial/parallel conversion circuits, 440 to 446 are switching circuits, 450 to 453 are frame memories, 460 and 461 are timing adjustment circuits, and 470 and 471 are parallel to serial conversion circuits. circuit.

480 is the color signal interpolation circuit A90.491.492 is D
/A converter, 500.501.502 is LPF, 510
．． 511 and 512 are output terminals for the luminance signal Y and two color signals PB and Pg, respectively, 520 and 521 are synchronization separation circuits, 530 and 531 are clock generation circuits, 540 are write address generation circuits, 550 are reference clock generation circuits, 5
60 is a servo control circuit, 561 is a servo reference signal output terminal, 570 is a read address generation circuit, 580 is a synchronization signal generation circuit, and 581 is a composite synchronization signal output terminal. Further, FIG. 8 is a signal waveform diagram showing a signal processing process in the signal processing circuit of FIG. 7.

The operation of the reproduction system signal processing circuit 80 that implements the reproduction signal processing described above will be described below with reference to FIGS. 7 and 8. The two-channel reproduction signal input from the input terminal 400.401 is band-limited by the LPF 410.411, and then supplied to the A/D converter 420.421 and the synchronization separation circuit 520.521. Synchronous separation circuit 520, 5
At step 21, the synchronization information S added during recording is separated and sent to clock generation circuits 530 and 531, respectively. The clock generation circuits 530 and 531 generate clocks that are phase-synchronized with the burst signal in the separated synchronization information, that is, clocks that are synchronized with the jitter of the reproduced signal, and generate clocks that are synchronized with the jitter of the reproduced signal.
Converter 420, 421 and write address generation circuit 5
Send to 40. After converting the analog signal into a digital signal using a clock synchronized with the jitter of the reproduced signal, the signal is inputted to switching circuits 440 and 441 via serial/parallel conversion circuits 430 and 431. The reproduction system signal processing circuit has two frame-memory systems for each channel, and writes and reads alternately for each frame.

The memory to be written is selected by the switching circuits 440 and 441, and the clock P-WCK-A is synchronized with the write address and the jitter of the above-mentioned reproduction signal.

Data is written to the memory according to B (FIG. 8(Q),(d)). Here, frame memory 450°451
．． Write data to 452 and 453 as follows.

Figure 6 shows frame memory 450.451.452.4
In the reproduced signal showing the memory map No. 53, only the effective video portion excluding the synchronization information portion is written into the memory in the form in which the luminance signal and color signal are time-division multiplexed.

The write start address must be reset every l line.

That is, in FIG. 6, after one line of data is written at write start address A, the next line is written by setting write start address A. Thereby, error propagation due to dropouts and the like during playback can be minimized.

When reading, for example, in the case of the line with write address A0, if it is a color signal, it is from address A, to address A, +71
/c-1, address A for luminance signal. Address A from +7Lc. + Le. All you have to do is read up to +9 C1. Further, by address control of the write address generation circuit 540.1 and the successive address generation circuit 570, signals can be easily rearranged. In addition, when reading, from the reference clock generation circuit 550 such as a crystal oscillator,
By using a stable clock with no time axis error, jitter in the reproduced signal can be removed, and since the synchronization information S is not written to the memory, the synchronization information can also be removed.

By using the clock Sc when reading out the color signal and the clock Sy when reading out the yR multiplied signal, time compression and expansion can be performed and the original time axis can be restored. Here, the eighth
As shown in Figures (g) and (h), switching is achieved by reading out line-sequential color signals and m-degree signals for each channel alternately, line by line, and with a phase difference of one line between channels. By simply switching the circuits 444 and 445 for each line, one channel of luminance signal Y (
(Fig. 8 (j)), line sequential color signal Ct, (Fig. 8 (i)
) can be obtained. Therefore, read clock P-RC
K・A, B are also read clocks (FIG. 8(e) , (f)).

Since the luminance signal Y read out in the above manner has a high sampling clock rate, the timing is adjusted by the timing adjustment circuit 460 while the luminance signal Y remains phase-divided.
9 On the other hand, since the sampling clock rate of the color signal is not as high as that of the luminance signal, it is first converted into a serial signal by the parallel/serial conversion circuit 481, and then the necessary signal processing is performed. be exposed. Therefore, timing adjustment circuit 461. The interpolation circuits 480 are only needed for one system each, and are not required for the number of phase divisions, so an increase in circuit scale can be prevented. As mentioned above, if the digital element is fast enough, the serial/parallel conversion port @430°431,
Parallel/serial conversion circuits 470, 471 are not required.

The timing adjustment circuits 460 and 461 are mainly LPF50.
0 and L P F2O3,502 fli! This corrects the delay time difference due to the continuous band of the I-limited band, and can prevent color shift due to the delay time difference. This timing adjustment circuit is composed of digital delay elements such as shift registers and line memories.

Since the line-sequential color signals Ct, a have been subjected to line-sequential processing during recording, necessary interpolation processing is performed at interpolation port #1480 to restore the two color signals PB, PR.

The luminance signal Y and the two color signals P m + P R obtained as described above are each converted into analog signals by the D/A converter 490.491°492, and then
Unnecessary components are removed by L P F2O3, 501, 502, and output from output terminals 510, 511, 512. Further, a composite synchronization signal is generated from the synchronization signal generation circuit 580 and outputted from the output terminal 581. Further, servo control during reproduction is performed by a servo control circuit 560, and a servo reference signal is output from an output terminal 561 to control the cylinder 50.

By combining and controlling an appropriate switching circuit and frame memory in the manner described above, it is possible to remove the time axis error of the reproduced signal using the same memory.

Synchronization information, separation of luminance signal and two color signals, signal time expansion,
It becomes possible to perform compression and signal rearrangement.

In this embodiment, the recording system and the reproducing system have separate frame memories, but since the required memory capacity is the same, it is possible to share the memory capacity.

Further, in this embodiment, 2-channel divided 3-segment recording has been described, but in general, N-channel division (N is an integer greater than or equal to 2) and M segments (M is ]).

The above method can also be applied to recordings of integers greater than or equal to the above.

Since this system is equipped with frame memory, VT
Another advantage is that special playback of R, such as freezing the screen, can be easily achieved by stopping writing to the memory and only reading it.

〔Effect of the invention〕

As explained above, according to the present invention, channels can be divided by combining two systems of frame memories and a switching circuit for each channel.

The memory system can be equipped with many functions such as synthesis, time-division multiplexing and separation of luminance and color signals, rearrangement in frame (field) units, and correction of time axis errors in the reproduction signal in the reproduction system. It is possible to downsize the signal processing circuit.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a diagram explaining a high-definition television system, Figure 3 is a diagram explaining a recording signal format, and Figure 4 is a diagram of a recording system signal processing circuit. FIG. 2 is a block diagram showing an example of a configuration. 5 and 8 are diagrams explaining the operation of the embodiment shown in FIG. 1, FIG. 6 is a diagram showing a memory map showing an example of writing to memory, and FIG. 7 is a configuration example of a reproduction system signal processing circuit. FIG. 1.2, 3.4... Input terminal, 101, 102.103.104... Output terminal, 20
... Recording system signal processing circuit, 80 ... Reproduction system signal processing circuit, 220, 221.222.420.421 ... A/D
Converter, 290, 291.490.491.492...
・D/A converter, 260.261, 262, 263, 2
64,265,266.440...446...Switching circuit, 270, 271.272.273.450.451.4
52.453・Frame memory. 300, 530.531...clock generation circuit, 55
0... Reference clock generation circuit, 320, 540... R-inclusive address generation circuit, 330,
570...Reading 71~Response generation circuit. View Z Figure 1 Flash Atsushi Figure

Claims (1)

[Claims] 1. The luminance signal and chrominance signal of the video signal are multiplexed in a time-division manner, and a rotary head divides one field of signals into N channels (N is an integer of 2 or more) and M channels (M is a positive number). In a magnetic recording/reproducing device that divides the video signal into segments (an integer of
a clock generation circuit (300), and an A/D converter (220) that converts the luminance signal into a digital signal using a first sampling clock of a predetermined frequency generated from the first clock generation circuit (300); An A/D converter (
221, 222), and a switching circuit (221, 222) that can perform switching in arbitrary units.
60, 261, 262, 263, 264, 265, 26
6), two systems of frame memories (270, 271, 272, 273) for each channel, and writing in synchronization with the first and second sampling clocks generated from the first clock generation circuit (300). A circuit (320) that generates an address, and a third clock of a predetermined frequency generated from the first clock generation circuit (300).
A circuit that generates a read address synchronized with the clock of
330), and a D/A converter (290, 2) that converts a digital signal into an analog signal using the third clock.
91) and the same frame memory (270, 271, 272, 27
3) writing the luminance signal and the color signal, the luminance signal being synchronized with the first sampling clock and the color signal being synchronized with the second sampling clock;
The luminance signal and the chrominance signal are time-division multiplexed by reading out the luminance signal and the chrominance signal continuously according to a predetermined format in synchronization with the third clock, and the luminance signal and the chrominance signal are time-division multiplexed, and then converted into the predetermined format by write and read address control. 1. A magnetic recording/reproducing device characterized in that it is configured to perform recording by performing rearrangement according to the following. 2. Frame memory for each channel (270, 2
71, 272, 273) have a configuration in which time-division multiplexed color signals and luminance signals are written in consecutive areas on the same memory, and the color signals and luminance signals are read out successively. A magnetic recording/reproducing device according to claim 1. 3. Frame memory for each channel (270, 2
71, 272, 273), the switching circuits (260, 261) are switched line by line, and a signal in which a luminance signal and a color signal are alternated line by line is written. Item 1. The magnetic recording and reproducing device according to item 1. 4. A circuit (520, 521) that separates the synchronization information from the reproduced signal for each channel, and a circuit (52) that separates the synchronization information for each channel.
a circuit (530, 531) that generates a third clock synchronized with synchronization information output from
A/D converters (420, 421) that perform sampling using the third clock output from 1), and switching circuits (440, 441, 442, 4
43, 444, 445, 446), two systems of frame memory (450, 451, 452, 453) for each channel, and a clock generation circuit (530, 53) for each channel.
A circuit (540) that generates a write address synchronized with the third clock output from 1), and a reference clock generation circuit (550) that outputs stable first and second sampling clocks without time axis errors. , a circuit (570) that generates a read address in synchronization with the first and second sampling clocks output from the reference clock generation circuit (550), and converts the digital signal into an analog signal using the first sampling clock. a first D/A converter (490) for converting a digital signal into an analog signal; and a second D/A converter (491) for converting a digital signal into an analog signal using the second sampling clock.
, 492), and the reproduced signal is a form in which the luminance signal and the color signal are time-division multiplexed, and is stored in the frame memory (450) in synchronization with a third clock having the same time axis error as the reproduced signal. , 451, 452,
453) and when read out, the time axis error is corrected using stable first and second sampling clocks with no time axis error, and the luminance signal and the color signal are 2. The magnetic recording/reproducing apparatus according to claim 1, further comprising a configuration for restoring the original signal by restoring the original signal to the time length of 1 and then rearranging the signals in the opposite manner to that during recording by controlling write and read addresses. 5. The above frame memory (450, 451, 452, 4
The circuit (540) that generates the write address of 53) is
5. The magnetic recording and reproducing apparatus according to claim 4, wherein a write start address is always set for each line of the reproduced signal, and the color signal and the luminance signal are written into the memory while being time-division multiplexed. 6. The circuit (570) that generates the read address is:
The luminance signal is read out using the first clock, and the chrominance signal is read out using the second clock, so that the luminance signal and the chrominance signal appear alternately for each line of the original signal. In addition, there is a phase difference of one line between the channels, and the switching circuits (444, 44
5. The magnetic recording and reproducing apparatus according to claim 4, wherein the magnetic recording and reproducing apparatus has a configuration in which the luminance signal and color signal of one channel are obtained by switching 5) on a line-by-line basis.