JPH0221041B2 - - Google Patents

Info

Publication number
JPH0221041B2
JPH0221041B2 JP55118790A JP11879080A JPH0221041B2 JP H0221041 B2 JPH0221041 B2 JP H0221041B2 JP 55118790 A JP55118790 A JP 55118790A JP 11879080 A JP11879080 A JP 11879080A JP H0221041 B2 JPH0221041 B2 JP H0221041B2
Authority
JP
Japan
Prior art keywords
oscillator
detector
output
transistor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP55118790A
Other languages
Japanese (ja)
Other versions
JPS5744206A (en
Inventor
Tatsumi Sumi
Shiro Mizutani
Yukihiko Myamoto
Atsushi Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11879080A priority Critical patent/JPS5744206A/en
Publication of JPS5744206A publication Critical patent/JPS5744206A/en
Publication of JPH0221041B2 publication Critical patent/JPH0221041B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/24Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing noise

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)

Description

【発明の詳細な説明】 本発明は放送受信機の音声信号と録音レベル校
正用発振器の出力信号とを選択する出力回路に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output circuit that selects an audio signal from a broadcast receiver and an output signal from an oscillator for calibrating a recording level.

放送を磁気録音機に録音する場合の録音レベル
設定のために放送受信機たとえばFMチユーナに
録音レベル校正用発振器を内蔵したものがある。
このようなFMチユーナにおいて、音声信号と録
音レベル校正用発振器(以下、単に発振器と記
す)の出力信号との出力選択回路は従来、第1図
に示す如く構成されていた。
Some broadcast receivers, such as FM tuners, have a built-in oscillator for calibrating the recording level in order to set the recording level when recording broadcasts on a magnetic recorder.
In such an FM tuner, an output selection circuit for selecting an audio signal and an output signal of a recording level calibrating oscillator (hereinafter simply referred to as an oscillator) has conventionally been constructed as shown in FIG.

しかるに従来の方法ではFM検波器1からの音
声信号と、発振器2からの出力信号とを切替スイ
ツチ3で選択していた。そこでFM検波器1から
の音声信号と発振器2からの出力信号を選択して
共通端子4から取り出すためには2接点のスイツ
チが必要であり、FM検波器1の動作点と、発振
器2の動作点とが異なる場合にはスイツチ3を切
替えたときにシヨツク音を生じる欠点があつた。
However, in the conventional method, the audio signal from the FM detector 1 and the output signal from the oscillator 2 were selected by the changeover switch 3. Therefore, in order to select the audio signal from the FM detector 1 and the output signal from the oscillator 2 and take them out from the common terminal 4, a switch with two contacts is required. If the points are different from each other, there is a drawback that a shock sound is produced when the switch 3 is switched.

また、発振器2の信号がFM検波器1側に混入
するときは、第1図に示すごとく発振器2の動作
を停止させるためのスイツチ5が更に必要となる
欠点もあつた。
Another disadvantage is that when the signal from the oscillator 2 enters the FM detector 1 side, a switch 5 is additionally required to stop the operation of the oscillator 2, as shown in FIG.

本発明は上記にかんがみなされたもので、上記
の欠点を解消した出力選択回路を提供することを
目的とするものである。
The present invention has been made in view of the above, and it is an object of the present invention to provide an output selection circuit that eliminates the above-mentioned drawbacks.

この目的は、本発明によれば検波器の負荷抵抗
と発振器の負荷抵抗とを共通にして出力端子を共
通にし、出力選択スイツチにより非選択側の回路
を非作動状態に切替えることにより達成される。
According to the present invention, this object is achieved by making the load resistance of the detector and the load resistance of the oscillator common, making the output terminal common, and switching the non-selected circuit to the inactive state by the output selection switch. .

以下、本発明を実施例により説明する。 The present invention will be explained below with reference to Examples.

第2図は本発明の一実施例の回路図である。 FIG. 2 is a circuit diagram of one embodiment of the present invention.

1はFM検波器である。i1,i2は入力端子であ
る。FM検波器1は移相回路6と二重平衡差動形
乗算器とからなるクオドラチヤー検波器で構成さ
れている。7は二重平衡形乗算器の定電流源用の
トランジスタである。2は発振器であり、抵抗8
および10は発振器用の抵抗であり、コンデンサ
9および11は発振器用のコンデンサである。1
2は発振器2の定電流源用のトランジスタであ
る。13はFM検波器1と発振器2の負荷抵抗で
あり、FM検波器1と発振器2とに共通にしてあ
る。14は定電圧電源であり、FM検波器1の出
力、または発振器2の出力はトランジスタ15か
らなるエミツタホロワを通して共通の出力端子1
6に出力される。
1 is an FM detector. i 1 and i 2 are input terminals. The FM detector 1 is composed of a quadrature detector consisting of a phase shift circuit 6 and a double-balanced differential multiplier. Reference numeral 7 designates a transistor for a constant current source of the double-balanced multiplier. 2 is an oscillator, and resistor 8
and 10 are resistors for the oscillator, and capacitors 9 and 11 are capacitors for the oscillator. 1
2 is a constant current source transistor for the oscillator 2; 13 is a load resistance for the FM detector 1 and the oscillator 2, which is common to the FM detector 1 and the oscillator 2. 14 is a constant voltage power supply, and the output of the FM detector 1 or the output of the oscillator 2 is connected to the common output terminal 1 through an emitter follower consisting of a transistor 15.
6 is output.

一方、選択スイツチ3′はその切替によりFM
検波器1の定電流源用のトランジスタ7に定電圧
源17からベースバイアス電流を供給してFM検
波器1を動作状態に、または発振器2の定電流源
用のトランジスタ12に定電圧源17からベース
バイアス電流を供給して発振器2を動作状態にす
るとともに、非選択側の回路、すなわちFM検波
器1を選択したときは発振器2が、発振器2を選
択したときはFM検波器1が非作動状態となるよ
うに構成する。
On the other hand, the selection switch 3' changes to FM.
The base bias current is supplied from the constant voltage source 17 to the transistor 7 for the constant current source of the detector 1 to put the FM detector 1 into operation, or the constant voltage source 17 is supplied to the transistor 12 for the constant current source of the oscillator 2. Supplying base bias current to put oscillator 2 into operation state, and when selecting the non-selected circuit, that is, FM detector 1, oscillator 2 becomes inactive, and when oscillator 2 is selected, FM detector 1 becomes inactive. Configure it so that it is in the state.

以上の如く構成した本実施例において、FM検
波器1と発振器2とは選択スイツチ3により選択
されて、定電流源用のトランジスタ7または12
に定電圧源17からベースバイアス電流が供給さ
れ、FM検波器1と発振器2との動作は、作動か
停止かを制御される。
In this embodiment configured as described above, the FM detector 1 and the oscillator 2 are selected by the selection switch 3, and the constant current source transistor 7 or 12 is selected.
A base bias current is supplied from a constant voltage source 17 to the FM detector 1 and the oscillator 2, and the operations of the FM detector 1 and the oscillator 2 are controlled to be activated or stopped.

また、FM検波器1と発振器2は負荷抵抗13
が共通で定電圧源14に接続されているために、
FM検波器1の動作点と発振器2の動作点とは同
一になつている。
In addition, the FM detector 1 and oscillator 2 are connected to the load resistor 13.
are commonly connected to the constant voltage source 14,
The operating point of the FM detector 1 and the operating point of the oscillator 2 are the same.

いま、選択スイツチ3′で第2図に示す如く発
振器2を選択したときは、トランジスタ12にベ
ースバイアス電流が供給されて発振器2は作動状
態となり、共通負荷点Pには発振器2の発振信号
が現われる。一方、この場合にトランジスタ7に
はベースバイアス電流が供給されずFM検波器1
は停止状態となつている。そこで共通負荷点Pか
らFM検波器1側をみた回路は開放状態となつて
いて、共通負荷点Pに現われた発振器2の発振信
号はFM検波器1の影響を受けずに、エミツタホ
ロワトランジスタ15を通して出力端子16に出
力される。
Now, when the selection switch 3' selects the oscillator 2 as shown in FIG. 2, the base bias current is supplied to the transistor 12, the oscillator 2 is activated, and the oscillation signal of the oscillator 2 is applied to the common load point P. appear. On the other hand, in this case, the base bias current is not supplied to the transistor 7 and the FM detector 1
is in a stopped state. Therefore, the circuit viewed from the common load point P to the FM detector 1 side is in an open state, and the oscillation signal of the oscillator 2 that appears at the common load point P is not affected by the FM detector 1, and is transferred to the emitter follower. The signal is outputted to the output terminal 16 through the transistor 15.

つぎに選択スイツチ3′を前記の位置から切替
えたときは、トランジスタ7にベースバイアス電
流が供給されてFM検波器1は作動状態となり、
共通負荷点PにはFM検波器1からの音声信号が
現われる。一方、この場合にトランジスタ12に
はベースバイアス電流は供給されず発振器2は停
止状態になつている。そこで共通負荷点Pに現わ
れたFM検波器1からの音声信号はエミツタホロ
ワトランジスタ15を通して出力端子16に出力
される。この場合、発振器2は完全にその動作を
停止しているため音声信号は発振器2の影響を受
けることもない。
Next, when the selection switch 3' is switched from the above position, the base bias current is supplied to the transistor 7, and the FM detector 1 is activated.
The audio signal from the FM detector 1 appears at the common load point P. On the other hand, in this case, no base bias current is supplied to the transistor 12, and the oscillator 2 is in a stopped state. Therefore, the audio signal from the FM detector 1 appearing at the common load point P is outputted to the output terminal 16 through the emitter follower transistor 15. In this case, since the oscillator 2 has completely stopped its operation, the audio signal is not affected by the oscillator 2.

また、選択スイツチ3′の切替時において、共
通負荷点Pの動作点は前記した如く同一であるた
め、選択スイツチ3の切替によつてシヨツク音が
発生することもない。
Furthermore, since the operating point of the common load point P is the same as described above when the selection switch 3' is switched, no shock noise is generated by the switching of the selection switch 3'.

以上説明した如く本発明によればFM検波器と
発振器とは負荷抵抗を共通に接続されて動作点を
同一にしているために、選択スイツチの切替時に
シヨツク音を発生することもない。
As explained above, according to the present invention, since the FM detector and the oscillator have the same load resistance and the same operating point, no shock noise is generated when the selection switch is switched.

また選択スイツチにより選択されていない方の
回路は完全に停止状態にあり、出力信号が選択さ
れていない方の回路によつて影響されることはな
い。たとえば音声信号出力中には発振器は完全に
停止状態となつているため、音声信号中に発振出
力や雑音が混入することもない。さらに本発明で
は2系統の出力回路を1つの出力端子に共通接続
しているために、集積回路化したときに、パツケ
ージのピン数を節約することができる。
Further, the circuit not selected by the selection switch is completely stopped, and the output signal is not affected by the circuit not selected. For example, since the oscillator is completely stopped while the audio signal is being output, no oscillation output or noise will be mixed into the audio signal. Furthermore, in the present invention, since the two output circuits are commonly connected to one output terminal, the number of pins of the package can be reduced when integrated circuits are formed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の出力選択回路のブロツク図、第
2図は本発明の一実施例の回路図である。 1……FM検波器、2……発振器、3′……選
択スイツチ、7,12……定電流源用のトランジ
スタ、13……負荷抵抗、14,17……定電圧
源。
FIG. 1 is a block diagram of a conventional output selection circuit, and FIG. 2 is a circuit diagram of an embodiment of the present invention. 1... FM detector, 2... Oscillator, 3'... Selection switch, 7, 12... Transistor for constant current source, 13... Load resistor, 14, 17... Constant voltage source.

Claims (1)

【特許請求の範囲】[Claims] 1 磁気録音機の録音レベル校正用の基準信号を
発振する発振器を有する放送受信機において、放
送受信機の検波器の直流動作点と前記発振器の直
流動作点とを同一にし、かつ、それぞれの出力発
生点を共通出力端子に接続し、前記検波器または
発振器の出力を、選択スイツチにより非選択側の
回路を非作動状態にし、かつ、選択側の回路を作
動状態にして選択することを特徴とする出力選択
回路。
1. In a broadcasting receiver having an oscillator that oscillates a reference signal for calibrating the recording level of a magnetic recorder, the DC operating point of the detector of the broadcasting receiver and the DC operating point of the oscillator shall be the same, and the respective outputs shall be the same. A generation point is connected to a common output terminal, and the output of the detector or oscillator is selected by setting a non-selecting side circuit in an inactive state and a selecting side circuit in an active state by a selection switch. output selection circuit.
JP11879080A 1980-08-27 1980-08-27 Output selecting circuit Granted JPS5744206A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11879080A JPS5744206A (en) 1980-08-27 1980-08-27 Output selecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11879080A JPS5744206A (en) 1980-08-27 1980-08-27 Output selecting circuit

Publications (2)

Publication Number Publication Date
JPS5744206A JPS5744206A (en) 1982-03-12
JPH0221041B2 true JPH0221041B2 (en) 1990-05-11

Family

ID=14745152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11879080A Granted JPS5744206A (en) 1980-08-27 1980-08-27 Output selecting circuit

Country Status (1)

Country Link
JP (1) JPS5744206A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5213708A (en) * 1975-07-23 1977-02-02 Seiko Epson Corp Telephone set

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5645116Y2 (en) * 1974-12-18 1981-10-21

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5213708A (en) * 1975-07-23 1977-02-02 Seiko Epson Corp Telephone set

Also Published As

Publication number Publication date
JPS5744206A (en) 1982-03-12

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