JPH02207563A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction from occurring by a method wherein a terminal resistor and a capacitor terminating a transmission line transmitting input signals to a circuit are formed near an input stage in a chip. CONSTITUTION:Silicon ion is implanted in a semiinsulating GaAs substrate 20 while an n type conductive layer 15 and another n type conductive layer 17 as a terminal resistor R are formed. Next, after a gate electrode 19 of a FET is formed of a tungsten nitride, an ohmic electrode is formed by piling AuGe/Au upward. Next, an input pad 13, the gate electrode 19 of an input FET 9, another input pad 13 and the terminal resistor R are connected by the first wiring layer 27 comprising the three layer upward structure of Ti/Pt/ Au. Furthermore, the wiring layer 21 to be one electrode of a capacitor CB extending from one end of the terminal resistor R is formed in rectangular shaped on the GaAs substrate 20. Next, an SiO2 film is formed by CVD process on the upper part of this rectangular shaped wiring layer 21 and then the SiO2 film 24 to be an interlayer insulating film 23 is selectively turned into a thin layer by reactive ion etching process. Through these procedures, ringing or reaction is reduced for high frequency input signals, thereby enabling a semiconductor integrated circuit to be operated normally and rapidly.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit that receives and processes a high frequency input signal, and particularly to a circuit that terminates a transmission line through which a high frequency input signal is transmitted. The present invention relates to a semiconductor integrated circuit comprising:

(Prior Art) Recent electronic devices are required to speed up data processing. In line with this, development of semiconductor integrated circuits (hereinafter referred to as rGaAs IC4) using gallium arsenide (GaAs) FETs with high electron mobility as basic elements is progressing. This GaAsIC is beginning to be applied as an ultra-high-speed IC in fields such as communication, measurement, and computers. For example, frequency dividers that can directly divide microwaves in the 10 to 20 GHz band have been manufactured.

In this way, since the ultra-high-speed TC processes signals in the GHz band, a mounting technology corresponding to this is required. With conventional integrated circuit mounting technology, the electrical characteristics of the system hardly change due to mounting. However, when implementing ultra-high-speed ICs, parameters such as the characteristic impedance of the signal transmission path have a large effect on high frequencies. For this reason, these must be taken into consideration when designing a system by implementing ultra-high-speed ICs.

For example, when multiple ICs that process high-frequency signals are mounted on a printed circuit board, if the characteristic impedance of the wiring path connecting the ICs is not taken into account, a portion of the signal propagating through the wiring path will be reflected at the end. , ringing occurs. As a result, there is a risk of system malfunction.

Therefore, it is necessary to make the characteristic impedance of all wiring paths the same (for example, 50Ω) and to terminate each wiring path with this characteristic impedance. That is, I.C.
The input impedance of the circuit must be matched with the characteristic impedance of the wiring path.

Various methods have been considered for termination. For example, as shown in FIG.
When the frequency divider 3 composed of s1C receives signals, a termination circuit 5 called "capacitive coupling" is used.

This termination circuit 5 includes a transmission line 7 between the VCOI and the frequency divider 3.
It is inserted near the frequency divider 3 in the. That is,
The termination circuit 5 is provided at the end of the transmission line 7. The termination circuit 5 combines the VCOI and the frequency divider 3, and
a capacitor Cc with negligible impedance for the oscillation frequency, a terminating resistor R with the same impedance as the characteristic impedance of the transmission line 7 (for example, 50Ω), and a capacitor CB with an impedance value considerably smaller than the characteristic impedance of the transmission line 7. It is composed of. The terminating resistor R and the capacitor C8 are connected in series between the transmission line 7 on the input pin side connected to the input FET 9 of the frequency divider 3 and the ground, and a predetermined terminating voltage v7T is applied to the series connection point. .

In such a configuration, the input signal to the frequency divider 3 outputted from the VCOI is given to the termination circuit 5 via the input terminal (2), and is applied to the termination circuit 5 via the coupling capacitance Cc and the termination resistor R to the termination voltage vrt. terminated in In addition, the switching noise of the input FET 9 is led to the ground via the capacitor CB,
This prevents fluctuations in the termination voltage VTT.

(Problems to be Solved by the Invention) As described above, in the conventional termination circuit 5, as shown in FIG. was.

For this reason, the output side of the termination circuit 5 (point 0 in Fig. 5) - the input pin of the frequency divider 3 - the bonding wire cover connecting the input cover and the input pad -> the input cover and the input FE
Wiring connecting the gate of T-gate of human-powered FET (5th
Between point 0 in the figure, the oven stub state is reached.

As a result, when the frequency of the input signal exceeds 10 GHz, the oven stub state generated at the 0 point and the 0 point cannot be ignored with respect to signal propagation. Therefore, reflection or ringing of the input signal may occur between the 0 point and the ■ point, which may cause a delay in signal propagation or malfunction.

Therefore, this invention was made in view of the above, and its purpose is to reduce ringing and reflection for high-frequency input signals without increasing the occupied area, and to provide high-speed and normal operation. The object of the present invention is to provide a semiconductor integrated circuit that can operate in the following manner.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a substrate, a ground wiring path formed on the substrate, and a ground wiring path formed on the substrate adjacent to the ground wiring path. A resistor having the impedance of the transmission line through which the input signal is transmitted is connected in series with a capacitor whose one electrode is the ground wiring path, and a predetermined termination voltage is applied to this series connection point to terminate the transmission line. The present invention provides a semiconductor integrated circuit characterized in that the capacitor is formed in a layered manner on the ground wiring path.

(Function) In the above configuration, the present invention forms a terminating resistor and a capacitor for terminating a transmission line for transmitting a human-powered signal into the circuit near the input stage in the chip, and connects one electrode of the capacitor to the vicinity of the human-powered stage. The ground wiring path is formed as a ground wiring path.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing the arrangement of main parts of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing a pattern layout of the circuit shown in FIG. 1. In the embodiments shown in both figures, a terminating resistor R and a capacitor CB constituting a terminating circuit are arranged immediately before a human power stage in, for example, a GaAs IC chip 11 that processes high frequency human power signals at high speed.

In FIG. 1, the coupling capacitance Cc constituting the termination circuit is
It is provided outside the IC chip 11.

On the other hand, the termination resistor R and the capacitor C5 that absorbs the switching noise of the human input FET 9 are connected to the human input pad 13 and the input FET 9.
connected in series between the wiring path connecting the IC and the ground.
It is arranged and formed within the chip 11. A terminating voltage vT is applied to the series connection point between the terminating resistor R and the capacitor Cs.

Next, one method for arranging and forming such a structure within the IC chip 11 will be described with reference to FIG. 2 and FIG. 3 showing a cross section taken along line xx' in FIG. 2.

First, silicon (Sl) was deposited on a semi-insulating QaAs substrate.
For example, the ions are accelerated at a dose of 2 at an acceleration energy of 50 KeV.
Ion implantation was performed under the conditions of ×10I2■-2, and FE
An n-type conductive layer (active layer) 15 that becomes the source region and drain region of the T (field effect transistor) and, for example, 50
An n-type conductive layer 17 of a terminal resistor R having an impedance of Ω is formed. Next, one gate electrode of the FET is formed of tungsten nitride, and then ohmic electrodes, which will become the source and drain electrodes of the FET and the electrodes at both ends of the termination resistor R, are formed by laminating AuGe/Au from below.

Next, input pad 13 and gate electrode 19 of input FET 9
Then, connect the input pad 13 and the termination resistor R to the TI/P from below.
Connection is made by a first wiring layer 21 having a three-layer structure of t/Au. Also, the first electrode, which is one electrode of the capacitor CB,
The third wiring layer 21 is extended from one end of the terminating resistor R to
a Formed in a rectangular shape on an As substrate. Next, a 5to2 film having a thickness of 6,000 layers is formed on top of this rectangular wiring layer 21 by atmospheric pressure CVD. This 8102 film serves as an interlayer insulating film of the capacitor CB.

Here, the impedance (Z) of the capacitor CB, which explains the capacitance value and occupied area of the capacitor C, is I21-1
/2πfC, (Ω). f is the frequency of the applied signal and C
B is the capacitance value.

Here, suppose that an input signal of, for example, 12 GHz is to be processed, and the impedance of the capacitor CB is set to the terminating resistance value (for example, 5
Set it to about 5% or less of 0Ω). In such a case, cB-'3pF'.

I21-2.6Ω.

On the other hand, the capacitance value of capacitor CB is expressed by the following equation as an approximation of parallel plates.

CB″ε0εS·A/dOx Here, ε〇−dielectric constant in vacuum, εS−relative dielectric constant of interlayer insulating film, dox−thickness of interlayer insulating film, A− opposing area between both electrodes.

In the above formula, dox-6000 people and CB-59F
In order to obtain a capacitance value of A-5×104 μ2. Therefore, the thickness of the interlayer insulating film is 600 mm.
If there were no people, an extremely large occupied area would be required to form the capacitor CB.

Therefore, in this embodiment, as shown in FIG. 3, the 5to2 film which becomes the interlayer insulating film 23 was selectively thinned to a thickness of 1000 by reactive ion etching. Thereby, the capacity per unit area can be increased six times.

Therefore, in order to set the capacity CB to 59F, A → 8
The area is approximately 400 μ2, and can be formed with an area of 176 compared to the above-mentioned one.

Therefore, the second wiring layer 25, which has the same structure as the first wiring layer 21, becomes the ground wiring of the IC chip 11 by passing through the upper part of the thinned interlayer insulating film 23.
It is formed with a line width (W) of 00μ, and the area occupied by the capacitor CB is 8
It is formed into a rectangular shape of 0μ×140μ.

As described above, in this embodiment, as a feature in forming the capacitor CB, one of the grounded electrodes of the capacitor CB is connected to the IC.
The second wiring layer 25 serves as the ground wiring for the chip 11
The reason lies in the fact that That is, the ground wiring is used as the electrode of the capacitor CB. As a result, the capacity C
It is no longer necessary to secure a space for forming B, and forming the termination circuit within the chip does not significantly increase the chip area.

On the other hand, the terminal voltage v7. is given from a termination voltage supply line 29 connected to a connection portion 27 between the termination resistor R and the first wiring layer 21, which serves as one electrode of the capacitor CB.

In this way, by arranging and forming the terminating resistor R and capacitor Ca of the terminating circuit immediately before the input FET 9, the oven stub area that conventionally occurs can be significantly reduced. As a result, the input voltage sensitivity when the input signal is 12 GHz can be improved by about 8 dB compared to the conventional method.

FIG. 4 is a diagram showing the main part configuration of a semiconductor integrated circuit according to another embodiment of the present invention, FIG. 4(A) is a circuit diagram showing the circuit configuration, and FIG. It is a figure which shows the pattern layout of the circuit shown in (A).

The feature of this embodiment is that the termination voltage supply line 29 that supplies the termination voltage vT7 shown in the above-mentioned embodiment is not formed, but the power supply wiring and ground wiring that are arranged and formed around the IC chip 11 are used. Therefore, 77 terminal voltages are generated and supplied at each signal input section.

In FIG. 4(A), the termination voltage VTT is a resistor RI connected in series between the power supply Vdd and the ground.

It is generated by resistance-dividing the power supply voltage by R2, and is supplied to the terminating resistor R from the series connection point. Here, the resistance value of the resistor RI*R2 needs to be set to be sufficiently smaller than that of the terminating resistor R. This is the resistance R
This is because if the resistance value of 1tR2 is not sufficiently smaller than the terminating resistor R, fluctuations in the terminating voltage VTT will increase.

Such resistors R1+R2 are connected to F in the IC chip 11.
Ion implantation under different conditions than the n-type conductive layer of ET and termination resistor R, e.g. 5X 1013 am- at 120 KeV
By ion implantation of ', as shown in Fig. 4(B),
A connecting portion 27 between the terminating resistor R and the capacitor CB is connected to the power supply wiring 31 and the ground wiring 25.

In such an embodiment, the same effects as the above-described embodiment can be obtained, and a dedicated wiring path for supplying the termination voltage VTT is not required. This makes it possible to suppress an increase in chip area due to forming the termination resistor R and capacitor CB within the IC chip 11, compared to the embodiments described above.

[Effects of the Invention] As explained above, in the present invention, the terminating resistor and capacitor for terminating the transmission line that transmits the input signal into the circuit are formed near the input stage in the chip. The area that becomes oven stub is significantly reduced. This reduces input signal reflection and ringing, prevents malfunctions, and allows normal operation at high speed.

In addition, since one electrode of the capacitor is formed using a ground wiring path placed around the input stage, the increase in chip area can be suppressed even if the terminating resistor and capacitor are formed within the chip. be able to.

[Brief explanation of the drawing]

1 is a diagram showing the arrangement of main parts of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing a pattern layout of the circuit shown in FIG. 1, and FIG. −
4 is a diagram showing the arrangement of main parts of a semiconductor integrated circuit according to another embodiment of the present invention, and FIG. 5 is a diagram showing an example of the configuration of a termination circuit used in a conventional semiconductor integrated circuit. FIG. 9...Input FET 11-Ga As IC chip 25...Ground wiring R...Terminal resistor CB...Capacity W 9 Manual FET Figure 4 (A)

Claims (3)

[Claims] (1) A substrate, a ground wiring path formed on this substrate, and a ground wiring path formed on a substrate adjacent to this ground wiring path,
A circuit that terminates the transmission line by connecting in series a resistor having the impedance of a transmission line through which an input signal is transmitted and a capacitor whose one electrode is the ground wiring line, and applying a predetermined termination voltage to this series connection point. A semiconductor integrated circuit characterized in that the capacitor is formed in a layered manner on the ground wiring path. (2) The semiconductor integrated circuit according to claim 1, wherein the capacitor is formed by thinning the interlayer insulating film by etching. (3) The terminating voltage is obtained from a series connection point of resistors connected in series between a power wiring path and a ground wiring path arranged around the input stage. The semiconductor integrated circuit described.