JPH02201706A - Reproducing circuit for disk device - Google Patents

Abstract

PURPOSE:To prevent the saturation of an equalization-corrected signal by providing AGC amplifiers on the respective stages of an equalizing circuit to correct a peak shift and an equalizing circuit to correct an amplitude fluctuation, providing level detecting circuits on respective output stages, making constant the output level of the equalizing circuit by means of the gain control of the AGC amplifier. CONSTITUTION:Gain controllable AGC amplifiers 22 and 24 are provided on the respective stages of a first equalizing circuit 12, which corrects the peak shift of a reproduced signal read from a head 10, and a second equalizing circuit 14, which corrects the amplitude fluctuation of the reproduced signal from the head 10. Level detecting circuits 26 and 28, which detect output signal levels to respective output stages, are provided, and the amplitude gains of the AGC amplifiers 22 and 24 are controlled so as to make constant the output level of the first and second equalizing circuits 12 and 14 based on the detection level of the level detecting circuits 26 and 28. Thus since the output signals of the equalizing circuits 12 and 14 are not affected by the fluctuation of the head output, the peak position and amplitude of the reproduced signal can be correctly detected, and the reliability at the time of reproducing the signals can be improved.

Description

[Detailed description of the invention] [N required] Regarding a reproduction circuit of a disk device that performs equalization correction for peak shift and amplitude fluctuation on a reproduction signal read from a head and then converts it into a rectangular wave signal, In order to improve the reliability of signal reproduction by preventing signal saturation and level insufficiency, an AGC amplifier is installed at each input stage of the equalization circuit that corrects peak shifts and the equalization circuit that corrects amplitude fluctuations. A level detection circuit is provided at the output stage, and the output level of the equalization circuit is made constant by controlling the gain of the AGC amplifier based on the level detection at the output stage.

[Industrial Application Field] The present invention relates to a reproduction circuit for a disk device that performs peak shift and equalization correction for amplitude fluctuations on a reproduction signal successively output from a head and then converts the signal into a rectangular wave signal.

The reproduction circuit of a magnetic disk device detects the peak position of the reproduction signal read from the head, detects the amplitude width exceeding a predetermined slice level, and reproduces the original signal based on the detected peak position and amplitude width. The aim is to create a rectangular wave signal that faithfully represents the image.

In the playback circuit of such a disk device, since the peak position of the playback signal shifts due to the correlation with other adjacent peak positions (size of time interval), equalization is performed to correct this peak shift. A circuit is required. Furthermore, since the amplitude of the reproduced signal fluctuates when the reproduction frequencies differ, an equalization circuit is required to correct the amplitude fluctuation.

Furthermore, since the optimal values of the equalization circuit that corrects peak shift and the equalization circuit that corrects amplitude fluctuation do not match, it is desirable to set the optimal equalization characteristics in consideration of this point. Furthermore,
Since the head output fluctuates due to variations in each head, the track position of the head, etc., equalization characteristics that can be converted into an appropriate rectangular wave signal without being affected by this output fluctuation are required.

[Prior Art] FIG. 5 is a block diagram showing a reproducing circuit already proposed by the inventors of the present application.

In FIG. 5, 10 is a head, and the reproduced signal read from the head 10 is transmitted to a preamplifier 46 with a constant gain.
is amplified. The output of the preamplifier 46 is divided into two branches and then pulled up to the power supply voltage Vcc via resistors 38 and 40, and a first equalization circuit 12 corrects the peak shift;
The signal is input to a second equalization circuit 14 that corrects amplitude fluctuations.

The output of the equalization circuit 12 is input to a peak position detection circuit 16, which differentiates the reproduced signal and then inputs it to a zero-cross comparator to detect the peak at which the reproduced signal rises to an H level at the peak position and maintains the H level for a predetermined time. Position detection signal (
(square wave signal).

The output of the second equalization circuit 14 is input to the amplitude detection circuit 18, which generates an amplitude detection signal (rectangular wave Generate belief @). Finally, the separation circuit 20 performs a logical product (AND) of the outputs of the peak position detection circuit 16 and the amplitude detection circuit 18 to produce a reproduced signal whose waveform has been shaped into a rectangular wave signal.

The first equalization circuit 12 has a delay line 30-1°30-2
, attenuator 32-1, 32-2, and brightness amplifier 34-
Similarly, the second equalization circuit 14 includes a delay line 30-3, 30-4, an attenuator 32-3, 32-4, and an addition/subtraction amplifier 34-2.

The reason why the circuit configuration is such that the output of the head 10 is branched into two and input to the two equalization circuits 12 and 14 individually is as follows.
This is due to the fact that the optimum value of the attenuator for correcting the peak shift and amplitude fluctuation is different, and the optimum value of the attenuator can be set individually in each equalization circuit 12, 14.

Here, as shown in FIG. 6, the reproduced signal from the head 10 has negative edges 44, which are amplitude components of opposite polarity, before and after the main signal waveform 42. Therefore, in the equalization circuit 12.14 of FIG. 5, the attenuator 32-1.32
-3 sets the attenuation amount mainly for correcting the peak shift and amplitude fluctuation of the main signal waveform 42, and the attenuator 32
-2°32-4 sets the attenuation amount for correcting the pix shift and amplitude fluctuation caused by the negative edge 44.

[Problems to be Solved by the Invention] However, in such a reproducing circuit, the output signal from the head fluctuates depending on variations in the head output and the track position of the head, and due to the fluctuation in the head output, etc. There is a problem in that the output of the converter circuit fluctuates, and peak position detection and amplitude detection cannot be performed normally.

That is, when the output of the first equalization circuit 12 becomes saturated or becomes insufficient in level, an erroneous peak position may be detected or the peak position may not be detected. Furthermore, when the output of the second equalization circuit 14 becomes saturated or becomes insufficient in level, an abnormally long amplitude detection signal is output, amplitude detection becomes impossible, and the signal level becomes too low with respect to the reference voltage from the reference voltage generation circuit 36. This fluctuation causes problems such as noise, which deteriorates the reliability of signal reproduction.

The present invention has been made in view of such conventional problems, and provides a playback circuit for a disk device that prevents saturation or insufficient level of an equalization-corrected signal and improves the reliability of signal playback. The purpose is to

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, the present invention first includes a head 10, a first equalization circuit 12 that corrects the peak shift of the reproduced signal read from the head 10, and a first equalizer circuit 12 that corrects the amplitude fluctuation of the reproduced signal from the head 10. a peak position detection circuit 16 that detects the peak position from the output signal of the first equalization circuit 12, and a peak position detection circuit 16 that detects the amplitude width exceeding a predetermined level from the output signal of the second equalization circuit. An amplitude detection circuit 18 and a separation circuit 2 that outputs a reproduction signal converted into a rectangular wave based on the outputs of the peak position detection circuit 16 and the amplitude detection circuit 18.
The target is a playback circuit for a disk device equipped with 0.

Regarding such a reproducing circuit, in the present invention, an AGC amplifier 22.24 whose gain can be controlled is provided at each input stage of the first and second equalization circuits 12.14, and an output signal level is adjusted at each output stage. A level detection circuit 26.28 is provided to detect the output level of the AGC amplifier 22.24 so that the output level of the first and second equalization circuits 12.14 is kept constant based on the detection level of the level detection circuit 26.28. Control amplification gain.

Here, the first and second equalization circuits 12.14 are connected to the head 1.
A first delay line 3 that sequentially delays the reproduced signal from 0
0-1,3C)-3 and second delay line 30-2.3
0-4 are connected in series and the first delay line 30-
a first attenuator 32-1 that attenuates the output of 1,3C)-3;
．． 32-3 and a second attenuator 32-2.32-4 that directly attenuates the reproduced signal from the head 10, and the second delay line 30-2.
The outputs of the first attenuators 32-1 and 32-3 are subtracted from the outputs of the second attenuators 32'-2 and 32-4.
It is configured to add the outputs of 4.

Attenuator 32-1. provided in first equalization circuit 12.
32-2 makes it possible to set the optimum value for correcting the peak shift, and the attenuator 32-3, 32-4 provided in the second equalization circuit 14 sets the optimum value for correcting the amplitude fluctuation. I think it's possible.

[Function] In the playback circuit of the disk device according to the present invention having such a configuration, even if the bed output fluctuates due to variations in each head or the track position of the head, the output level of the equalization circuit can be maintained. The gain of the AGC amplifier installed at the input stage of the equalization circuit is controlled to keep it constant, and the output signal of the equalization circuit is not affected by fluctuations in head output.
By accurately detecting the peak position and amplitude of the reproduced signal, reliability during signal reproduction can be greatly improved.

[Embodiment] FIG. 2 is a block diagram showing an embodiment of the present invention.

In FIG. 2, 10 is a head, and a read signal from the head 10 is amplified by a preamplifier 46 having a constant gain, and the preamplifier 46 branches the signal into two outputs. One output of the preamplifier 46 is sent to the first equalization circuit 1 via the AGC amplifier 22, which will be explained later.
2 is input. The first equalization circuit 12 is provided to correct the peak shift, and sets a first delay line 30-L having a delay time τ1, a second delay line 30-2 having a delay time τ2, and an attenuation amount Z11. The first attenuator 32
'-1, the second attenuator 32-2 that sets the attenuation amount Z12
, further includes an addition/subtraction amplifier 34-1. Addition/subtraction amplifier 3
4-1 via delay line 30-1.30-2 (τ
The output of the attenuator 32-1 is subtracted from the reproduced signal delayed by 1+τ2), and the output of the attenuator 32-2 is further added.

On the other hand, the other output of the preamplifier 46 is sent to the second equalization circuit 14 via the AGC amplifier 24, which will be explained later.
is input. The second equalization circuit 14 is provided to correct amplitude fluctuations, and sets a first delay line 30-3 having a delay time τ1, a second delay line 30-4 having a delay time τ2, and an attenuation amount Z21. First attenuator 3
2-3, second attenuator 32-4 that sets attenuation amount Z22
, further includes an addition/subtraction amplifier 34-2. Addition/subtraction amplifier 3
4-2 is the delay line 30-3.30-4 (τ1+τ
The attenuator 323 is subtracted from the reproduced signal delayed by 2) and the output of the attenuator 324 is added to output a signal.

Note that in the first and second equalization circuits '12.14,
The first attenuator 32-1, 32-3 sets a value for correcting the peak shift and amplitude fluctuation of the head reproduction signal waveform shown in FIG. 6 with respect to the main signal waveform 42, and the second
The attenuators 32-2 and 32-4 set values for correcting peak shifts and amplitude fluctuations caused by negative edges 44 that exist before and after the main signal waveform 42.

The output of the first equalization circuit 12 that corrects the peak shift is given to the peak position detection circuit 16. The peak position detection circuit 16 includes a differentiation circuit 48 and a zero cross comparator 50.
is provided. The differentiating circuit 48 differentiates the reproduced signal from the first equalizing circuit 12 to produce a differential signal that crosses zero at the peak position. The zero cross comparator 50 rises to the H level at the zero cross of the differential signal and remains H for a predetermined time.
Generates a peak position detection signal (square wave signal) that maintains the level.

On the other hand, the output of the second equalization circuit 14 that corrects amplitude fluctuations is given to the amplitude detection circuit 18. The amplitude detection circuit 18 includes comparators 52 and 54 that form a window comparator, and the comparators 52 and 54 receive positive and negative reference voltages +vr from the reference voltage sources 55 and 56 of the reference voltage generation circuit 36.

-Vr is set. Therefore, the amplitude detection circuit 18
An amplitude detection signal is generated according to the time width during which the reproduced signal from the equalization circuit 14 exceeds the slice level of the reference voltage ±Vr, that is, the amplitude time width.

The outputs of the peak position detection circuit 16 and the amplitude detection circuit 18 are given to a separation circuit 20, and the separation circuit 20 is, for example, an AND
It is composed of a gate 58, and generates a rectangular wave read signal whose waveform is shaped to a predetermined pulse width by taking the logical product of the peak position detection signal and the amplitude detection signal.

In the present invention, regarding the reproduction circuit of such a disk device, AGC amplifiers 22 and 24 are provided at the input stages of the first and second equalization circuits 12 and 14, respectively, and the first and second equalization circuits A level detection circuit 26.28 is provided which receives the output of the circuit 12.14. Level detection circuit 26.2
8 generates a DC voltage that follows the amplitude level change of the reproduced signal by integrating the output signal of each equalization circuit 12.14, and feeds it back to each of the AGC amplifiers 22.24 as an AGC control voltage. As a result, equalization circuit 12.1
AGC amplifier 22, to keep the output level of 4 constant.
It constitutes an AGC control loop that controls the amplification gains of 24.

Here, attenuator 32-1. provided in first equalization circuit 12.
32-2 is determined such that the time width of the rise of the output signal of the zero cross comparator 50 provided in the peak position detection circuit 16 is a predetermined amount.

In addition, an attenuator 32-3.3 provided in the second equalization circuit 14
2-4, the attenuation amount is determined by adding and subtracting the amplitude of the highest frequency f max signal of the read signal from the head 10 and the amplitude of the reproduction signal of the lowest frequency f min.
Set the two outputs to be equal.

Next, the operation of the embodiment shown in FIG. 2 will be explained with reference to the operation signal waveform diagrams shown in FIGS. 3 and 4.

FIG. 3 (A> shows the output signal from the head 10, the output signal from the head 10 has peak positions shown as P1 to P6, and the rear side of the peak position P2, before and after the peak position P3, and the peak position P4 A case is shown in which negative edges 44 are provided before and after the peak position P5, and further before the peak position P5.

The reproduced signal from the head 10 is sent to the preamplifier 4.
After receiving constant gain amplification at AGC amplifier 22.
24 through each of the first and second equalization circuits 12.
14.

At this time, the GC amplifier 22.24 is connected to the equalization circuit 12.1.
A by the level detection circuit 26゜28 provided in the output stage of 4
The amplification gain is controlled in response to a DC voltage for GC control. For example, if the head output level decreases due to variations in each head or head position, the output of the equalization circuit will fluctuate as the head output decreases, and the DC voltage level of the level detection circuits 26 and 28 will also decrease. However, in response to such a decrease in the DC voltage level, the AGC amplifiers 22 and 24 are controlled to increase the amplification gain.

As a result, the output level of equalization circuits 12 and 14 is maintained at a constant level.

FIG. 3(B) shows the output signal waveform of the adder/subtractor amplifier 34-1 provided in the first equalization circuit 12, and the delay time due to the delay line 30-1°30-2 with respect to the head output of FIG. The signal waveform has a peak position with a time delay of (τ1+τ2), and the negative edge 44 in the head output signal has been removed, and the attenuator 32
The peak shift is corrected by i, 32-2.

In addition, in FIG. 3(B), in order to simplify the explanation, the attenuator 32-3, 32- provided in the second equalization circuit 14
The attenuator 32-1.4 is provided with an attenuation amount of 4 in the first equalization circuit.
When the attenuation amount is the same as that of 32-2, that is, Z11=Z2
1. The case where Z12=Z22 is shown. Therefore,
The output of the addition/subtraction amplifier 34-1 of the first equalization circuit 12 is the same as the output of the addition/subtraction amplifier 34-2 of the second equalization circuit 14.

The output of the addition/subtraction amplifier 34-1 of the first equalization circuit 12 shown in FIG. 3(B) is given to the peak position detection circuit 16,
First, the differential circuit 48 converts the signal into a differential signal that crosses zero at the peak position. Subsequently, the zero-cross comparator 50 converts the differential signal into the output signal waveform of the zero-cross comparator 50 shown in FIG. 3(C), which rises to H level at the zero-cross position and maintains the H level state for a certain period of time.

On the other hand, the addition/subtraction amplifier 34- provided in the second equalization circuit 14
The output of 2 is given to the amplitude detection circuit 18, and is shown in FIG. 3(B).
A rectangular wave signal with slice levels of the reference voltage elements Vr and -Vr shown in FIG. 3(D) is obtained as the output of the amplitude detection circuit 18 shown in FIG. 3(D).

Finally, the AND gate 58 of the separation circuit 20 performs a logical product of the peak position detection signal and the amplitude detection signal, producing the rectangular wave signal shown in FIG. 3(E).

FIG. 4 is a signal waveform showing the operation of the first and second equalization circuits 12 and 14 in FIG. 2, taking as an example the isolated waveform at the peak position P3 with the negative edge 44 shown in FIG. It is a diagram.

In FIG. 4, first, the delay line 30 of the equalization circuit 12 is
Suppose that the output signal from the head 10 shown in the figure (A>) is input to -1 in the same figure.The signal from this head is delayed by τ1 time by the delay line 30-1, and becomes the signal shown in Fig. 4 (B). Furthermore, the signal is delayed for 12 hours by the delay line 30-2, resulting in the signal shown in FIG. 4(C).

Here, since the input impedance of the adder/subtracter amplifier 34-1 is sufficiently high, the signal from the delay line 30-2 is reflected at the input end of the adder/subtracter amplifier 34-1, and the reflected signal is sent to the input side via the delay line 30-2. I'm starting to go back.

Therefore, for the attenuator 32-1, the output of the delay line 30-1 and the output of the delay line 30-2 shown in FIG.
The reflected signal returned via the delay line 30-
The reflected signals with a time delay of 2×τ2) with respect to the output of the attenuator 3 are combined and added.
The output of 2-1 has a signal waveform shown in FIG. 4 (D>).

Furthermore, the signal from the head 10 and the delay lines 30-'l, 30-2 shown in FIG.
A composite signal of the reflected signal (having a delay time of 2×(τ1+τ2) with respect to the input signal) reflected from the input stage of the adder/subtractor amplifier 34-1 is inputted through the attenuator 32-2. The output has the signal waveform shown in FIG. 4(E).

Therefore, the adder/subtractor amplifier 34-1 subtracts the output of the attenuator 32-1 shown in FIG. 4(D) from the output of the delay line 30-2 shown in FIG. The output signal from the head 10 is added to produce the output signal waveform shown in FIG. A reproduced read signal can be obtained.

The signals shown in FIGS. 4(A) to 4(F) can be obtained by making the attenuation amounts of the first and second equalization circuits 12 and 14 the same.
Signal waveforms of the same circuit section in the second equalization circuit 14 are shown simultaneously.

The first and second equalization circuits 12 shown in FIG.
．． 14, the head 10 shown in FIG. 3(A)
The continuous reproduced signal waveform is outputted to the adder/subtractor amplifier 34 with the negative edges shown in FIG. 3(B) removed and whose peak position has a time delay of (τ1+τ2) with respect to the input signal.
-1,342 output, that is, the equalization circuit output.

[Effects of the Invention] As described above, according to the present invention, it is possible to always obtain a reproduced signal of constant amplitude from the equalization circuit by suppressing variations in head output and fluctuations due to the track position of the head.
Peak position detection based on the equalization circuit output and amplitude detection using a predetermined reference voltage can be performed accurately and stably, and reliability during signal reproduction can be greatly improved.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention; Fig. 2 is a block diagram of an embodiment of the present invention; Figs. 3 and 4 are operating signal waveform diagrams of the present invention; Fig. 5 is a block diagram of the prior art; Fig. 6 is a head reproduction waveform diagram with negative edges. In the figure, 10: head 12: first equalization circuit (for peak shift correction) 14: second equalization circuit (for amplitude fluctuation correction) 16: peak position detection circuit 18: amplitude detection circuit 20: separation circuit 22 .24: AGC amplifier 26.28 Two-level detection circuit 30-1 to 30-4: Delay line 32-1 to 32-4: Attenuator 34-1.34. -2: Addition/subtraction amplifier 36 Two reference voltage generation circuits 38, 40 Nibble up resistor 42: Main waveform 44: Negative edge 46: Preamplifier 48: Differentiator circuit 50: Zero cross comparator 52.54: Comparator 55.56: Reference voltage source 58: AND gate (A) head 10 power

Claims (2)

[Claims] (1) A head (10) and a first equalization circuit (
12), a second equalization circuit (14) for correcting amplitude fluctuations of the reproduced signal from the head (10), and a peak for detecting the peak position of the output signal of the first equalization circuit (12). a position detection circuit (16) and the second equalization circuit (14);
), the amplitude detection circuit (18) detects an amplitude width exceeding a predetermined level from the output signal of the peak position detection circuit (18);
6) and a separation circuit (20) that outputs a reproduction signal whose waveform has been shaped into a rectangular wave based on the output of the amplitude detection circuit (18), from the head (10). said first inputting a reproduction signal of
An AGC amplifier (22, 24) whose gain can be controlled is provided in each of the input stages of the second equalization circuit (12, 14), and the output of the first and second equalization circuit (12, 14) Each stage has a level detection circuit (
26, 28), and the level detection circuit (26, 28)
The first and second equalization circuits (12
, 14), the amplification gain of the AGC amplifier (22, 24) is controlled so as to keep the output level constant. (2) Each of the first and second equalization circuits (12, 14) has a first delay line (30-1, 30-3) and a first delay line (30-1, 30-3) that sequentially delay the reproduced signal from the head (10). a first attenuator (32-1, 32-3) connecting two delay lines (30-2, 30-4) in series and attenuating the output of the first delay line (30-1, 30-3); and a second one that directly attenuates the reproduced signal from the head (10).
attenuators (32-2, 32-4); (
32-1, 32-3) and the second
a first attenuator (32-2, 32-4) provided in each of the first and second equalization circuits (12, 14); 2. The reproducing circuit for a disk device according to claim 1, wherein the values of the attenuator (32-2, 32-4) and the attenuator (32-2, 32-4) can be adjusted to optimal values specific to each circuit.