JPH02201668A - Memory controller - Google Patents

Abstract

PURPOSE:To freely set the correspondence of a CPU address to a memory by decoding the address generated by a CPU, selecting the register of a corresponding memory block, decoding a selected register value, and outputting corresponding memory selective signal. CONSTITUTION:A register 13, which stores the number of a RAS signal to be outputted corresponding to each block when the address space of the CPU is divided into plural blocks at the same size, a selector 15, which decodes the address issued from the CPU and selects the register value of the corresponding block, and a selector 17, which decodes the selected register value and outputs the corresponding RAS signal, are possessed. Thus the arbitrary memories can be allocated in units of a block, the combination between the CPU address and the basic memory mounted on a system on a standard basis or the memory mounted on a expanded memory slot can be freely set, and hardware can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Field of Application) This invention relates to a memory control device suitable for use particularly in a personal computer.

(Prior Art) In the field of personal computers, option cards are often installed to expand functionality. A memory card is installed to expand memory capacity.

Conventionally, the correspondence between a memory area that is expanded by inserting a memory module into an expansion memory slot and an address space managed by a CPU is fixed by hardware, and usually they are allocated to a continuous space. Furthermore, when combining memory modules with different memory sizes, there are hardware restrictions on how to combine them.

For example, suppose you have the following hardware configuration.

That is, the memory for the first IM byte of the CPU address space is installed in the system as standard. This is called basic memory. There are three expansion memory slots, which are called slot A5, slot B1, and slot C, respectively. There are two types of memory modules: one with a 2M byte capacity and one with a 4M byte capacity.

In this case, the standard combinations of memory expansion that can be considered are limited to 10 as shown in FIG. 4, and combinations other than these are not allowed. The following conditions are set here. In the figure, ■ indicates the basic memory of the IM byte mark, ■ indicates an additional 2 Mbyte memory module, and ■ indicates an additional 4 Mbyte memory module.

(1) Slots A, B, and C correspond from the upper to the lower CPU address.

(2) The addresses between the basic memory and slots I-A and between each slot are always consecutive.

(3) 4M byte memory module after 2M byte capacity memory module
Do not insert Hyde capacity memory modules.

(4) Do not insert a memory module after an empty slot.

DRAM is used for memory, and access selection is RA
According to the S signal, the output conditions of the RAS signal of each slot are as follows.

RAS output conditions for slot A When an expansion memory module with a capacity of 2M or so is installed in slot A, when the CPU accesses an address space from 1M byte to 3M bytes, or when slot A When the CPU accesses the address space from 1MB to 5MB when an expansion memory module with a 4MB capacity is installed.

RAS output condition of thrower L-B When the expansion memory module of 2M Hyde Yosei is placed in slots A and B, the CPU is 3MB to 5MB.
When the address space of the hide is accessed, or when an additional memory module with a 4M hide capacity is installed in thrower l-A and an additional memory module with a 2M byte capacity is installed in slot B, the CPU starts from 5M bytes. When accessing an address space up to 7M bytes, or when the CPU accesses an address space between 5M bytes and 9M bytes when an expansion memory module with a 4M hide capacity is inserted in slot AB.

RAS output condition of slot C When an expansion memory module with 2M hide capacity is installed in ports A, B, and C, the cPU will change from 5MB to 7MB.
When an address space up to M bytes is accessed, or when an expansion memory module with a 4M hide capacity is inserted in slot A, and an expansion memory module with a capacity of 2M hide capacity is inserted in slots B and C, When the CPU accesses the address space from 7M bytes to 9M bytes, or an additional memory module with a capacity of 4M bytes is placed in slots A and B, and an additional memory module with a 2M hide capacity is placed in slot hC. When the CPU is 9MB to 11
When accessing an address space of up to M bytes, or when an additional memory module with a capacity of 4M/< bytes is placed in the thrower l-AB, C, the CPU
11S0, which accessed an address space of 3M bytes, does not meet these conditions and the logic will be assembled in hardware.

(Problems to be Solved by the Invention) According to the above conventional example, the RAS signal output to each slot must be created by decoding all the conditions allowed for that slot. In addition, in order not to reduce the decoding conditions, it is necessary to impose restrictions on the combination of memory expansions. Relaxing those constraints had the disadvantage of making the hardware that much more complex.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a memory control device that eliminates the above-mentioned constraints and realizes them using simple logic.

[Structure of the Invention (Means for Solving the Problems)] The present invention provides a computer in which memory can be expanded by inserting a memory module into an expansion memory slot in addition to the memory that is standardly installed in the system. The address space managed by the CPU is divided into multiple equal areas, each area has an independent register, and the memory is either the standard memory installed in the system or the memory of a memory module inserted into any expansion memory slot. This is a memory control device that can arbitrarily allocate memory by setting in the register for each area whether the area is to be used or not.

(Function) As described above, the present invention includes a register that remembers the number of the RAS signal to be output corresponding to each block when the CPU address space is divided into a plurality of blocks of equal size. , by having a selector that decodes the address issued by the CPU and selects the register value of the corresponding block, and a selector that decodes the selected register value and outputs the corresponding RAS signal. Memory can be allocated.

As a result, the correspondence between the CPU address and the basic memory installed as standard in the system or the memory installed in the expansion memory slot can be freely set, and the hardware can be simplified.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Here, it is assumed that there are three expansion memory slots, the CPU address space is 16 Mbytes, and the system has IM bytes as standard memory.

In the figure, 11 is a basic memory, which has a standard capacity of 1 Mbyte in the system. Selected by RASO. Reference numeral 12 is an expansion memory slot, which has three slots.

Slot A is RASI and RAS2, slot B is RA
S3 and RAS4 select slot C, and RAS5 and RAS6 select the slot C, respectively. Reference numeral 13 denotes 16 independent registers each having a length of 4 bits, and remembers the number corresponding to the RAS signal supplied to each slot.

Each register value from “0” to “6” is RASO.
A register value of "7" or higher does not correspond to any RAS signal.

14 is a decoder, which selects the upper 4 pins of the CPU address.
Select one 1M byte block from.

A selector 15 outputs the RAS number of the selected block. A decoder 16 selects one RAS signal from the RAS number.

No RAS signal is selected when the RAS number is "7" or higher. A gate 17 outputs a selected RAS signal. 18 is a gate, which indicates that memory access is performed to a block selected by the CPU address.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. C
Assume that the total address space that can be accessed by the PU is 16 Mbytes, and it is divided into a total of 16 blocks, from block O to block 15.

In this case, the memory area of each block is 1 Mbyte. Basic memory access uses RASO. Further, two RAS signals each from RASI to RAS6 are output to the expansion memory slots. The 2M byte memory module uses only one RAS signal and the 4M byte memory module uses only one RAS signal.
The byte memory module uses both RAS signals. Here, the 4 MB memory module is treated as a combination of two 2 MB memory modules.

During system startup processing (IRT), register 13
Set the RAS number corresponding to each block. A value of "7" or more is stored in the register of the block where memory is not implemented.

Address signals A23-20 from the CPU are sent to the decoder 14
The data is divided into 16 blocks of IM byte units 9 to 15, and only the output of the corresponding block is valid. Upon receiving this signal, the selector 15 selects and outputs the register value of the corresponding block in the register 13. Based on the value, the decoder 16 generates a signal that makes one or less of the RAS signals valid. In other words, if the value set in the register is an existing RAS number (from "0" to 6), the corresponding signal will be enabled, and if the value is a non-existent RAS number ("7" or higher), the signal will be valid. , none of the signals becomes valid.The RAS timing signal supplied from the system is inhibited by gate 7 and output as the RAS signal corresponding to the selected block.Also, any RAS signal becomes valid. Sometimes Kate 1
8 makes the memory enable signal valid and allows the system to access the memory. That is,
When this memory enable signal is not valid, it indicates that no memory exists in that block, and the system can perform appropriate processing such as accessing an external lot.

The invention can also be implemented with other logic. FIG. 2 shows another embodiment of the invention. Here, the configurations of the expansion memory slot and RAS signal are the same as in the embodiment shown in FIG. In the figure, 21 represents 16 independent 14
R is a bit length register and is supplied to each slot.
Remember the number corresponding to the AS signal. Register value “0”
” to “6” respectively correspond to RASO to RAS6, and register values of “7” and above do not correspond to RAS signals. 22 is a decoder, and each register is One RAS signal is selected. If the RAS number is "7" or higher, the other RAS signal will not be selected. 23 is a decoder, which selects one M byte block from the upper 4 bits of the CPU address. 2
4 is a selector, which selects the RAS signal of the target block from the RAS signal set for each block for each RAS signal.
Select AS signal. A gate 25 outputs RAS timing for a selected RAS signal. 26
is a gate and indicates that memory access is performed to the block selected by the CPU address.

According to this example, the RAS signal set in the register is selected in advance for each block, and then the CPU
RAS for the block selected by address
? ≧ issues will be selected and output. This allows the CPU
This embodiment has the advantage that the time from the address to the output of the RAS timing signal is shorter by one decoder stage than in the embodiment shown in FIG. 1, and the delay time in the actual circuit configuration is reduced by two. Conversely, the circuit scale becomes larger.

FIG. 3 shows an example of memory unsealing as an application example. Expansion memory slot A is unused, a 2M byte memory module is inserted into slot B, and a 4M byte memory module is inserted into slot C. In this case, RAS3 is used to access the 2M hide memory module, and RAS5 and RAS6 are used to access the 4M byte memory module.

According to this register setting, the 2M byte memory module is accessed from the beginning of the CPU address to 2M bytes, and the 2M hide or basic memory is accessed. The 4M hide memory module is accessed from 3M bytes to 7M bytes, but the latter 2M bytes can also be accessed from the area from 14M bytes to 1.6M bytes. 1.4 from 7MB
The area up to M bytes is not accessed by any memory and is released to the external bus.

In this way, memory allocation (=J) can be specified freely.

[Effects of the Invention] As explained above, according to the present invention, the following effects can be obtained.

(1,) The correspondence between the CPU address and the basic memory installed as standard in the system or the memory installed in the expansion memory slot can be freely set.

(2) Addresses between each memory need not be consecutive.

(3) Memory modules with different capacities can be freely combined.

(4) There are no restrictions on the positions of empty slots.

(5) The hardware structure is simple.

[Brief explanation of the drawing]

FIG. 1 is a logic block diagram showing an embodiment of the present invention, FIG. 2 is a logic block diagram showing another embodiment of the present invention, and FIG. 3 is a diagram showing memory allocation as an application example. FIG. 4 is a diagram showing a combination of memory expansion shown as a conventional example. ]4 11... Basic memory, 12... Expansion memory slot, 13.21... Register, 14.16.22.23.
...Decoder, 15.24...Selector, 17.18
．． 25.26...Gate.

Claims (1)

[Claims] In addition to the standard memory installed in the system, in computers where memory can be expanded by inserting a memory card into an expansion memory slot, the CPU's address space is divided into arbitrary equal areas, and each area is divided into standard memory or memory. There are multiple independent registers in which the block number of the extended memory to be used is set, and the CP
A selector that decodes the address generated by U, selects the register of the corresponding memory block, decodes the value of the selected register, and outputs the corresponding memory selection signal. memory control device.