JPH0220039A - Evaluating method for single event resistance of semiconductor element - Google Patents

Evaluating method for single event resistance of semiconductor element

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Publication number
JPH0220039A
JPH0220039A JP63170310A JP17031088A JPH0220039A JP H0220039 A JPH0220039 A JP H0220039A JP 63170310 A JP63170310 A JP 63170310A JP 17031088 A JP17031088 A JP 17031088A JP H0220039 A JPH0220039 A JP H0220039A
Authority
JP
Japan
Prior art keywords
region
single event
charge collection
charge
energy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63170310A
Other languages
Japanese (ja)
Inventor
Kunihiko Kasama
笠間 邦彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63170310A priority Critical patent/JPH0220039A/en
Publication of JPH0220039A publication Critical patent/JPH0220039A/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To secure a region having weak single event resistance and to calculate the sectional area of a single event phenomenon due to the sum of the areas of the regions by forming the same connecting structure as that of a real element, elongating or contracting a flying stroke by ion energy change, isolating and evaluating charge collecting step. CONSTITUTION:When energy of alpha-ray is varied and radiated by regulating the vacuum degree of a vacuum chamber in which a 241Am beam source and a sample are secured, for example, to an N<+>-P bond formed on a P-type substrate and a charge collecting step is discussed, its incident energy is proportional to the charge collection amount in a region A (less than 1Mev), and a funneling step in the P-well is generated. A diffusing step in the P-well occurs in a region B, ranged at least 3mum. In a region C, the charge collection amount is reduced by half due to the ion shunt phenomenon of the N<+> type substrate. Further, one responsive region P<+>-N junction is discussed, compared with the magnitude of the charge collection amount, a region in which single event resistance is deteriorated is secured, and the sectional area of the single event phenomenon can be calculated by the sum of the areas of the regions.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子におけるシングルエベント耐性の評
価方法に関し、特にシリコン半導体素子のソフトエラー
、ラッチアップ耐性評価に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for evaluating single event resistance in a semiconductor device, and particularly to soft error and latch-up resistance evaluation of a silicon semiconductor device.

〔従来の技術〕[Conventional technology]

人工衛星に搭載される半導体集積回路は、衛星の高機能
化、高性能化に伴い、より大容量、高集積となり、従っ
てより高密度微細化の傾向にある。
Semiconductor integrated circuits mounted on artificial satellites have become larger in capacity and more highly integrated as satellites become more sophisticated and performant, and there is therefore a trend towards higher density and miniaturization.

ところが半導体素子の微細化はビット当り情報電荷量を
減少させるため荷電重粒子入射に起因するソフトエラー
、およびラッチアップ等のシングルエベントによる損傷
を受けやすい。そのため上記シングルエベント現象が宇
宙用電子機器における重大な問題として認識される様に
なっている。
However, miniaturization of semiconductor devices reduces the amount of information charge per bit, making them susceptible to damage due to soft errors caused by incidence of charged heavy particles and single events such as latch-up. Therefore, the single event phenomenon has come to be recognized as a serious problem in space electronic equipment.

次にシングルエベント現象のメカニズムについて、N”
−P接合に荷電粒子が入射したときを例にとって述べる
。第6図に電荷収集過程の時間推移を示す。第6図(a
)に示す荷電粒子入射により空乏層の電界が歪み空乏層
が実質的に伸びる(第6図(b))。すると伸長した電
界中の電荷は電界によって収集され(ファネリング過程
)、空乏層の歪は解消される。この過程は数100ピコ
秒以内で起こる高速現象であることが知られている。次
に第6図(c)に示す様にシリコン基板中に残存する電
荷(N、子および正孔)が拡散して空乏層領域に到達す
ることにより電荷収集が起こる。この過程は拡散過程と
呼ばれ荷電粒子の飛程等に依存し、数ナノ−数十ナノ秒
続く。以上述べた2つの過程、すなわちファネリング過
程と拡散過程により接合構造に電荷が収集される。この
収集された電荷量がメモリの反転あるいはラッチアップ
を生じるに充分な量あればシングルエベント現象が起こ
ることになる。
Next, regarding the mechanism of single event phenomenon, N”
An example will be described in which a charged particle is incident on a -P junction. FIG. 6 shows the time course of the charge collection process. Figure 6 (a
) The electric field in the depletion layer is distorted by the incidence of charged particles, and the depletion layer is substantially elongated (FIG. 6(b)). Then, the electric charges in the elongated electric field are collected by the electric field (funneling process), and the strain in the depletion layer is eliminated. This process is known to be a fast phenomenon that occurs within several hundred picoseconds. Next, as shown in FIG. 6(c), charges (N, electrons, and holes) remaining in the silicon substrate diffuse and reach the depletion layer region, thereby causing charge collection. This process is called a diffusion process and depends on the range of the charged particles and lasts several nanoseconds to several tens of nanoseconds. Charges are collected in the junction structure through the two processes described above, namely the funneling process and the diffusion process. If the amount of collected charge is sufficient to cause memory inversion or latch-up, a single event phenomenon will occur.

実際の半導体素子では接合の面積は小さく、拡散過程に
よる収集量は小さい。したがって実質的な電荷収集は主
にファネリング過程で生じる。
In actual semiconductor devices, the area of the junction is small, and the amount collected by the diffusion process is small. Therefore, substantial charge collection occurs primarily during the funneling process.

本発明で述べる様な半導体素子のシングルエベント耐性
の評価法の確立は実際に衛星搭載の可否を決定するため
にも、また耐性強化法の検討の上からも重要である。
Establishment of a method for evaluating the single event resistance of semiconductor devices as described in the present invention is important both for determining whether or not to actually mount a semiconductor device on a satellite, and for considering methods for enhancing resistance.

従来、シングルエベント耐性評価は実際の半導体素子に
加速器等により放出される荷電粒子を照射し、反転した
メモリー数を観測することにより行なわれていた。この
方法は個々の衛星搭載用素子の最終評価に必須の手続き
であるが反面、素子内部で生じる機構、すなわちファネ
リングや拡散による電荷収集過程に関する情報は得られ
ない。
Conventionally, single-event resistance evaluation has been performed by irradiating an actual semiconductor device with charged particles emitted by an accelerator or the like and observing the number of memory inversions. Although this method is an essential procedure for the final evaluation of each individual satellite-mounted device, it does not provide information about the mechanisms that occur inside the device, that is, the charge collection process due to funneling or diffusion.

そのため素子内部の電荷収集過程を検討するため実際の
素子を模擬した接合構造を形成し、収集電荷量を観測す
ることにより、シングルエベント現象機構の検討が行な
われている。
Therefore, in order to study the charge collection process inside the device, the single event phenomenon mechanism is being investigated by forming a junction structure that simulates an actual device and observing the amount of collected charge.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の接合構造を用いた評価方法は、拡散過程
による電荷収集過程を減少させるために接合面積を小さ
くすると接合に入射する荷電粒子が大幅に減少するため
観測に多大の時間を要するという欠点がある。そのため
100μmX100μm以上の比較的広い面積の接合が
用いられるが、この場合はファネリング過程と拡散過程
の2成分の寄与がある。
The conventional evaluation method using the junction structure described above has the disadvantage that when the junction area is made smaller in order to reduce the charge collection process due to the diffusion process, the number of charged particles incident on the junction is significantly reduced, which requires a large amount of time for observation. There is. Therefore, a junction with a relatively large area of 100 μm×100 μm or more is used, but in this case, two components, the funneling process and the diffusion process, contribute.

この2つの過程の分離のため電荷収集量の時間変化を調
べ、速い成分なファネリング過程、遅い成分を拡散過程
と分離することが試みられている。
In order to separate these two processes, attempts have been made to examine the temporal changes in the amount of charge collected and to separate the fast component from the funneling process and the slow component from the diffusion process.

しかしながらファネリング現象は高速(数100ピコ秒
程度)現象であり、その時間および電荷量の測定値の信
頼性は低い。また測定装置も高速現象を追跡するため高
価なものになる。
However, the funneling phenomenon is a fast phenomenon (on the order of several hundred picoseconds), and the reliability of the measured values of the time and amount of charge is low. Furthermore, the measuring equipment becomes expensive because it tracks high-speed phenomena.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のシングルエベント耐性の評価法は入射粒子のエ
ネルギーと飛程を変化させつつ、接合に収集される総電
荷量を精度の優れた波高分析測定系により評価すること
により、電荷収集過程を分離するものである。
The single-event resistance evaluation method of the present invention separates the charge collection process by varying the energy and range of the incident particle and evaluating the total amount of charge collected on the junction using a highly accurate pulse height analysis measurement system. It is something to do.

すなわち荷電粒子のエネルギーが小さく、その飛程がフ
ァネリング長より短い領域では、電荷収集はファネリン
グ過程のみによって生じ、入射エネルギーと電荷収集量
は比例する。さらにエネルギーが増大し、ファネリング
長より飛程が長くなると、電荷収集の一部は拡散によっ
て起こる。但し拡散過程による収集はファネリング過程
に比較し、その効率は低い。したがって入射エネルギー
に対し電荷収集量は比例せずしだいに傾きは減少する。
That is, in a region where the energy of charged particles is small and their range is shorter than the funneling length, charge collection occurs only by the funneling process, and the incident energy and the amount of charge collection are proportional. As the energy increases further and the range becomes longer than the funneling length, some of the charge collection occurs by diffusion. However, collection through the diffusion process is less efficient than the funneling process. Therefore, the amount of charge collected is not proportional to the incident energy, and the slope gradually decreases.

さらにエネルギーを増大させて、電荷収集の生じない深
さまで粒子が達するとイオンエネルギーを増加させても
ほとんど収集電荷量は増大しない。
If the energy is further increased and the particles reach a depth where no charge collection occurs, the amount of collected charge will hardly increase even if the ion energy is increased.

以上の様にイオンエネルギー変化によって飛程を伸縮さ
せることにより、3つの領域、すなわちファネリング過
程の生じる領域、拡散過程の生じる領域、電荷収集の起
こらない領域を分離することができる。
By expanding and contracting the range by changing the ion energy as described above, it is possible to separate three regions, namely, a region where a funneling process occurs, a region where a diffusion process occurs, and a region where no charge collection occurs.

さらに実素子の接合構造と同じ接合構造を形成して、上
記方法で電荷収集過程を分離評価すればシングルエベン
ト耐性の弱い領域の固定、およびその領域の面積和より
シングルエベント現象の断面積を導出することが可能と
なる。
Furthermore, by forming a junction structure that is the same as that of the actual device and separately evaluating the charge collection process using the above method, it is possible to fix the region with weak single event resistance and derive the cross-sectional area of the single event phenomenon from the sum of the areas of that region. It becomes possible to do so.

〔実施例〕 次に、本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の結果を示したものである。FIG. 1 shows the results of one embodiment of the present invention.

P型基板(不純物濃度5 X 1015cm−’)に作
製したN”−P接合(面積500μmX500μm)に
α線に照射して収集された電荷量を観測したものである
。ここで用いたα線はアメリシウム241 (241A
m)より放出された荷電粒子で初期エネルギーは約5.
5 M e V、飛程はおよそ33μmである。α線の
イオンエネルギーは例えば241Am線源と試料を固定
する真空室の真空度を調節することにより任意に変える
ことができる。
An N''-P junction (area 500 μm x 500 μm) fabricated on a P-type substrate (impurity concentration 5 x 1015 cm-') was irradiated with alpha rays and the amount of charge collected was observed.The alpha rays used here were Americium 241 (241A
The initial energy of the charged particles emitted from m) is approximately 5.
5 M e V, range is approximately 33 μm. The ion energy of the α rays can be arbitrarily changed, for example, by adjusting the degree of vacuum in the vacuum chamber in which the 241 Am ray source and the sample are fixed.

第2図に入射したα線(エネルギー5.5MeV)がエ
ネルギーを失う様子とそとストツピングパワー値(単位
長さ当り失うエネルギー値)を示した。
Figure 2 shows how the incident alpha rays (energy 5.5 MeV) lose energy and the stopping power value (energy lost per unit length).

さらにエネルギーの小さいα線の飛程は横軸の原点を所
定のα線のエネルギー値まで異動することによって、求
めることができる。α線のエネルギーが減少するにつれ
てストツピングパワー値が増加するのがわかる。
Furthermore, the range of α-rays with lower energy can be determined by moving the origin of the horizontal axis to a predetermined α-ray energy value. It can be seen that the stopping power value increases as the energy of the α-ray decreases.

第1図に示すように電荷収集は3つの領域I。As shown in FIG. 1, charge collection is performed in three regions I.

■、■に分割できる。領域Iはファネリング過程のみが
生じている領域で入射エネルギーと電荷収集量が比例し
、その傾きは0.9である。したがってファネリング長
に生じた電子−正孔対のほとんどが接合電極に収集され
ている。この領域の最大入射エネルギー値1.8〜2.
0 M e Vよりファネリング長は7.0〜8,0μ
m程度と求められる。領域■はファネリング過程と拡散
過程がともに生じている領域で入射エネルギー値〜3.
75MeVより拡散成分の生じる領域が〜17μm程度
まで伸びていると考えられる。さらに領域mは電荷収集
過程にほとんど影習を与えない領域で17〜33μmの
飛程に相当する。
It can be divided into ■ and ■. Region I is a region where only the funneling process occurs, and the incident energy and the amount of charge collection are proportional, and the slope thereof is 0.9. Therefore, most of the electron-hole pairs generated in the funneling length are collected at the junction electrode. The maximum incident energy value in this region is 1.8-2.
Funneling length is 7.0~8.0μ from 0 M e V
It is expected to be about m. Region ■ is a region where both the funneling process and the diffusion process occur, and the incident energy value is ~3.
It is thought that the region where the diffusion component occurs extends to about 17 μm from 75 MeV. Further, region m is a region that hardly affects the charge collection process and corresponds to a range of 17 to 33 μm.

以上の様に本方法を用いることによりN”−P接合によ
る電荷収集機構を容易に分離することが可能となる。
As described above, by using this method, it becomes possible to easily separate the charge collection mechanism based on the N''-P junction.

次に本発明の評価法を0MO8SRAMを模擬した構造
に適用してみる。第3図にCMO8SRAMのセル部と
感応領域の位置、第4図に0MO8)ランジスタの断面
構造の一例を示す。
Next, the evaluation method of the present invention will be applied to a structure simulating a 0MO8SRAM. FIG. 3 shows the positions of the cell portion and sensitive region of a CMO8SRAM, and FIG. 4 shows an example of the cross-sectional structure of a MO8) transistor.

第4図に示す位置(Nチャンネルトランジスタのドレイ
ン部)に入射したα線による電荷収集過程を検討した結
果を第5図に示す。
FIG. 5 shows the results of examining the charge collection process due to α rays incident on the position shown in FIG. 4 (the drain portion of the N-channel transistor).

領域は3つの部分に分割される。すなわち領域A(〜I
MeV)では入射エネルギーと電荷収集量が比例する。
The area is divided into three parts. That is, area A (~I
MeV), the incident energy and the amount of charge collection are proportional.

したがってPウェル部でのファネリング過程が生じてい
ることがわかる(ファネリング長〜3μm)。領域Bは
Pウェル中での拡散過程の起こる領域と考えられ、その
範囲は3〜5μmと考えられる。領域Cでは電荷収集量
が急激に減少し、電荷収集量が半減する。これはN+基
板とのイオンシャント現象(軌跡に沿って生じた電子−
正孔対を2つのN+領領域分割する現象)が生じている
ためである。
Therefore, it can be seen that a funneling process occurs in the P-well portion (funneling length ~3 μm). Region B is considered to be a region where the diffusion process in the P-well occurs, and its range is thought to be 3 to 5 μm. In region C, the amount of charge collection decreases rapidly, and the amount of charge collection is halved. This is due to the ion shunt phenomenon (electrons generated along the trajectory) with the N+ substrate.
This is because a phenomenon in which a hole pair is divided into two N+ regions has occurred.

以上の様にα線のエネルギーを変化させて電荷収集量を
観測することによって電荷収集機構を分割することがで
きる。
As described above, the charge collection mechanism can be divided by changing the energy of the α ray and observing the amount of charge collection.

さらにもう一方の感応領域P”−N接合(P+/Nウェ
ル/Nエピ/N+基板構造)を検討することにより電荷
収集量の大小を比較し、シングルエベント耐性の劣る領
域を固定することができる。
Furthermore, by considering the other sensitive region P''-N junction (P+/N well/N epi/N+ substrate structure), it is possible to compare the amount of charge collection and fix the region with poor single event resistance. .

また、その領域の面積和によりシングルエベント現象の
断面積を導出できる。
Furthermore, the cross-sectional area of the single event phenomenon can be derived from the area sum of the area.

また上記各実施例いずれもα線を入射したものであるが
、他の荷電粒子を用いても同様の手法を実施できる。そ
の際イオンエネルギーの変化は反応室の真空度、他ガス
の導入、金属薄膜によるじゃ閉等で行うことができる。
Further, although each of the above embodiments uses α rays, the same method can be implemented using other charged particles. At this time, the ion energy can be changed by adjusting the vacuum level of the reaction chamber, introducing other gases, closing the reaction chamber with a thin metal film, etc.

〔発明の効果〕〔Effect of the invention〕

以上、説明したように本発明は荷電粒子のイオンエネル
ギーを変動させてイオンの飛程を伸縮し、実素子を模擬
した接合構造による電荷収集を観測することにより、電
荷収集機構を分離して評価できるという効果がある。
As explained above, the present invention expands and contracts the range of ions by varying the ion energy of charged particles, and by observing charge collection by a junction structure that simulates a real device, the charge collection mechanism is isolated and evaluated. There is an effect that it can be done.

その結果シングルエベントに弱い領域を固定することが
可能となり、さらにその面積の和を求めることにより断
面積を予測することが可能となる。
As a result, it becomes possible to fix a region that is vulnerable to a single event, and furthermore, it becomes possible to predict the cross-sectional area by calculating the sum of the areas.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の結果によるα線入射エネル
ギーと電荷収集量との関係を示すグラフである。 領域I・・・・・・ファネリング過程の生じる領域、領
域ト・・・・・拡散過程の生じる領域、領域■・・・・
・・電荷収集量の少ない領域。 第2図はα線のイオンエネルギーの減衰とストツピング
パワーの変化を示すグラフである。 第3図は0MO3SRAMの等価回路図、第4図は0M
O8)ランジスタへの荷電粒子入射を模式的に示した図
である。 第5図は0MO3)ランジスタ構造を模擬した接合構造
へα線が入射した際の入射エネルギーと電荷収集量の関
係を示したグラフである。 領域A・・・・・・Pウェル領域のファネリング過程の
生じる領域、領域B・・・・・・Pウェル領域での拡散
過程の生じる領域、領域C・・・・・・基板N+領領域
のイオンシャント(電子−正孔対の分割)現象の生じる
領域。 第6図(a)〜(c)は荷電粒子入射による電荷収集過
程を示す模式図である。 代理人 弁理士  内 原   音 区壬iのヌトッピシ2′八゛ワ (MeVβC) 聾           N (A aH)−、ビl責丁′ン未ω)Ac<徨の入射エ
ネルN′− (、’4e:V) 第3図 第4図 メ系欠の入射エネノーー(MeV) 第5困
FIG. 1 is a graph showing the relationship between the incident energy of α-rays and the amount of charge collected according to an embodiment of the present invention. Area I: Area where the funneling process occurs, Area I: Area where the diffusion process occurs, Area ■...
...A region with a small amount of charge collection. FIG. 2 is a graph showing the attenuation of the ion energy of α rays and the change in stopping power. Figure 3 is an equivalent circuit diagram of 0MO3SRAM, Figure 4 is 0M
O8) is a diagram schematically showing the incidence of charged particles on a transistor. FIG. 5 is a graph showing the relationship between incident energy and charge collection amount when α rays are incident on a junction structure simulating a 0MO3) transistor structure. Region A: region where the funneling process occurs in the P-well region, region B: region where the diffusion process occurs in the P-well region, region C: region of the substrate N+ region. A region where the ion shunt (splitting of electron-hole pairs) phenomenon occurs. FIGS. 6(a) to 6(c) are schematic diagrams showing the charge collection process due to the incidence of charged particles. Agent Patent Attorney Uchihara Uchihara Otoku I's Nutopisi 2' 8゛wa (MeVβC) Deaf N (A aH)-, Bill's responsibility ding'n ω) Ac < the incident energy N'- (,'4e :V) Figure 3 Figure 4 Incident energy without MeV (MeV) 5th problem

Claims (2)

【特許請求の範囲】[Claims] (1)半導体素子のシングルエベント耐性評価において
、半導体素子を模擬した接合構造に、荷電粒子を該荷電
粒子のエネルギーと半導体内での飛程を変化させて照射
し収集される電荷量を計測することを特徴とする半導体
素子におけるシングルエベント耐性の評価方法。
(1) In single event resistance evaluation of semiconductor devices, a junction structure simulating a semiconductor device is irradiated with charged particles while changing the energy and range of the charged particles within the semiconductor, and the amount of charge collected is measured. A method for evaluating single event resistance in a semiconductor device, characterized in that:
(2)請求項1の電荷量計測により電荷収集過程の機構
を分離評価し、半導体素子のシングルエベント耐性とシ
ングルエベント発生断面積を導出することを特徴とする
半導体素子におけるシングルエベント耐性の評価方法。
(2) A method for evaluating single event resistance in a semiconductor device, characterized in that the mechanism of the charge collection process is separately evaluated by measuring the amount of charge according to claim 1, and the single event resistance and single event generation cross section of the semiconductor device are derived. .
JP63170310A 1988-07-07 1988-07-07 Evaluating method for single event resistance of semiconductor element Pending JPH0220039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63170310A JPH0220039A (en) 1988-07-07 1988-07-07 Evaluating method for single event resistance of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63170310A JPH0220039A (en) 1988-07-07 1988-07-07 Evaluating method for single event resistance of semiconductor element

Publications (1)

Publication Number Publication Date
JPH0220039A true JPH0220039A (en) 1990-01-23

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP63170310A Pending JPH0220039A (en) 1988-07-07 1988-07-07 Evaluating method for single event resistance of semiconductor element

Country Status (1)

Country Link
JP (1) JPH0220039A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7200825B2 (en) 2004-08-27 2007-04-03 International Business Machines Corporation Methodology of quantification of transmission probability for minority carrier collection in a semiconductor chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7200825B2 (en) 2004-08-27 2007-04-03 International Business Machines Corporation Methodology of quantification of transmission probability for minority carrier collection in a semiconductor chip

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