JPH02199946A - High-speed packet switching equipment - Google Patents

Abstract

PURPOSE:To reduce the cost of a packet switchboard of a bus matrix type and to improve reliability by arranging buffer memories corresponding to the outputs of a bus matrix section. CONSTITUTION:Packet output common memory circuits (50-1)-(50-n) are con nected to a first-in first-out buffer connecting to each output bus to increase the transfer speed of the output buses of a bus matrix section between output buses (42-1)-(42-n) of the bus matrix section 40 and output traffic transfer control circuits (60-1)-(60-n). The capacity of (number of input buses of the bus matrix section 40 X maximum packet length) is required for the memory capacity of a memory circuit 50, but the capacity of each buffer being the component of the bus matrix section 40 is enough to be the capacity of maximum packet length, and not only the number of input buses needs not be taken into account but also one common memory circuit is enough at every output bus.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of a bus matrix type packet switching device, the price of the packet switching device is reduced by reducing the memory capacity of the first-in, first-out buffer arranged at grid points on the bus matrix. For the purpose of reducing the number of packets and improving reliability, a bus matrix in which input/output buses are arranged in a grid is used to transfer packets from each of multiple transmit buffer circuits connected to each of multiple input packet transfer buses. A bus matrix type packet switching device for transferring packets to any one of a plurality of receiving buffer circuits connected to each of a plurality of output packet transfer buses via a section, the input packet transfer bus and an input of the bus matrix section. a plurality of input traffic transfer circuit control units that are connected between the bus and control the input buses of the bus matrix unit based on packets from the transmission buffer circuit;
a plurality of exchange buffer circuits connected between the input bus and the output bus of the bus matrix section; a plurality of output traffic transfer circuits that control output packet transfer buses, and prevents packets from being accumulated in the exchange buffer circuit between the output bus of the bus matrix unit and the input of the output traffic transfer circuit. Common memory circuits are arranged to prevent this.

[Industrial application field]

The present invention relates to an improvement in a bus matrix type packet switching device.

As a background to the present invention, a packet switching device as shown in FIG.
No. 29, filed February 14, 1985, Japanese Patent Application Laid-Open No. 1983-2165
(See No. 45 “High-speed Packet Switching System”).

In FIG. 10, a plurality of input packet transfer buses 21-
1.21-2. ...,. The packets from each of the plurality of transmission buffer circuits 20 connected to each of the transmission buffer circuits 21-n,
Bus matrix section 1 in which input/output buses are arranged in a grid pattern
bus matrix type packet exchange for transferring the packets to any one of the plurality of receiving buffer circuits 70 connected to each of the plurality of output packet transfer buses 71-1, 7L-2, . . . , 71-n via the bus 00. Equipment is shown.

Input packet transfer bus 21-1.21-2. ...,.
21-n and the input bus of the bus matrix section 100, an input bus tot-i of the bus matrix section 100 is connected based on the packet from the first transmission buffer circuit 20.
A plurality of human-powered traffic transfer control circuits 3-1 to 3-n are connected to control the traffic transfer control circuits 3-1 to 101n.

In the bus matrix section 100, an input bus 101-1
A plurality of exchange buffer circuits 11-1.11-2.~101-n and the output buses 102-1~102-n.・・・
...In-n is connected.

The output bus of the bus matrix section 100 includes exchange buffer circuits 11-1, 11-2.・・・・・・In-n
a plurality of output traffic transfer control circuits 6-1.6- controlling the output packet transfer bus based on packets from the
2°...6-n is connected.

The packets accumulated in the transmission buffer circuit 20 and transferred from the input packet transfer bus 21-4 (i-1, 2, . . . n) are transferred to the input traffic transfer control circuit 3-i.
exchange buffer circuit 11-1.11
-2°---An-n, the packet is stored in a desired receiving buffer circuit 70, and sent to the corresponding output packet transfer bus 71-j.

In this kind of packet switching device, an exchange buffer circuit 11-1.11 constituting the bus matrix unit lOO
-2. Since the number of In-n increases in proportion to the product of the number of input buses and the number of output buses, it is desirable that the memory capacity of each exchange buffer circuit be as small as possible.

[Conventional technology]

In FIG. 10, input buses 101-1, 101-2 . ...,. Packets are input from 101-n, and these are sent to the output bus 102-n, for example.
Buffers 11-j, 12-j, etc. connected to j
. . , In-j, there is a limit to the allowable transfer speed of the output bus 102-j, so conventionally, the buffers 11-1, 11-2, .・・・
The capacity of each buffer in -n is increased to increase the amount of packets stored in each buffer in the bus matrix section 100, and the packets are sequentially sent out according to the allowable transfer speed of the output bus.

[Problem to be solved by the invention]

According to the above conventional method, in order to prevent discarding of packets due to unbalanced traffic, the bus matrix section l
Buffers 11-1, 11-2゜ that make up OO...
...The capacity of each of 1n-n must be increased. This is because it is not known on which output bus the concentration of output packets will occur. Generally, if the number of output buses is 0 and the packet length is ■, each first-in first-out buffer requires a capacity corresponding to nXV. For example, if the number of output buses is 3 and the packet length is 4 bytes, each of the buffers 11-1.11-2°-...+In-n is 12 bytes.
This requires a capacity of 20 bytes, and considering the margin, the capacity becomes 20 bytes.

Moreover, the large-capacity buffers must be distributed at all grid points.

In this way, the need for a large capacity buffer means that
This means that the circuit scale of the bus matrix section 100 has to be increased, which causes problems in that the cost of the device is high and the reliability of the device is low.

SUMMARY OF THE INVENTION In view of the above problems in the prior art, an object of the present invention is to increase the transfer speed of an output bus of a bus matrix unit by connecting a bus between the output bus and an output traffic transfer circuit. Based on the concept of arranging a common memory in the first-out buffer, we reduced the circuit scale of the bus matrix section in bus matrix type packet switching equipment, thereby reducing the cost of the equipment and improving reliability. be.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. In the figure, 40 is a bus matrix section, l-1 to n-n are exchange buffer circuits arranged at grid points of the bus matrix section 40, and 41-1 to 41-n are bus matrix sections 40.
42-1 to 42-n are output buses of the bus matrix unit 40, 21-1 to 21-n are a plurality of input packet transfer buses, 71-1 to 71-n are a plurality of output packet transfer buses, 20-H to 20-1, 20-21 to 20
-1! .......

20-nl-20-nm is the input packet transfer bus 21
A plurality of transmission buffer circuits are connected to each of -1 to 21-n, and 70-21 to 70-2 are connected to 70-11 to 70-1.
f..., 70-nl to 70nm are transmission buffer circuits connected to each of the output packet transfer buses 71 to 1 to 71-n, and 30-1 to 30-n are the input packet transfer buses 21 -1 to 21-n are input traffic transfer control circuits, and 60-1 to 60-n are output traffic transfer control circuits connected to output packet transfer buses 71-1 to 71-n. According to the present invention, the memory capacity of each of the exchange buffer circuits 1-1 to n-n is an amount that does not depend on the number of input buses, and the memory capacity of each of the exchange buffer circuits 1-1 to n-n is an amount that does not depend on the number of input buses, and Between the control circuits 60-1 to 60n, packet output common memory circuits 50-1 to 50-n are connected to first-in, first-out buffers connected to each output bus in order to increase the transfer speed of the output buses of the bus matrix section. It is connected.

[Effect]

Output buses 42-1 to 42-n of bus matrix section 40
The transfer speed is the packet output common memory circuit 50-1 to 50-5.
By setting 0n, the speed can be increased. Therefore, the exchange buffer circuits 1-1 to nn can output packets at high speed. Therefore, even if traffic is concentrated on one output bus, the exchange buffer circuit 1
There is no need to store extra packets in -1 to nn as in the conventional case. Instead, packets input at high speed to the packet output common memory circuits 50-1 to 50-n are accumulated there, and the output packet transfer buses 71-1 to 71
The data is output sequentially at a transfer rate of -n.

〔Example〕

Below, the configuration of each part in the block diagram of FIG. 1 and one buffer 20- connected to the input packet transfer bus 21-1 will be explained.
if, passes through the input traffic transfer control circuit 30-1, the replacement bar latch circuit i-j in the bus matrix unit 40, and passes from the packet output common memory circuit 50-j to the output traffic transfer control circuit 60-j. The flow of packet transfer to one reception buffer circuit 70-jl connected to the output packet transfer bus 71-j will be sequentially explained.

FIG. 2 is a block diagram showing the configuration of the transmission buffer circuit 20-il. In the figure, 201 is a transmission line code decoding circuit, 202 is a packet delimiter detection circuit, and 203 is a 1
a packet delay circuit; 204 is an address check circuit;
05 is a packet transfer timing generation circuit, 206 is a packet presence/absence notification circuit, and 207 is an amplifier.

Input packets sent from the transmission line are sent to the transmission line code decoding circuit 201 at the input stage of the transmission buffer 20-if.
When the packet delimiter detection circuit 202 detects the end of one packet, a one-packet end signal is given to the packet presence/absence notification circuit 206, and the input traffic transfer control circuit 30-1 is notified in advance. On the other hand, the input packet is input to the 1-packet node delay circuit 203,
It is output according to the transfer timing from the packet transfer timing generation circuit 205. When the address specification from the input traffic transfer control circuit 30-1 matches the address of this transmission buffer 20-il, the address check circuit 204 enables the amplifier 207, so that the packet presence signal and the output packet are transferred to the input traffic transfer control circuit. The signal is sent to circuit 30-1. This method of monitoring address matching is called the address filtering method.

FIG. 3 shows the input traffic transfer control circuit 30- of FIG.
1 to 30-n (for example, 30-i); FIG. In the figure, 301 is an LCN memory, which stores one address (hereinafter also referred to as FIFO-B address) of buffers l-1 to n-n in the bus matrix unit 40 and a new address according to the designation of an input address. L
CN (Logical Channel Number)
number and output traffic transfer control circuit 60-1.60
-2. ...,. One address of 60-n (hereinafter referred to as FI
(also referred to as FO-C address), 30
2 is an address generation circuit that generates an address for the transmission buffer 20-il connected to the manual packet transfer bus 21-1, 303 is a packet presence/absence detection circuit, 304 is a timing generation circuit, 305 is a latch circuit, and 306 is a delay circuit. , 307.308 is an enable circuit, 309.31
0 is an amplifier.

The packet presence/absence detection circuit 303 connects the plurality of transmission buffers 20-i1 to 20 via the input packet transfer bus 21-1.
-Detect the packet presence/absence signal sent from ix.

When a packet presence signal is detected, address generation circuit 3
02, thereby selecting the highest priority transmission buffer, for example 20-il, from among the transmission buffers y20-i1 to 20-ix (hereinafter also referred to as FIFO-A), and performing the selected transmission. The address specifying the buffer 20-il is the address generation circuit 30.
At the same time, a packet transfer permission signal is sent from the packet presence detection circuit 303. Transmission buffer 2 that matches the address from address generation circuit 302
A data packet is sent from 0-il in response to a packet transfer permission signal, and is sent to delay circuit 3 via amplifier 309.
06 is input. Send buffer 2 other than address specification
0-i2 to 20-4x ignore the packet transfer permission signal. Therefore, the addressed transmit buffer 20-i
Only 1 recognizes the packet transfer permission signal and sends the packet to the input packet transfer bus 21-1 in response to the signal.

The packet transferred through the input packet transfer bus 21-1 is received by the delay circuit 306, and the LCN (Logical Channel) in the packet header of the packet is received by the delay circuit 306.
LCN memory 30 using l Number) as the address.
1 is searched for, and buffers 1-1 to nn (hereinafter FIFO) in the bus matrix section 40 are searched for.
-B), and output traffic transfer control circuits 60-1 to 60.
One corresponding address and new LCN are selected from n (hereinafter also referred to as POFO-C).

FIG. 8 shows the structure of the destination table in the LCN memory 301. As shown in the figure, the input address part of the destination table is the input port number (FIFO-A number) and the input LC
The output data section consists of a FIFO-B number, a FIFO-C number, a new LCN number, and a control section, and the output data section is made up of the input port number and input LCN number as keys. Search each data.

Returning to FIG. 3 again, the timing generation circuit 304 receives the packet presence detection notification signal from the packet presence/absence detection circuit 303, provides an address latch clock to the latch circuit 305, monitors input packet data, and outputs the packet header section. Detecting the end signal of the amplifier 307 disables the amplifier 307 and enables the enable circuit 308. As a result, a new LCN and FIFO-C address are added to the header portion of the packet output from the amplifier 310 in place of the old LCN. Further, the address of FIFO-8 is sent from the latch circuit 305. Furthermore, the timing generation circuit 304 sends out a packet transfer start signal after a predetermined time from detection of the end signal of the packet header section.

FIG. 4 is a block diagram showing the configuration of one of the first-in, first-out buffers 1-1=nn (for example, 1-j) in the bus matrix unit 40. In the figure, 401 is a memory circuit with a capacity of several kilobytes, which is several times the maximum packet length, 402 is an accumulation counter that counts the number of packets or bytes, 403 is an input packet address generation circuit, and 404 is an output Packet address generation circuit section, 405
．． 406 is an address check circuit, 407 is an output timing generation circuit, and 408, 409, and 410 are amplifiers. As will become clear later, in principle, the memory capacity of the memory circuit 401 only needs to be equal to the packet length.

Address check circuit 405 compares the designated address sent from latch circuit 305 (FIG. 3) in input traffic transfer control circuit 30-1 with its own address, and if they match, enables amplifier 408. If there is a mismatch, amplifier 408 is kept disabled. The enabled amplifier 408 supplies the packet transfer start signal from the timing generation circuit 304 (FIG. 3) to the address generation circuit section 403 for the input packet, and also sends the packet transfer start signal to the input packet address generation circuit section 403, and in synchronization with this packet transfer start signal, the amplifier 310
The input packet transferred from the memory circuit 401 is stored in the memory circuit 401. A storage counter 402 counts the number of packets or bytes of a plurality of packets stored in the memory circuit 401. The reason why two types of byte number counters and packet number counters are provided is that when outputting at the same transfer rate as the transfer rate of packets input to the memory circuit 401, it is possible to count and output the number of bytes. This is because when outputting at an integral multiple of the transfer rate of packets input to the memory circuit 401, it is preferable to count and output the number of packets. When the value of this accumulation counter 402 exceeds a predetermined value set in advance, the accumulation counter 402 generates a packet present signal.

Packet output common memory circuits 50-1 to 50-5 connected to the output side of the bus matrix unit 40 (FIFO-B)
The address signal of the corresponding buffer l-j+2-J+-0-+n-J is cyclically outputted from the corresponding one of 0-n (50-D).This address signal is output by the address check circuit 406. If there is a match, amplifier 409 is enabled and the packet present signal is sent to the corresponding packet output common memory circuit 50-i via output bus 42-j.

FIG. 5 shows packet output common memory circuits 50-1 to 50-.
FIG. 2 is a block diagram showing the configuration of one (for example, 50-j) of n. In the figure, 501 is a large capacity memory circuit of several hundred kilobytes, 502 is an accumulation counter that counts the number of packets or bytes, 503 is an input packet address generation circuit, 504 is an output packet address generation circuit, and 505 is a packet Withdrawal timing generation circuit, 5
06 is a packet transfer timing generation circuit, 507 is a packet-traffic counter circuit, and 508 and 509 are amplifiers. The memory capacity of the memory circuit 501 is as follows:
The number of input buses of the bus matrix section 40 x maximum packet length is required, but the capacity of each buffer configuring the bus matrix section 40 is not only the maximum packet length, but also the number of input buses does not need to be considered. Since only one common memory circuit is required for each output bus, the overall memory capacity can be significantly reduced compared to the conventional method.

The packet presence signal sent from each accumulation counter 402 of the buffers 1-j+2-J+-0+n-J via the amplifier 409 is sent to the packet output common memory circuit shown in FIG. 5 via the output bus 42-j. It is given to the packet extraction timing generation circuit 505 in 50-j. On the other hand, the packet extraction timing generation circuit 505 is a bus matrix, and the exchange buffer circuits 1-j and 2-j are connected to the output bus 421 of the Tx unit 40.

6. -+n-J address signals are generated cyclically, and these address signals are sent to the address check circuit 406 in the bus matrix section 40.

The packet extraction timing generation circuit 505 that receives the packet presence signal sends a packet transfer permission signal to the bus matrix section 40 (FIG. 4) at a predetermined timing. In the bus matrix section 40, when the addresses match in the address check circuit 406, this packet transfer permission signal is sent to the amplifier 410 and the output timing generation circuit 40.
7 to the output packet address generation circuit 404, and thereby the output packet address generation circuit 404
accesses the memory circuit 401 and reads the output packet. The read output packet is stored as an input packet in the memory circuit 501 via the amplifier 508 in FIG. Packet extraction timing generation circuit 505
At this time, activates the packet extraction timing generation circuit 505 and provides the input address to the memory circuit 501. LCN address and FIFO from header part of input packet
The -C address is extracted and input to the packet traffic counter circuit 507, and the cumulative value up to now is counted for each LCN in each first-in, first-out buffer unit. Further, the input packet end signal is input to an accumulation counter 502, which counts the amount of packets accumulated in the internal memory circuit 501 in units of packets or in units of bytes. Furthermore, the input packet end signal is sent to the packet traffic counter circuit 5.
07, and the accumulated amount corresponding to the number of buffers connected to the corresponding output bus 42-j is also counted.

When the accumulation counter 502 counts a predetermined number of packets or bytes, it outputs a packet presence signal indicating that packets are being accumulated to the output traffic transfer control circuit 60-j.

FIG. 6 is a block diagram showing the configuration of the output traffic transfer control circuit 60-j. In the figure, 601 is a packet presence/absence detection circuit, 602 is a timing generation circuit, and 60 is a timing generation circuit.
3 is a delay circuit, 604 is an address generation circuit, 605, 6
06 is an amplifier.

When the packet presence detection circuit 601 receives the packet presence signal from the accumulation counter 502, after confirming that the Motoyama Kadra traffic control circuit 60-j is in a receivable state, the packet presence detection circuit 601 detects the output traffic transfer control circuit 60-j.
j packet transfer timing generation circuit 506 (Figure 5)
A packet transfer permission signal is sent to the In response to this signal, the packet transfer timing generation circuit 506 activates the output packet address generation circuit 504, thereby providing the memory circuit 501 with a read address indicating the beginning of the wait state. As a result, the output packet is read from the memory circuit 501 and input to the delay circuit 603 via the amplifier 509 and the amplifier 605 in the output traffic transfer control circuit 60-j. Next, the address of FIFO-C is extracted from the header part of the packet input to the delay circuit 605, and the address is sent to the address generation circuit 604 according to the latch timing generated by the timing generation circuit 602.
, and address FIFO-C with that value. At the same time, the timing generation circuit 602 notifies the FIFO-C of a packet transfer start signal.

FIG. 7 is a block diagram showing the configuration of one of the receiving buffers 70-11-70-nm, for example 7O-jl. In the figure, 701 is a transmission path encoding circuit;
2 is a packet delimiter insertion circuit, 703 is a transmission path waiting packet accumulation buffer circuit, 704 is an address check circuit, 705 is a packet transfer permission timing generation circuit, 70
6 is an amplifier.

When the address specification from the address generation circuit 604 in the output traffic transfer control circuit 60-j matches its own reception buffer address, the amplifier 706 is enabled, and the packet transfer start signal and output from the output traffic transfer control circuit 60-j are activated. The packets are input to a packet transfer permission timing generation circuit 705 and a transmission waiting packet accumulation buffer circuit 703, respectively. The packet transfer permission timing generation circuit 705 receives the packet transfer start signal and provides a packet transfer permission signal to the transmission waiting packet accumulation buffer circuit 703 at an appropriate timing.

The transmission waiting packet accumulation buffer circuit 703 that received this
outputs packets sequentially. The packet delimiter insertion circuit 702 receives the packet output from the transmission waiting packet accumulation buffer circuit 703 and sends a signal indicating the delimitation of the packet to the transmission path encoding circuit 701.

The transmission line encoding circuit 701 converts the input packet into a form corresponding to the transmission line and outputs the packet into the output packet transfer frame 1.
- Send to j.

FIGS. 9(a) to 9(e) are diagrams showing the format of packets flowing through each transmission path.

FIG. 9(a) shows the packet format on the input packet transfer bus 21-1, and as shown in the figure, a header section containing an LCN number is added to the beginning of each received data.

FIG. 9 shows the input bus 4 of the bus matrix section 40.
11 and output bus 42-j, and as shown in the figure, there is a FIFO-C at the beginning of each packet.
A number and a new LCN number are added.

FIG. 9(C) shows the output traffic transfer control circuit 60-j.
and the reception buffer circuit 7O-jx, and as shown in the figure, the header part is the new L
It is a CN number.

FIG. 9(d) shows the packet format on the transmission path, in which a new LCN number is added to the header part, and a code such as a frame check sequence (FCS) is added after the data part.

Transmission buffer circuit 20- in the above embodiment of the present invention
11-20-nm, replacement buffer circuit 1-1-n-n
.

And the receiving buffer circuits 70-11 to 70-nm can be realized by first-in first-out buffer circuits.

There are the following two methods for constraining the output buses 42-1 to 42-n of the bus matrix 40.

The second method is a method in which a packet transfer bus is individually drawn from each FIFO-8 to the packet output common memory circuit by wiring. In this method, it is possible to increase the link speed as long as the number of wires can be increased, but fan-out becomes a problem depending on the elements used.

The second method is to use ECL elements and optical semiconductor elements using device technology, and use memories distributed in a matrix as units of output packet transfer buses. According to this method, the size of the matrix can be flexibly changed simply by changing the degree of memory integration.

[Effects of the Invention] As is clear from the above description, according to the present invention, the buffer memories, which were conventionally distributed in the bus matrix section, are grouped together to correspond to the output of the bus matrix section, so that the buffer memory arranged at the lattice points can be is multiple L
SI becomes possible, and the amount of memory is reduced from an increase of 2f1 times to an increase of n times, and accordingly, the price of the bus matrix type packet switching device is reduced, and
It becomes possible to improve credibility.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram showing the configuration of a transmission buffer 20-1 according to an embodiment of the present invention, and FIG. 3 is an input traffic transfer control circuit 30 according to an embodiment of the present invention. 4 is a block diagram showing the configuration of buffer circuits i to j in the bus matrix section 40 according to the embodiment of the present invention, and FIG. A block diagram showing the configuration of the memory circuit 50-j, FIG. 6 is an output traffic transfer control circuit 60 according to an embodiment of the present invention.
7 is a block diagram showing the configuration of the receiving buffer 7O-jl according to the embodiment of the present invention, and FIG. 8 is a block diagram showing the configuration of the input traffic transfer control circuit 30-i according to the embodiment of the present invention. FIG. 9 is a diagram showing the configuration of a QLCN table, FIG. 9 is a diagram showing packet formats on each transmission path according to an embodiment of the present invention, and FIG. 10 is a block diagram showing a conventional bus matrix type packet switching device. In the figure, 20-11 to 20-nm...transmission buffer circuit, 21
-1~21-n...Input packet transfer bus 30-1~
30-n... Input quadrature ink transfer control circuit, 40.
... Bus matrix section 41-1 to 41-n... Input bus of bus matrix section, 42-1 to 42-〇... Output bus of lotus matrix section, ■-1 to n-n... Lotus Buffer circuits 50-1 to 50-n forming the matrix section...Packet output common memory circuits 60-1 to 60-n...Output traffic transfer control circuit, 70-11 to 70-n+*...Reception It is a buffer circuit. 0-nl Principle block diagram of the present invention Fig. 1

Claims (1)

[Claims] A plurality of transmission buffer circuits (20-11) connected to each of a plurality of input packet transfer buses (21-1 to 21-n).
~20-nm) is transferred to a plurality of output packet transfer buses (42-1 to 42-n
) connected to each of the plurality of receive buffer circuits (70-
11 to 70-nm), the input packet transfer buses (21-1 to 21-n) and the input bus (41-n) of the bus matrix section (40). 1-41
-n), and the transmission buffer circuit (
a plurality of input traffic transfer circuit control units (30-1 to 30-nm) that control the input buses of the bus matrix unit (40) based on packets from 20-11 to 20-nm);
n) and the input buses (41-1 to 41-1) of the bus matrix section (40).
A plurality of exchange buffer circuits (1-1, 1-2) connected between the output buses (42-1 to 42-n)
, ..., n-n) and the output buses (42-1 to 42-1) of the bus matrix section (40).
42-n), and the exchange buffer circuit (
1-1, 1-2, . . . , n-n).
A plurality of output traffic transfer circuits (60-1
~60-n), and output buses (42-1~60-n) of the bus matrix section (40).
42-n) and the output traffic transfer circuits (60-1 to 60-1)
The exchange buffer circuit (1
-1, 1-2, ..., n-n) common memory circuit (50-1, 50
-2, . . . , 50-n), respectively.