JPH02199918A - 4-phase clock generating circuit for switched capacitor filter - Google Patents

Abstract

PURPOSE:To set a delay time to a desired time by providing a prescribed number of delay units as a delay, circuit for a 4-phase generating circuit for a switched capacitor filter and turning on required number of delay units at the adjustment at manufacture. CONSTITUTION:A delay circuit is provided in a 4-phase generating circuit for a switched capacitor filter(SCF). In the case of adjusting the delay of the 4-phase generating circuit, an output of a predetermined standard pattern is inputted in parallel with each pin of a register 251 of a setting circuit 25, for example, and the delay time at that time is measured, then whether the time is too long or too short is detected, and other pattern is selected, then an optimum delay is detected. When a control signal with a detected optimum delay is generated in an LSI, the circuit is operated afterward at the optimum delay time.

Description

[Detailed Description of the Invention] [Summary] Regarding a four-phase lock generation circuit for driving four switches that turn on and off both ends of a capacitor of a switched capacitor filter, the delay amount of the delay circuit can be adjusted. The purpose of the present invention is to provide a four-phase clock generation circuit for a switched capacitor filter, which includes a fourth clock generation means that receives an input clock, a third clock generation means, and a delay between the fourth clock and the third clock. The fourth clock generating means has a delayed output of the third clock as its other input, and the third clock generating means has a delayed output of the fourth clock as its other input. The first clock generating means has a delayed output of the second clock as another input, and the second clock generating means has a delayed output of the first clock as another input. In the 4-phase clock generation circuit for capacitor filter, the delay circuit for delaying the first to fourth clocks includes:
It is constructed by cascading a plurality of delay units each having a plurality of stages of logic circuits connected in cascade, and each delay unit is constructed to include a switch circuit whose delay function can be switched on and off by a control signal.

Field of the Invention The present invention relates to a four-phase lock generation circuit for driving four switches that turn on and off both ends of a capacitor in a pinched capacitor filter.

A switched capacitor filter (SCF) is a filter consisting of a capacitor with a switch that opens and closes and an operational amplifier (operational amplifier). R with L removed
The C active filter was further developed to remove R to make it suitable for LSI implementation, and is used as a sample value filter.

In a conventional switched capacitor filter, two switches (four in total) are provided at each end of the capacitor (SCF), and a four-phase lock generation circuit that turns on and off the four switches is as follows: The phase is controlled by a delay circuit so that the clocks during charging and discharging do not overlap.

However, when an SCF is constructed using an LSI circuit, there is a problem in that the delay time of the delay circuit may vary depending on each circuit, deteriorating the characteristics, and an improvement is desired.

[Prior art] Figure 3 shows a switched capacitor filter (SCF).
) is shown.

Figure 3A shows a switched capacitor filter (SC
The configuration of F) is shown in FIG. 3B, whose clock generation circuit is shown in FIG.

Driven by clocks φl to φ4 generated from a four-phase clock generation circuit as shown in FIG. The phases of the clocks are controlled so that the pairs do not occur at the same time.

In operation, when SWI and SW3 are on, capacitor C
is charged with the charge of the input signal, and then SW2. When SW4 is turned on (SWI, SW3 is off), the charge in capacitor C is discharged by the operational amplifier and transferred from capacitor C to capacitor CO of the operational amplifier, and since its transfer function is equivalent to an RC type integrator, the filter can be configured.

As a clock generation circuit for the switched capacitor filter, FIG. 4 is an explanatory diagram of Conventional Example 1, and FIG. 5 is an explanatory diagram of Conventional Example 2.

In conventional example 1 in FIG. 4, A is a clock generation circuit;
B is a clock time chart.

In the clock generation circuit A, 40 is a NAND circuit;
41 is a NOR circuit, 42 and 43 are inverters, 44 is a delay circuit 1 (delay time delay l), and 45 is a delay circuit 2 (delay time delay 2).

To explain the operation of the clock generation circuit A, with reference to the time chart of the clock B, the input clock (C
LK) first passes through a NAND circuit 40° inverter 42 and receives a clock φ2. φ4 is generated (falls), and the delay circuit 44. Through the NOR circuit 41, the delay time de
After lay 1, clock φ1. φ3 is generated (rises), and the input clock (CLK) is “L”
When changing from “H” to “H”, the power clock (CLK)
The clocks φl and φ3 are generated (falling down) through the NOR circuit 41, and the waveforms are further passed through the inverter 43. Delay circuit 45. Through the NAND circuit 40, the delay time dela
After y2, clock φ2. Generate φ4 (start up).

In the case of this conventional example 1, the generated clocks φl, φ3, φ2
and φ4 use the same clock, but they do not actually clock at the same time due to delays in each element, so φ1 and φ4 use the same clock.
3. It is not possible to predetermine the order in which φ2 and φ4 occur, so problems such as DC offset occur in the configuration of the SCF shown in FIG. 3 as an integrator.

The configuration of a clock generation circuit that solves this problem is shown in FIG. 5 as an explanatory diagram of Conventional Example 2. FIG. 5A6 is a clock generation circuit, and B is a clock time chart. This prior art example 2 was previously filed by the applicant of the present application.

In the clock generation circuit shown in FIG. 5A, 50°57 is a NAND circuit, 51.56 is a NOR circuit, and 52°53.58
．． 59 is an inverter, 54. 55. 60.61 is the fourth delay circuit (delay time delay 4).

Third delay circuit (delay 3), %l delay circuit (delayl), second delay circuit (delay 2)
It is.

In the clock generation circuit A, the NOR circuit 56 is the first
The NAND circuit 57 and the inverter 59 constitute a second clock generation means, the NOR circuit 51 constitutes a third clock generation means, and the NAND circuit 50 and the inverter 52 constitute a fourth clock generation means. Configure.

The operation of the clock generation circuit shown in FIG. 5A will be explained with reference to the clock time chart shown in FIG. When the output is delayed by delay 4 through the fourth delay circuit 54 and input to the NOR circuit 51 of the third clock generating means, the third clock φ is generated.
3 occurs (rises).

When the output of the third clock φ3 is delayed by delay 3 through the third delay circuit 55 and input to the NAND circuit 57 of the second clock generating means, the second clock φ2 is generated from the inverter 59 and falls). The clock signal passes through a delay circuit 61, is delayed by delay 2, and is input to the NOR circuit 56 of the first clock generating means.

The NOR circuit 56 is driven by the clock φ2 from the second delay circuit 61 and the clock φ4 delayed by delay 4 from the fourth delay circuit 54 to generate the clock φ1, which is delayed by delay by the first delay circuit 60. and inputs it to the NAND circuit 57 of the second clock generating means. The NAND circuit 57 receives the de signal from the third delay circuit 55 described above.
It is driven by a clock φ3 delayed by lay 3 and a clock φl delayed by delay 1 by the first delay circuit 60 to generate a clock φ2.

[Problems to be Solved by the Invention] According to the configuration of Conventional Example 2 described above, the clock φ1 turns on/off after the clock φ3, and the clock φ2 turns on/off after the clock φ4. The on/off characteristics of the filter capacitor are maintained. In order to maintain this relationship, the delay 11delay 1 to delay 4 between the timings of each clock is an important factor that determines the characteristics of the switched capacitor filter.If this imbalance occurs, DC offset will occur, and the switched capacitor・Causes deterioration of filter characteristics.

Specifically, the delay circuit is configured by cascading inverters (nont circuits) on an integrated circuit in a design-determined number of stages, and the number of stages is fixed. However, when an SCF is manufactured using an LSI circuit, it is inevitable that there will be variations depending on the circuit characteristics of the LSI for each individual circuit, and the degree of variation will vary depending on the delay time of the delay circuit when the SCF is used at a high operating speed. This has become a problem as the delay time approaches the limit of the design-allowed range.

SUMMARY OF THE INVENTION An object of the present invention is to provide a four-phase clock generation circuit for a switched capacitor filter in which the amount of delay of a delay circuit can be adjusted.

[Means to solve the problem] FIG. 1 is a diagram showing the principle configuration of the present invention.

The present invention improves the delay circuit of a four-phase clock generation circuit for a switched capacitor filter (SCF) shown as Conventional Example 2. Therefore, FIG. 1 does not show the overall structure of the SCF, but only the basic structure of the delay circuits (first to fourth delay circuits).

In FIG. 1, 10 is a delay unit, 11 is a logic circuit constituting the delay unit, 12 is a switch circuit that can switch the delay function of the delay unit 10 on and off by a control signal, 1
3 is a control signal.

The present invention is equipped with a predetermined number of delay units as a delay circuit of a four-phase generation circuit for a switched capacitor filter, and a desired delay time can be set by turning on the required number of delay units during adjustment during manufacturing. This allows settings to be made.

[Operation] In FIG. 1, the logic circuit 11 of the delay unit 10 is composed of a one-stage circuit such as an inverter, a NAND circuit, or a NOR circuit, and a plurality of logic circuits kl are connected in cascade to form a delay unit. Configure. Line 11 of the final stage output of the logic circuit 11
0 is connected to one contact a of the switch circuit 12, and the other contact a of the switch circuit 12 is connected to a line 100 that bypasses the cascaded logic circuit 11. Also,
A fixed contact C of the switch circuit 12 is connected to the input of the next stage delay unit IO. In response to the control signal 13, the switch circuit 12 turns on the delay function of the delay unit 10 (contacts c and b
It is possible to switch between the state a) in which the contacts are connected, or the state in which they are turned off (the state in which the contacts c and a are connected).

Although the switch circuit 12 is shown in the form of relay contacts, it is constituted by an electronic analog switch.

When a switched capacitor filter LSI is manufactured, when adjusting the delay time of the delay circuit of the 4-phase clock generation circuit, the delay time is measured and each delay unit of 10 is adjusted to the desired time. Controls the switch circuit 12 that switches the delay function on and off? It is controlled by a binary signal of the D signal 13.

In this way, by making the delay amount of the delay circuit adjustable, it is possible to absorb deterioration factors such as variations in LSI circuit elements and obtain an optimal delay amount.

〔Example〕

FIG. 2 is a configuration diagram of the embodiment.

20 in Figure 2 is a switched capacitor filter (S
CF) LSI, 21, 22. . . . represents a delay unit of a delay circuit in the four-phase lock generation circuit (corresponding to 10 in FIG. 1), P1 to Pn represent control signal input bins, and 25 represents a setting circuit.

A delay circuit shown in FIG. 2 is provided as a delay circuit in a four-phase lock generation circuit of a Swiss capacitor filter (SCF). This delay circuit has a delay unit of 22. It has a configuration in which multiple... are connected in cascade. Taking the delay unit 21 as an example, in this embodiment the delay unit is composed of a two-stage circuit of inverters 21a and 21b, and the switch circuit is a switch that is turned on and off by a control signal supplied from the bin PI of the LSI circuit. *I#22c, 22d
Consisted of. Since the control signal is supplied to the switch 22C via the inverter, the control signal is supplied to the switch 22C.
and 22d operate in a complementary manner, and one of them is turned on.

When a plurality of such delay units 21, 22, etc. are connected in cascade, and a control signal is supplied from pin PIP2P, corresponding to each delay unit, the delay function of the delay unit is turned on/off. be done.

For the switched capacitor filter LSI including the configuration shown in FIG. 2, when adjusting the delay amount of the delay circuit of the four-phase lock generation circuit, for example, the setting circuit 25
The output of a predetermined standard pattern (a bit string indicating whether each delay unit 21, 22, etc. is turned on or off as "13" or "0") is input from each pin in parallel to the register 251 of By measuring the delay time at that time (or by measuring each clock φ1 to φ4), it is possible to detect whether the delay is too long or too short, and by changing to another bit pattern, the amount of delay can be increased by 11! can be detected.The wIm signal with the detected optimal delay amount can be
If it is generated within the SI, subsequent operations can be performed using that optimum delay time.

lO: Delay unit 11: Logic circuit 12: Switch circuit 13: i control signal [Effects of the invention] According to the present invention, the amount of delay between clocks of each phase of a four-phase lock generation circuit in a switched capacitor filter can be adjusted and high precision switched
A capacitor filter can be realized.

Patent applicant: Fujitsu Limited Sub-agent Patent Attorney Hosaka Sosen

[Brief explanation of the drawing]

Figure 1 is a diagram showing the principle configuration of the present invention, Figure 2 is a diagram showing the configuration of an embodiment,
Figure 3 shows a switched capacitor filter (S CF
), FIG. 4 is an explanatory diagram of Conventional Example 1 of the clock generation circuit, and FIG. 5 is an explanatory diagram of Conventional Example 2. In Figure 1, A, the number of switched filters (SCF) is 1.7 + the number of filters (SCF) f
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Claims (1)

[Claims] In order to drive the four switches that turn on and off both ends of the capacitor of the switched capacitor filter, there is provided a fourth clock generating means that receives an input clock;
It comprises a clock generation means, a first clock generation means and a second clock generation means each receiving the delayed output of the fourth clock and the third clock, and the fourth clock generation means receives the delayed output of the third clock as input. The third clock generation means uses the delayed output of the fourth clock as another input, the first clock generation means uses the delayed output of the second clock as another input, and the second clock generation means uses the delayed output of the first clock as another input. In a four-phase clock generation circuit for a switched capacitor filter having a configuration in which a delayed output is used as another input, the delay circuit for delaying the first to fourth clocks is a multi-stage logic circuit (11). Delay units connected in cascade (
10) are connected in cascade, and each delay unit (10
) is a four-phase clock generation circuit for a switched capacitor filter, characterized by comprising a switch circuit (12) whose delay function is turned on and off by a control signal.