JPH02199680A - Magnetic disk device - Google Patents

Abstract

PURPOSE:To prevent data loss due to a fault of write by providing a control section, an instruction generating section and a data verification control section provided with a timing generating section. CONSTITUTION:A control section 13 of a data verification control section 10 receives a write start, data quantity from a write control section 2 during the write and a control signal 39 representing the start of an ECC section and commands the fetch of a write instruction and the fetch of execution timing. An instruction generating section 11 converts a write instruction 22 into a relevant readout instruction code under the control of the control section 13, stores it or outputs it. A timing generating section 12 manages the drive position synchronizing with the rotation period of a recording section 8 and stores and reproduces the execution timing of write operation by the control of the control section 13. Thus, re-write is executed in the system and loss of data while left unprocessed regardless of write error is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a magnetic disk device, and more particularly to a magnetic disk device equipped with a writing abnormality detection means for preventing data loss due to a writing abnormality.

[Conventional technology]

Traditionally, as means for detecting write abnormalities in magnetic disk drives, means for detecting abnormal operation of write signals or control signals during the writing process has been adopted, and verification of recorded data is performed by a host system such as program specification. This is done under the control of

[Problem to be solved by the invention]

With the signal checking means during the writing process in conventional magnetic disk drives as described above, the guarantee for recorded data is an indirect guarantee, and even if no abnormality is detected in the intermediate signal, the last recorded data has not been verified, and there is a drawback that there is a possibility that the recorded data may not be recorded in a readable and normal state.

Therefore, verification of recorded data requires intervention from a higher-level system. However, in this case, there is a drawback that extra steps such as searching for the recording position are required, and there is a risk that other error factors may be added and the error may be confused with another abnormality.

[Means to solve the problem]

The magnetic disk device of the present invention receives a read command from a host device and outputs a corresponding read command signal, inputs an end status signal from a read control unit and outputs it to the host device, and receives a write command from the host device. an interface unit that receives a read command signal from the interface unit and outputs a corresponding write command signal, inputs an end status signal from the write control unit and outputs it to the host device; and a synchronization signal generator that receives a read command signal from the interface unit. Timing verification based on the synchronization signal from the data demodulator and EC
performs a status check with reference to the operation status of the C section, outputs a control signal, inputs the operation status signal and instructs the data demodulation section to output read data to the interface section and the ECC section; The ECC data is read and output to the ECC section, and the ECC data is read out and output to the ECC section.
An operation status signal is input from the C section and an end status signal or an error signal is output, and timing verification and data demodulation are performed based on the synchronization signal from the synchronization signal generation section according to a read command from the data verification control section. and the read control unit which performs a status check with reference to the operation status of the ECC unit and the ECC unit and outputs an end status signal to the data verification control unit, and which inputs a read signal from the recording unit and retrieves data. the data demodulation unit outputs an operation status signal as a result of the read operation and read data restored to the original data format, and converts the magnetization reversal pattern recorded by the read operation into an electrical signal and outputs it, and outputs the write command. Verifying the read data from the recording section that inputs a signal and records it as a magnetization reversal pattern, the synchronization signal generation section that outputs a synchronization signal synchronized with the rotation of the recording section, and the data demodulation section. and outputs the result as an operation status signal, and inputs write data from the interface section, performs arithmetic processing, and outputs ECC data; and inputs a write command signal from the interface section and outputs the synchronization signal. A control signal for controlling the write operation is output by performing timing verification based on the synchronization signal from the generation section and a status check referring to the operation status of the data demodulation section and the ECC section. terminating the input and instructing the sending of ECC data, referring to the operation status of the ECC section to output a termination status signal or activating the data verification control section, and transmitting the verification status signal from the data verification control section. The write control unit receives input and outputs an end status signal, inputs write data from the interface unit, inputs a control signal from the write control unit, performs code conversion and signal format conversion, and inputs ECC data. a data modulation unit that outputs a write signal by adding it to the write data; and a data modulation unit that inputs a control signal from the write control unit to instruct the acquisition of a write command and the execution timing, and upon activation of a verification operation. A read command code is taken out from the command generation section, a timing at which a write operation is executed is taken out from the timing generation section and a read command is outputted, an end status signal is inputted from the read control section, a verification status signal is outputted, and a verification operation is performed. a control unit that converts a write command into a corresponding read command code under the control of the control unit, stores the same, and outputs the same;
and the data verification control unit, which includes the timing generation unit that manages the rotational position of the storage unit in synchronization with the rotation period of the storage unit, and stores and reproduces the execution timing of a write operation under the control of the control unit. There is.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a particularly characteristic portion and peripheral functional portions of an embodiment of the present invention.

In FIG. 1, an interface control section 1 receives a read command from a host device and sends out a read command 23 equivalent to the read command to operate the read control section 3.

The read control section 3 performs timing verification based on the synchronization signal 34 generated by the synchronization signal generation section 6 and the data demodulation section 7.
A status check is performed with reference to the operation statuses 33 and 35 of the ECC section 4, and if the execution conditions are met, control signals 36 and 37 are generated based on the synchronization signal 34 to control the read operation.

The synchronization signal 34 is a signal synchronized with the rotation of the recording unit 8, and is a reference signal for managing the rotational position, which includes a signal indicating the starting point of the rotational position, a clock signal that equally divides the rotational position, and the like.

The synchronizing signal generating section 6 receives a position signal 30 generated at a reference point provided in the recording section 8 and a corresponding readout signal 31, and generates a synchronizing signal 34. In the read operation, the recording unit 8 converts the recorded magnetization reversal pattern into an electrical signal and outputs it.

The data demodulator 7 inputs the read signal 31, restores it to the original data format, searches for data, and generates an operation status signal 33 when detecting data.

The read control unit 3 receives this signal and reads the read data 32.
The read data 32 is sent to the interface control section 1 and the ECC section 4. When the output of the specified data is completed, the ECC data is subsequently read and inputted to the ECC section 4.

The ECC unit 4 performs arithmetic verification on the read data 32 and sends out a signal indicating the presence or absence of a read error as an operation status 35.

The read control unit 3 inputs this operation status 35 and sends out an end status 38 depending on its contents. If there is no reading error, a status indicating normal completion is generated, and if there is an error, a status indicating an error is generated. In addition, the operation status of each part is constantly referred to at the start of the read wI control operation and during control, and if there is a problem with the operating conditions, the execution is canceled, and if an abnormality is reported, the operation is interrupted and responded accordingly. Generates an exit status.

The interface control unit 1 inputs the termination status, sends it to the higher-level device, and terminates the operation for the command.

When the interface control unit 1 receives a write command, it operates the write control unit 2 that has generated a write command 22 equivalent to the write command.

Similar to the read control unit 3 when receiving the read command 23, the write control unit 2 performs timing verification and status checks of the operation statuses 28 and 35, determines the execution conditions, and executes the write operation when the execution conditions are satisfied. Control the execution of actions.

The data modulation unit 5 transmits data to the write control unit 2 at a specified timing.
The write data 25 is inputted from the write data 25, and a write signal 29 suitable for writing in the recording unit 8 is generated by code conversion and signal format conversion, and the recording unit 8 records this as a magnetization reversal pattern.

The write control unit 2 controls the start timing of writing and the input timing of write data using a synchronization signal 34, and instructs to send out the ECC data 27 when inputting predetermined data is completed.

The data modulator 5 converts the ECC data 27 into write data 2.
5, and then modulates ECC data 2 to write data 25.
A write signal 29 to which 7 is added is generated, and the recording section 8 records this. The ECC data 27 is information for verifying recorded data when it is read, and is used for detecting data errors and correcting error locations. By doing this, the reliability of the data is guaranteed. Depending on the degree of error, it may become impossible to correct and data may be lost.

The ECC unit 4 receives write data 21 at the time of writing, processes it using a predetermined algorithm, and generates ECC data 27. At the time of reading, the read data 32 including the data is input, and arithmetic processing according to the algorithm that generated the ECC data 27 is performed to determine the presence or absence of an error. The main cause of this error is an operational error in the read function, but there are also deterioration of the recording state and operational errors in the write function during writing, with the latter having a high possibility of losing data.

The write control unit 2 always refers to the operation status and performs the same processing as the read control unit 3 in response to defects and abnormalities.
Accordingly, the end status 24 is generated and the operation for the command is completed, but there is no abnormality report and the ECC data 2
When the writing up to 7 is completed, the verification operation of the data verification control unit 10 is activated. Conventionally, this operation does not exist, and the operation for the instruction ends with normal termination.

In the data verification control unit 10, the control unit 13 receives a control signal 39 from the write control unit 2 indicating the start of writing, the amount of data, and the activation of the ECC unit during the write operation, and takes in the write command and the execution timing. Instruct.

The instruction generation unit 11 converts the write instruction 22 into a corresponding read instruction code and stores it under the control of the control unit 13,
Also output this. The timing generating section 12 manages the rotational position of the recording section 8 in synchronization with the rotation period of the recording section 8, and stores and reproduces the execution timing of the write operation under the control of the control section 13.

Upon receiving activation of the verification operation, the control unit 13 extracts the read instruction code from the instruction generation unit 11, extracts the timing at which the write operation was executed from the timing generation unit 12, and executes the read at the recording position of the written data. A read command 41 is generated so as to be executed. In response, the read control unit 3 performs the same operation as in response to the read command 23 from the interface control unit 1 described above. However, the termination is not sent to the interface control unit 1, but to the control unit 13 of the data verification control unit 10 via the termination status 4.
Send 2. The control unit 13 determines its termination status 42.
The verification status 40 is generated with reference to the verification status 40, and the verification operation is ended.

The write control unit 2 generates a termination status indicating normal completion only after confirming that there are no errors or abnormalities in the verification status 40, and the interface control unit 1 sends it to the host device to perform the operation in response to the write command. finish. If there is an error or abnormality in the verification status 40, a corresponding completion status is sent.

FIG. 2 is a block diagram showing details of the data verification control section 10.

The data end 41C is set to "1" to command reading. If the data is divided, it is sent out sequentially as a series of read commands corresponding to a series of write commands during writing. EC
When a command is sent with a read command code that corresponds to a write command code that adds C data, and the command is executed, E
Verification of read data by CC is completed. At this time,
ECC verification completed 42A becomes “1” and read error 42
C is "1" if there is a data error, and "O'" if there is no data error. If another abnormality occurs during the read operation, the operation is stopped and the malfunction 42B becomes "1".

The end of the read operation is the end of the verification operation, and the end of the operation 4
Set 0A to "1", if there is no abnormality or data error, set verification failure 40B to "0", if any of these exist, set it to "1",
This logical value becomes a criterion for determining whether or not there is a write abnormality.

“Q” of D type flip-flop (DF/F) 116
When the write operation 39A reaches 1°, it becomes 1° at the rising edge of the synchronous clock 34A, and the first-in first-out buffer memory (FIFO)
102, 104, and 105 are reset.

"Qo" and "Q1" of the serial-in-parallel out shift register (sist register) 112 describe the logic values of the data conversion 39B in terms of the signals input and output at the beginning of the synchronization clock 34A and the operations thereof. When a write command is executed, the write operation 39A first becomes active (“1”). Next, when the write data is received and the data write operation is started, the data conversion 39B becomes "1". When the write data is completed, the ECC data writing starts, and the ECC sending 39C becomes "1".
When data writing is completed, data conversion 39B and EC
C sending 39C both return to inactive (“O'°).To avoid defects in the recording section, when one piece of data is divided and recorded in a series of write commands, the entire data is stored in the last block. In order to measure the execution timing of each instruction in the data conversion 39B, which changes for each instruction, the end of a series of write operations is detected by sending an ECC code in which only the last instruction changes. used to trigger verification operations.

The synchronizing clock 34A is a clock signal that equally divides the rotational period obtained by dividing the basic period based on the bit rate of data synchronized with the rotation of the recording section, and uses this as a reference for managing the rotational position. It is also used to synchronize control timing. The verification operation is the execution of data reading, in which a read command code 41A corresponding to the write command code 22A at the time of writing is generated, the operation movement 41B is set to "1" at the rotational position where the data is recorded, and the data is written. "Ql" is shifted at a timing corresponding to the data length when it is loaded, and "Ql" is
Data conversion 39 that changes one clock later than "o"
When B becomes 1", "Qo" and Q1" of the shift register 112 change from "0" and 0" to II I IT and "0" and "1" and "1" and so on by the synchronous clock 34A.
..., and the output of the AND gate 113 becomes "'1" when the values are 1'' and 0''. Data conversion 39B is “
When the shift register 112 becomes “Q o”
and “Ql” changes from “1” and “1” to 0′° and l I II II○゛′ and “O11,”
The output of the AND gate 113 and the AND gate 114 is 1 clock width pulse of the synchronous clock 34A, and the AND gate 113 outputs 1 when the data is 0 and 1. The AND gate 114 outputs an output at the start timing of the conversion and at the end timing.

The programmable counter (counter) 103 sets the counting period to the number of synchronous clocks 34A for one rotation of the recording section. The "Q" output of the counter 103 indicates a count value synchronized with the rotation of the recording section, and the count value corresponds to the rotational position. FIFO 104 receives the output pulse of AND gate 114, FIFO 105 receives the output pulse of AND gate 114, and FIFO 105 receives the output pulse of AND gate 113. Each time a pulse is input, the count value of counter 103 is taken in and held. That is, PIFO105
stores the rotational position where the data starts, and PIFO 104 stores the rotational position where the data ends. The FIFOIOI captures and holds the write instruction code 22A for each output pulse of the AND gate 113.

The read-only memory (ROM) 102 records the read instruction code corresponding to the write instruction code 22A at the address corresponding to that instruction. Therefore, ROM
102 operates as a code converter and outputs a read instruction code corresponding to the write instruction code. When ECC sending 39B becomes “1”, DF/F11
“Q”’ of 5 becomes “1” and DF/FILO and 1
Cancel the reset of 11. At this time, FIFOIOI
and 104 and 105 output the first captured data. That is, PIFOIOI outputs the instruction code of the first write command executed in the current write operation, PIFO 105 outputs the rotational position at which it started, and FrFO 104 outputs the rotational position at which it ended.

When the address bits are divided into two sets of binary data, the ROM 106 and R, OM 107 record logic "1" only for data at addresses whose bit arrangement has a certain relationship. The ROM 106 stores the count value of the counter 103 and the FI
When the difference from the count value indicated by the output of F○ 104 reaches the set value, 1'' is output, and similarly, the ROM 107 outputs 1''.
When the difference between the count value of 3 and the count value indicated by the output of the PIFO 105 reaches the set value, "1" is output. Data conversion 3
The relative timing between the change point of 9B and the rotational position where data is actually recorded is constant, and the relative timing between the rotational position where data is recorded and the generation position of the command to read it is within a certain range. Therefore, the timing for generating a read command can be determined based on the count difference.

The ROM 107 outputs "1" from the rising edge of the data conversion 39B to the start point of the read operation, and the ROM 106 outputs "1" from the falling edge of the data conversion 39B to the end point of the data. When the value of the counter 103 becomes the correction value of the output of PIF0105 at the synchronization clock 34A and the output of the ROM 107 becomes "1'', the "°Q parameter" of DF/Fill becomes "1" at the next synchronization clock 34A. At the same time, the count of the counter 103 advances and the ROM 1
The output of 07 returns to “0” and DF/F1 is activated at the next clock.
11's "Q" also becomes "0". Therefore, the DF/F 111 outputs a pulse of one clock width at the correction timing set in the ROM 107 for "Q"'. With this pulse, the D-type latch 108 takes in data from ROMIO2 and converts the output, and at the same time, FIFOIOI and FIFO10
5 updates the output to the next data. D type latch 10
The output of 8 becomes the read instruction code 41A of the read instruction to be executed from now on, and the output is the read instruction code 41A of the read instruction to be executed from now on.
Data for the next instruction to be executed is prepared at the output of 05.

In order to wait for the output of the D-type latch 108 to be determined, the shift register 109 shifts the pulse of the DF/Fi 11 using the synchronous clock 34A, delays it by two clocks, and outputs 'Q!'. This is set as the operation start 41B, and the read instruction code 4 outputted by the D type latch 108
Commands the start of the operation specified by 1A. Reading is performed in accordance with the rotation of the recording section, and the count of the counter 103 also advances in synchronization with the rotation. The value of counter 103 is PIFO104
When the output of ROM 106 becomes the correction value, the output of ROM 106 becomes “1”.
Then, the output "Q" of the DF/F 110 becomes "1" for one clock.
Command the end of reading as C. At the same time, with this output, the PI
The FO 104 updates the output to quaternary data and prepares for the next instruction. Continue the above operation with the data left in FIFOIOI and 104 and 105 until ECC verification end 42A becomes "1" or malfunction 42B becomes 1", or write operation 39A becomes "°O゛°. .When malfunction 42B becomes 1", OR gates 117 and 118 both become "1'°, and DF/F
Q'' of 115 is also ``1'', and both AND gates 119 and 120 output ``1''. In this case, the operation end 4OA and the verification failure 40B are both "1'°, indicating abnormal termination, and the operation failure 42B is 'O" and the ECC is
When the verification end 42A is "1", the output of the OR gate 117 is "1", and the output of the AND gate 119 is also "1".
The operation end 40A becomes "1" to indicate the end, but the verification failure 40B is determined by the read error 42C, and when the read error 42C is "1", the output of the OR gate 118 becomes "1". The output of AND gate 120 is also “1”
Therefore, if the verification failure 40B becomes "1", indicating abnormal termination, and the read error 42C becomes "0", the output of the OR gate 118 becomes 0, and the output of the AND gate 120 also becomes "O". Therefore, verification failure 42B is “
In other words, normal completion occurs only when there is no malfunction, ECC verification is completed, and there is no read error. When the completion report to the host device is completed, the write operation 39A returns to "0". ”, the DF/F and FIFO are reset and stop operating.

〔Effect of the invention〕

As explained above, the magnetic disk device of the present invention guarantees that the data is reliably recorded in a readable state by reading and verifying the data within the write command when data is written. There is an effect that it can be done. This verification also has the effect of making it clear that there is a write error even if the data cannot be read normally. Therefore, in the system, writing is performed again, and there is an effect that it is possible to prevent the risk of data loss due to writing errors being left unattended. Another advantage is that it is possible to prevent the possibility that even if the data cannot be read when read later, it will be confused with a read error and the abnormality detection in the write system will be delayed, resulting in greater damage.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a data verification control section of the embodiment of FIG. 101, 104, 105...First-in first-out buffer memory (FIFO), 102, 106
・107...Read only memory (ROM), 103
...Programmable counter, 108...D type latch (D latch), 109/112...Serial in parallel out shift register (shift register),
110, 111, 115, 116...D type flip-flop (DF/F). 113, 114, 119, 120...and gate,
117/118...or gate.

Claims (1)

[Claims] Receiving a read command from a host device and outputting a corresponding read command signal, inputting an end status signal from a read control unit and outputting it to the host device, and receiving a write command from the host device. an interface section that outputs a corresponding write command signal from the write control section, inputs an end status signal from the write control section and outputs it to the host device; Timing verification based on the synchronization signal and status check referring to the operation status of the data demodulation section and the ECC section are performed, a control signal is output, and the operation status signal is input to the interface for the data demodulation section. and the ECC section to output read data, read the ECC data and output it to the ECC section, input an operation status signal from the ECC section, output an end status signal or an error signal, and read the ECC data. The data verification control is performed by performing a timing verification based on the synchronization signal from the synchronization signal generation section and a status check with reference to the operation status of the data demodulation section and the ECC section according to a read command from the verification control section. the read control unit outputs an end status signal to the storage unit; inputs a read signal from the recording unit and outputs an operation status signal as a result of data search and read data restored to the original data format; the data demodulation section that converts the magnetization reversal pattern recorded by the read operation into an electrical signal and outputs it, inputs a write command signal and records this as the magnetization reversal pattern; and the recording section the synchronization signal generator outputs a synchronization signal synchronized with the rotation of the synchronous signal generator, the data demodulator verifies the read data from the data demodulator, outputs the result as an operation status signal, and inputs the write data from the interface unit. The ECC section performs arithmetic processing and outputs ECC data; The data demodulation section and the ECC perform timing verification based on the synchronization signal from the synchronization signal generation section by inputting a write command signal from the interface section. outputs a control signal to control the write operation, completes input of predetermined data, instructs to send ECC data, and refers to the operation status of the ECC section. the write control unit that outputs a completion status signal or starts up the data verification control unit, inputs the verification status signal from the data verification control unit, and outputs the completion status signal; a data modulation section that inputs ECC data, inputs a control signal from the write control section, performs code conversion and signal format conversion, inputs ECC data, adds it to the write data, and outputs a write signal; Inputs a control signal from the unit to instruct the acquisition of the write command and execution timing, receives the start of the verification operation, retrieves the read instruction code from the instruction generation unit, and determines the timing at which the write operation was executed from the timing generation unit. a control unit that takes out and outputs a read command, inputs an end status signal from the read control unit and outputs a verification status signal to complete the verification operation; and a control unit that outputs a write command and a corresponding read command under the control of the control unit. the command generation section that converts into a code, stores it, and outputs it; and the storage section that manages its rotational position in synchronization with the rotation period of the storage section and stores the execution timing of the write operation under the control of the control section. and the data verification control section including the timing generation section for reproduction.