JPH021943Y2 - - Google Patents
Info
- Publication number
- JPH021943Y2 JPH021943Y2 JP191782U JP191782U JPH021943Y2 JP H021943 Y2 JPH021943 Y2 JP H021943Y2 JP 191782 U JP191782 U JP 191782U JP 191782 U JP191782 U JP 191782U JP H021943 Y2 JPH021943 Y2 JP H021943Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- agc
- resistor
- capacitor
- time constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 16
- 230000010354 integration Effects 0.000 claims description 4
- 230000004069 differentiation Effects 0.000 claims description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000001514 detection method Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005562 fading Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Circuits Of Receivers In General (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
この考案はAM受信機において、急激な強入力
時に復調出力がひずむのを防止するAGC回路に
関する。[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to an AGC circuit in an AM receiver that prevents demodulated output from being distorted when a sudden strong input occurs.
AM受信機では一般にキヤリアを整流して受信
出力を一定に保つためのAGC機能を備えている
が、強力な信号に同調した瞬間や、フエーデング
で急激な強度変化があつたときにはAGCの立ち
上りが間に合わずに、回路のオーバーロードによ
るひずみが生ずることがある。
AM receivers generally have an AGC function that rectifies the carrier and keeps the received output constant, but the AGC rises in time at the moment when it tunes to a strong signal or when there is a sudden change in intensity due to fading. Distortion due to overloading of the circuit may occur.
そこで、上述のような従来技術において、一時
的にAGC利得を越えるような信号に同調した瞬
間や、空間波におけるフエーデング等で急激な電
界強度の変動があつた場合はAGCの立ち上がり
が間に合わず、該AGC回路の過負荷による歪み
が生じていたものである。この考案は、以上のよ
うな欠点を改良する目的で行なわれたものであ
る。
Therefore, in the conventional technology described above, when the signal temporarily tunes to a signal that exceeds the AGC gain, or when there is a sudden change in electric field strength due to fading in a spatial wave, the AGC does not rise in time. The distortion was caused by an overload on the AGC circuit. This invention was made for the purpose of improving the above-mentioned drawbacks.
中間周波増幅器の出力を整流する２組の整流回
路を設け、第１の整流回路の出力は抵抗とコンデ
ンサからなる積分回路によつてAGC信号を得る
回路に、抵抗と並列に時定数切換スイツチが駆動
されたときだけ抵抗が付加する回路を配設し、第
２の整流回路の出力は、コンデンサと抵抗からな
る微分回路で微分した信号を増幅器で増幅し、そ
の出力を前記の時定数切換スイツチに付勢し駆動
してAGC発生積分回路の抵抗値を下げ、積分回
路の時定数を短縮する構成である。
Two sets of rectifier circuits are provided to rectify the output of the intermediate frequency amplifier, and the output of the first rectifier circuit is connected to an integrating circuit consisting of a resistor and a capacitor to obtain the AGC signal, and a time constant switch is connected in parallel with the resistor. A circuit is provided that adds a resistance only when driven, and the output of the second rectifier circuit is differentiated by a differentiator circuit consisting of a capacitor and a resistor, and the signal is amplified by an amplifier, and the output is sent to the time constant changeover switch mentioned above. This configuration lowers the resistance value of the AGC generation integration circuit by energizing and driving it, thereby shortening the time constant of the integration circuit.
図は本考案の一実施例を示すAGC回路のブロ
ツク図である。
The figure is a block diagram of an AGC circuit showing an embodiment of the present invention.
図中A1，A2は中間周波増幅器で、D1は音声検
波器である。整流器D2はAGC用整流器で負荷抵
抗R1とバイパスコンデンサC1の並列接地の負荷
に整流信号が発生し、抵抗２を介してコンデンサ
C2とでなる一定の時定数をもつ積分回路によつ
てAGC電圧として増幅器A1，A2に供給されて
AGC動作をする。このAGC信号発生回路におい
て、コンデンサC1は中間周波数をバイパスする
小容量コンデンサであつて整流出力に対してはコ
ンデンサとしての作用をしないので抵抗R2を通
つてコンデンサC2の両端に現われるAGC電圧は
キヤリア強度に比例する平均値出力であつて、変
調の影響を受けない代りに信号の急激な変化には
対応できない性質がある。 In the figure, A 1 and A 2 are intermediate frequency amplifiers, and D 1 is an audio detector. Rectifier D 2 is a rectifier for AGC, and a rectified signal is generated in the parallel grounded load of load resistor R 1 and bypass capacitor C 1 , and the rectified signal is sent to the capacitor via resistor 2.
It is supplied as an AGC voltage to amplifiers A 1 and A 2 by an integrating circuit with a constant time constant consisting of C 2 and
Performs AGC operation. In this AGC signal generation circuit, capacitor C 1 is a small capacitor that bypasses the intermediate frequency and does not act as a capacitor for rectified output, so the AGC voltage that appears across capacitor C 2 through resistor R 2 is an average value output proportional to the carrier strength, and is not affected by modulation, but has the property of not being able to respond to sudden changes in the signal.
整流器D3はAGC回路制御用電流で、抵抗R4の
コンデンサC3は整流出力に対して負荷として機
能する定数より成り、この整流出力は信号のピー
ク値に比例するピーク整流出力が得られる。この
出力はコンデンサC4・抵抗R5で成る微分回路を
通して出力の変化分のみが取り出され、増幅器
A3で増幅してリレースイツチＳを動作させる。
このリレースイツチＳは常時は開放で、動作時の
み接触し、AGC回路の時定数抵抗R2に並列にR3
を接続する。抵抗R3の抵抗値が０Ωの場合はコ
ンデンサC2は整流器D2の出力部に直接に接続さ
れたと同じであり、ピーク値整流となるが、コン
デンサC2の容量がAGC時定数の都合で適値より
大きい場合は出力の立ち上りに影響する等の副作
用を生ずるので、適当な抵抗R3を入れて、ピー
ク値整流に近い立上りも悪くならない定数を選定
する必要がある。 The rectifier D 3 is a current for controlling the AGC circuit, and the capacitor C 3 of the resistor R 4 is composed of a constant that functions as a load for the rectified output, so that a peak rectified output proportional to the peak value of the signal can be obtained. This output passes through a differentiation circuit consisting of capacitor C 4 and resistor R 5 , and only the change in output is taken out, and then the amplifier
A 3 amplifies it and operates relay switch S.
This relay switch S is normally open, contacts only during operation, and is connected to R 3 in parallel to the time constant resistor R 2 of the AGC circuit.
Connect. If the resistance value of resistor R 3 is 0Ω, it is the same as if capacitor C 2 was connected directly to the output part of rectifier D 2 , resulting in peak value rectification, but the capacitance of capacitor C 2 is If it is larger than the appropriate value, side effects such as affecting the rise of the output will occur, so it is necessary to insert an appropriate resistor R3 and select a constant that does not deteriorate the rise close to peak value rectification.
本考案によつてスイツチＳが動作するのは制御
用の整流器D3の出力を微分して、信号に急激な
大振幅の変化があつた場合だけ作動するので、微
分回路と増幅器A3の出力回路の定数による保持
時間が過ぎるとリレースイツチＳは開放され、そ
のリレースイツチＳの作動で抵抗R3が抵抗R2に
並列接続されたときだけAGC電圧は信号の急激
な変化に追従して出力の変化を減小して、回路の
オーバーロードによるひずみの発生を無くするよ
うに動作する効果がある。
According to the present invention, the switch S operates only when the output of the control rectifier D3 is differentiated and there is a sudden large amplitude change in the signal, so the output of the differentiating circuit and the amplifier A3 is When the holding time according to the circuit constant has passed, the relay switch S is opened, and only when the resistor R3 is connected in parallel to the resistor R2 due to the operation of the relay switch S, the AGC voltage follows the sudden change in the signal and is output. This has the effect of reducing the change in the voltage and eliminating the occurrence of distortion due to circuit overload.
図面は、本考案の一実施例を示す回路図であ
る。
A1，A2……増幅器、C1，C2，C3，C4……コン
デンサ、D1，D2，D3……整流器、R1，R2，R3，
R4，R5……抵抗。
The drawing is a circuit diagram showing an embodiment of the present invention. A 1 , A 2 ... Amplifier, C 1 , C 2 , C 3 , C 4 ... Capacitor, D 1 , D 2 , D 3 ... Rectifier, R 1 , R 2 , R 3 ,
R 4 , R 5 ...Resistance.
Claims (1)
コンデンサと抵抗が並列接地した検波回路を２組
設け、前記第１の検波回路はAGC信号用として
抵抗とコンデンサとでなる積分回路に接続し、該
積分回路の抵抗に、時定数切換スイツチと抵抗を
直列した回路を並列接続し、前記第２の検波回路
はAGC信号の積分回路の制御信号発生回路でコ
ンデンサと抵抗とでなる微分回路に接続し、該微
分回路は増幅器を介して前記積分回路の時定数切
換スイツチに入力し、急激な信号変化で前記時定
数切換スイツチを駆動してAGC時定数を可変す
ることを特徴とするAM受信機のAGC回路。 In series with the rectifier from the output side of the intermediate frequency amplifier,
Two sets of detection circuits are provided in which a capacitor and a resistor are grounded in parallel.The first detection circuit is connected to an integrating circuit consisting of a resistor and a capacitor for AGC signals, and a time constant changeover switch and a resistor are connected to the resistor of the integrating circuit. are connected in parallel, and the second detection circuit is a control signal generation circuit of an AGC signal integration circuit and is connected to a differentiation circuit consisting of a capacitor and a resistor, and the differentiation circuit is connected to the integration circuit through an amplifier. An AGC circuit for an AM receiver, characterized in that the AGC time constant is input to a time constant changeover switch, and a sudden signal change drives the time constant changeover switch to vary an AGC time constant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP191782U JPS58121418U (en) | 1982-01-11 | 1982-01-11 | AM receiver AGC circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP191782U JPS58121418U (en) | 1982-01-11 | 1982-01-11 | AM receiver AGC circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58121418U JPS58121418U (en) | 1983-08-18 |
| JPH021943Y2 true JPH021943Y2 (en) | 1990-01-18 |
Family
ID=30014910
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP191782U Granted JPS58121418U (en) | 1982-01-11 | 1982-01-11 | AM receiver AGC circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58121418U (en) |
-
1982
- 1982-01-11 JP JP191782U patent/JPS58121418U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58121418U (en) | 1983-08-18 |
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