JPH02193279A - Sorting device - Google Patents

Abstract

PURPOSE:To execute high speed sorting by comparing simultaneously a new distance and a character code with regard to all stages of each shift array, and also, executing simultaneously loading and shifting of each shift array based on a result of its comparison with regard to all stages. CONSTITUTION:In the case of applying to sorting of a candidate of a character recognizing device, data and a key become a character code and a distance, respectively. By each comparing means 8, 9, a new character code and a distance, and a character code and a distance held in each stage of each shift array 1, 2 are compared simultaneously. In accordance with a result of this comparison, shifting and loading of each stage of each shift array 1, 2 are controlled successively, a space is secured in a stage for the new character code and the distance, and the new character code and the distance are loaded to its stage, by which sorting whose key is a distance is executed. In such a way, high speed sorting can be executed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a sorting device that sorts data in a certain order according to its keys, and for example, in a character recognition device, character codes of candidates are determined using distance from a dictionary as a key. The present invention relates to a sorting device suitable for high-speed sorting applications.

[Problems to be solved by conventional technology and invention] Kanji OC
In R, recognition results (candidates) are determined by extracting the features of the recognition target character image and matching them with a standard feature dictionary. Sorting using distance as a key is required each time. FIG. 8 is an example of this sorting. In this example, in the state shown in (a), if the distance is 80 when matching the character code with the template (simply expressed as (K, 80)),
This shows that the character code K has been inserted between the character code C and the character code D, and the state has been updated to the state shown in (b).

In addition, Kanji OCR supports multiple fonts, etc.
In order to improve the recognition rate, multiple templates may be prepared for the same character code.

In this case, it is necessary to ensure that the same character code does not overlap in the candidates. Figure 9 is an example of this, where in the state of (a), character code G is duplicated and becomes a candidate.
After inserting (G, 80), by deleting the data of (G, 120) with the same character code G but with a large distance (b)
This indicates that the state has been reached.

Note that since it is common for Kanji OCR to output about 10 candidates as recognition results and use them for post-processing, 10 candidates are used here as well. Also, as a character code, usually
Kanji codes such as Shift JIS are used, but for convenience, they are shown in alphabetical order.

Such sorting can also be performed by software processing using a general-purpose CPU and memory. However, after comparing the distance with the registered data for each character and determining the insertion position, the registered data (character code and distance) behind that position (on the side with a larger distance) is moved ( This requires repeated reading and writing, making high-speed processing difficult. Similar processing is also required to eliminate duplicate character codes.

On the other hand, a sorting method has been proposed in which the distance value is used as an index of the memory address and character codes are written, but this method requires a considerable amount of memory capacity (the capacity is the maximum value of the distance that is valid as a candidate). This is particularly problematic when attempting to integrate into a single chip.

Also, elimination of duplicates of the same character code must be performed as a separate process.

Furthermore, pipeline merge sorters, bitonic sorters, etc., which execute sorting processing using dedicated hardware, have been proposed mainly for application to database systems, etc.; However, there is a problem that the circuit configuration is too complicated.

An object of the present invention is to provide a sorting device that has a relatively simple configuration that can be easily integrated into a single chip and is suitable for high-speed sorting of candidate data for Kanji OCR.

Another object of the present invention is to provide a sorting device that can efficiently read out sorted results to the outside.

[Means to solve the problem]

In order to achieve the above object, claim (1) provides means for retaining externally input data and its key;
A data shift array and a key shift array having a multistage configuration consisting of a combination of elements that can be loaded and shifted, each data held in each stage of the data = 4-shift array, and the data held in the data holding means. and a means to simultaneously compare the data
means for simultaneously comparing each key held in each stage of the key shift array with the key held in the key holding means, and for each stage of each shift array according to the comparison result Ik of each comparing means; By sequentially controlling the loading of the data and keys held in the holding means and the shifting of the data and keys held in each of the shift arrays, data and keys are transferred onto each of the shift arrays in the key order. and control means for arranging the arrangement according to the following.

Further, in claim (2), the control means controls each shift array up and down when reading out the sorting results, and arbitrarily reads out data and/or keys in ascending order of keys or in descending order of keys. It is.

[For production]

For example, when applied to sorting candidates for a character recognition device, the data is the character code and the key is the distance. When a new character code and distance are held in the holding means, each comparison means compares this character code and distance with the character code and distance held in each row of each shift array. The control means sequentially controls the shifting and loading of each stage of each shift array according to the result of this comparison,
A space is secured in the row where a new character code and distance should be inserted, and the new character code and distance are loaded into that row, thereby performing sorting using distance as a key. If there are duplicate character codes, the one with the larger distance is also deleted at the same time.

New distances and character codes are compared for all stages of each shift array at the same time, and loading and shifting of each shift array/r based on the comparison results is also performed for all stages at the same time, enabling high-speed sorting. It is.

In addition, when reading the sorting results to the outside, each shift array can be controlled up and down to read in the order of the smallest key or the largest key, so by changing this arbitrarily as necessary, you can improve efficiency. Reading is possible.

Regarding the device configuration, each shift array has a regular configuration in which elements are combined in multiple stages, and each comparison means has a regular configuration (repetition of the same element) similar to a normal multi-bit comparator, so the overall It has a relatively simple circuit configuration and is suitable for integration into a single chip.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. This example is applied to sorting candidates for a character recognition device, and the character code (data) as a recognition result
and distance (key) are character code and shift array 1, respectively.
It is assumed that the distance data is sorted on the distance data shift array 2 in descending order of distance.

When inserting a new character code and distance into the corresponding position of each shift array 1.2, the character code and distance data are set in the character code register 4 and the distance data register 5, respectively, via the internal bus 3, and the control Shift control section 7 is activated by line 6. Additionally, the distance data comparator 8 compares the distance data set in the distance data register 5 with the distance data registered in the distance data shift array 2 (up to 10 in this case).
They are compared at the same time, and the comparison results are given to the shift control section 7. At the same time, the character code comparator 9 compares the character code set in the single character code register 4 with the character code registered in the character code shift array 1 all at once, and the comparison result is provided to the shift control section 7.

In the activated shift control section 7, each comparator 8,
Perform simple logical operations (described later) based on the comparison results in step 9.
Based on the results, each shift array 1.2 is operated to secure an insertion space for the character code and distance data in each register 4, 5, and then the character code and distance data are written in the insertion space. The candidate character codes and distance data as the final recognition result are passed through the character code register 4 and the distance data register 5 in order of decreasing distance (from the first stage) or increasing distance (from the 10th stage). The data can be sequentially read out onto the internal bus 3.

FIG. 2(a) is a block diagram of a shift array (character code shift array 1 or distance data shift array 2, both having the same configuration). 11 is a shift element for holding and shifting 1-bit data. Shift elements 11 arranged horizontally hold one character code or distance data, and are arranged in ten stages.

Data is shifted from the top row to the bottom row or from the bottom row to the top row. Shift element 1 in the same stage
1 are controlled all at once by the shift control section 7.

FIG. 2(b) shows the relationship between the input and output signal lines of one shift element. Here, the load data input line a is commonly connected to the character code register 4 or the distance data register 5 at each stage. In addition, shift data input/output lines
When the shift direction is from top to bottom, b becomes the input line and C becomes the output line, and when the shift direction is from bottom to top, this relationship is reversed, and the shift data input/output line of the 1st stage and the 10th stage The second shift data input/output line C is connected to the register 4 or 5, respectively. dh is a control/clock signal line. Note that the shift/load designation line f and the clock input line g are omitted in FIG. The direction in which the data is shifted from the upper stage to the lower stage or from the lower stage to the upper stage is determined by the value of the shift up/down signal line.

Each shift element 11 is as shown in FIG.

AND circuits 21-25, OR circuits 26, 27, inverter circuits 28-30, transfer gate circuits 31-33
, a flip-flop circuit 34. The signal names match those in FIG.

During load operation, data (character code or distance) from register 4 or 5 is input to load data input line a,
It is held in a flip-flop 34.

During a shift operation, if the shift up/down signal line is low, the data shifted and output from the flip-flop from the previous stage is input to the shift data input/output line, transferred to the flip-flop 34 of the relevant stage, and is transferred to the flip-flop until then. The data held in the shift data input/output line C
Output to. When the shift up/down signal line is high, this relationship is reversed. The control signal lines from the shift control unit 7 necessary for these operations include a shift mask line d to which a shift mask signal is input to control whether or not to perform a shift, and a shift mask line d to control data input from the outside. A load mask se to which a load mask signal is input, a load/shift line f to which a load/shift signal for selecting shift or load is input, a clock line g to which a clock is input, and the shift data input/output lines S, c. There is a shift up/down signal line to which a shift up/down signal for switching the input/output relationship (i.e., shift direction) is input.

FIG. 4 is a block diagram of the distance data comparator 8, with 41
indicates a distance data comparator element that performs a 1-bit comparison. The distance data comparator 8 has a total of 10 blocks each having a number of distance data comparator elements 41 connected as shown in the figure, each corresponding to the number of bits of one distance data, corresponding to each stage of the distance data shift array 2. There are steps,
- Operate in unison. FIG. 4(b) shows the relationship between input and output signals of one distance data comparator element 41.

As shown in FIG. 5, each distance data comparator element 41 is comprised of AND circuits 42-45, OR circuits 46, 47, and inverter circuits 48-50. The signal names match those in FIG. a is a comparison distance input line connected to the output of the corresponding bit of the distance data register 8, and f is a registered distance input line connected to the shift data input/output line of the corresponding bit of the corresponding stage of the distance data shift array 2. be. d is an output line that becomes effective when registered distance>comparison distance, and e is an output line that becomes effective when registered distance=comparison distance. b and C are input lines to which the output lines d and e of the distance data comparator element of the upper bit are connected, respectively.

FIG. 6(a) is a block diagram of the character code comparator 9, and 51 indicates a character code comparator element for performing 1-bit comparison of character codes. The character code comparator 9 has a block in which a number of character code comparator elements 51 equal to the number of bits of one character code are connected as shown, for a total of 10 stages corresponding to each stage of the character code shift array 1. Yes, - operate in unison. FIG. 6(b) shows the input/output signal relationship of one character code comparator element 51.

As shown in FIG. 7, each character code comparator element 51 is composed of AND circuits 52 to 54, an OR circuit 55, and inverter circuits 56 and 57.

The signal names match those in FIG. A is a comparison character code input line connected to the output of the corresponding bit of the character code register 4, and C is a registered character code input line connected to the shift data output line of the corresponding bit of the corresponding stage of the character code shift array 1. It is. d is an output line that becomes valid when the registered character code=comparison character code, and b is an input line to which the output line d of the upper bit character code comparator element is connected.

The function of the shift control section 7 is as follows. The target distance data set in the distance data register 5 is D,
The target character code set in the character code register 4 is C1, and the registered distance data and character code are each D i + ci (i = i to 10, registered data from 1st to 10th place, that is, shift arrays 1 and 2). ), and the result of the distance data comparator 8 is RD
□, the result of the character code comparator 9 is RC.

RD□ is valid when D□>D, and RC□ is C =
It becomes effective when C.

If RX,=RC machining ΦRX□+1 RX11=RC,+RC2+・+RC1゜, shift mask MS=RX,・RD Erode mask ML□= (RD machining 0RD=-,)・MS
.

Tazoshi RD becomes =0. Here, + represents logical sum, * represents logical product, ■ represents exclusive logical sum, and - represents negation.

During the sorting operation, the shift control unit 7 applies the shift mask MS□ and load mask ML signals determined by the above calculation to the corresponding input lines of the shift array 1.2, and sends the shift/load designation signal to shift designation. It is brought into the state (high state) and supplied with a clock, and then brought into a load designation state (low state) and supplied with a clock. Keep the shift up/down signal low. At the first clock (when specifying a shift), a certain row on shift arrays 1 and 2 is secured as a space to be inserted, and at the next clock (when specifying a load), target distance data and target character code are written to that space row. be included.

In addition, if the character codes overlap, the data with the larger distance will be deleted from shift array 1゜2 by the above operation (
shifted out).

Furthermore, before starting the sorting operation, the character code shift array 1 is cleared to 0 (assuming that there is no O as a character code), and the distance data shift array 2 is of course initialized with a reject distance threshold. 1st
FIG. 0 shows a processing flowchart of the shift control section 7 during the sorting operation.

When the sorting operation is completed and the results are to be read from each shift array 1 and 2, the shift/load designation signal is set to the shift designation state (high state), and the shift uptown signal is set to high or low. Give the clock. As a result, the sorted character codes and distance data of each shift array 1, 2 are read out to each register 4, 5 in order of decreasing distance or increasing distance. That is,
When the shift up/down signal is set high, the shift direction will be from bottom to top in Figure 2, and the data will be read out in order of decreasing distance.When the shift up/down signal is set low, the shift direction will be from top to bottom in Figure 2. , are read out in descending order of distance. This reading may be performed for only one of shift arrays 1 and 2.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, high-speed sorting of kanji OCR recognition results and efficient reading of the sorting results is possible with a relatively simple and regular circuit configuration suitable for integration into a single chip. A sorting device can be realized.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of a shift array, Fig. 3 is a circuit diagram of a shift element, and Fig. 4 shows the configuration of one stage of a distance data comparator. Block diagram: FIG. 5 is a circuit diagram of the distance data comparator element; FIG. 6 is a block diagram showing the configuration of one stage of the character code comparator; FIG. 7 is a circuit diagram of the character code comparator element; Figure 9 is an explanatory diagram of sorting recognition results.
This figure is an explanatory diagram of sorting of recognition results when character codes overlap, and FIG. 10 is a processing flow diagram of the shift control section during sorting operation. 1...Character code shift array, 2...Distance data shift array, 3...Internal bus, 4...Character code register, 5
... Distance data register, 7... Shift control unit, 8... Distance data comparator, 9... Character code comparator, 11... Shift element, 31... Distance data comparator element, 41...Character code comparator element. Toichi 817--Yo. -Cree, study → ki ψ n, yh-) Fumigud υ fu--

Claims (2)

[Claims] (1) A data shift array and a key shift array having a multi-stage configuration consisting of a combination of elements that can be loaded and shifted; means for simultaneously comparing each data held in each stage with the data held in said data holding means; and each key held in each stage of said key shift array and the key held in said key holding means. loading the data and keys held in the holding means for each stage of each shift array at the same time according to the comparison results of each comparison means; and loading the data and keys held in each shift array at the same time 1. A sorting device comprising: control means for arranging data and keys on each shift array according to the order of keys by sequentially controlling shifts of data and keys. (2) The control means, when reading out the sorting results to the outside, controls each shift array up and down, and reads out data and/or keys in ascending order of keys or in ascending order of keys. sorting device.